CN101246384A - Configuration initialization circuit and method thereof - Google Patents

Configuration initialization circuit and method thereof Download PDF

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Publication number
CN101246384A
CN101246384A CNA2007100052237A CN200710005223A CN101246384A CN 101246384 A CN101246384 A CN 101246384A CN A2007100052237 A CNA2007100052237 A CN A2007100052237A CN 200710005223 A CN200710005223 A CN 200710005223A CN 101246384 A CN101246384 A CN 101246384A
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Prior art keywords
configuration
input signal
signal
circuit
end points
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CNA2007100052237A
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Chinese (zh)
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CN101246384B (en
Inventor
陈建志
翁启舜
谢孟翰
李明哲
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Abstract

A configuration enactment circuit and its method comprises clock generator, a plurality of endpoints and detector which one end is coupled. The clock generator is used for generating a plurality of clock signal with different frequency input through endpoints. An input signal inputs into the detector through the coupled endpoint to make the detector input at least two bites configuration signal according to the frequency of the input signal, wherein, the input signal actually is one of a plurality of clock signal with different frequency.

Description

Configuration initialization circuit and method thereof
Technical field
The present invention relates to a kind of electronic circuit, particularly relate to a kind of configuration initialization circuit and method thereof.
Background technology
In general, each integrated circuit (IC) all can provide multiple operating mode.The operating mode of integrated circuit all is just to set to finish in electric power starting or replacement usually, to guarantee that integrated circuit is able to correct operating mode and comes into operation.When initialization, all be generally by operating voltage or the ground voltage specific lead-in wire (pin) to integrated circuit being provided, deciding the init state of integrated circuit.When therefore the operating mode that can provide when integrated circuit increased, for the setting in response to operating mode, the lead-in wire of integrated circuit also can and then increase.And in the design of integrated circuit, the lead-in wire of integrated circuit is many more, and relatively the volume of integrated circuit is also big more.Therefore, reduce the required pin count of integrated circuit initialization how and be still the actively target of research and development of engineers.
Summary of the invention
One of purpose of the present invention is to provide a kind of configuration initialization circuit and method thereof, uses to solve existing many restrictions of prior art and shortcoming.
One of purpose of the present invention is to provide a kind of configuration initialization circuit and method thereof, sets required pin count to reduce.
Therefore, for reaching above-mentioned purpose, the disclosed configuration initialization circuit of the present invention comprises end points and couples the detecting device of end points.
End points is used for receiving inputted signal, and detecting device is exported at least two configuration signaling according to this by detecting the received input signal of end points.At this, detecting device is output configuration data according to this by the frequency that detects input signal.Wherein, detecting device can comprise counter and the determining device that couples mutually.Counter is used for the umber of pulse of counting controling signal, produces count results according to this.Produce configuration data by determining device according to count results again.At this, determining device can be a food slicer, and it can be corresponding with a predetermined interval value with the count results of counter, to produce configuration data.
At this, the configuration data that configuration initialization circuit is exported comprises the configuration data that wherein all detecting devices produced.
Detecting device can be arranged in the integrated circuit (IC), and end points promptly can be the lead-in wire (pin) or the joint sheet (bonding pad) of integrated circuit.
At this, input signal one of can be in a plurality of clock signals of different frequencies, or is high level signal, or is low level signal.
And, can utilize a clock generator to produce a plurality of clock signals of different frequencies, and by other end points to export these clock signals.And this clock generator can be arranged in the integrated circuit equally, also or be arranged on the outside of integrated circuit.And the end points that is used for clock signal can be the lead-in wire or the joint sheet of integrated circuit, also or be the output terminal of clock generator.
Clock generator can comprise clock generating unit and frequency divider.At this, clock generating unit can produce a reference clock signal, and frequency divider then produces a plurality of clock signals of different frequencies according to this reference clock signal.
And, under the initializing set (that is, the configuration and setting pattern) and normal operation (that is, mode of operation) of integrated circuit, can share the transmission that end points carries out signal.Wherein, can utilize switch module or multiplexer to be coupled between clock generator or detecting device and the end points, to control the running of end points according to mode of operation.And can design a controller to produce the running that control signal is come gauge tap module or multiplexer.
The disclosed configuration and setting method of the present invention comprises: be provided for the end points of receiving inputted signal, and detect input signal and export configuration signalings corresponding with the frequency of input signal and at least two according to this.
Wherein, the step of output configuration signal comprises: the pulse data of counting input signal is to produce a count results; And according to count results to produce configuration data.
And, more can comprise the step of transmitting signal according to control signal via end points input input signal or transmission.
At this, input signal one of can be in the input signal of four different frequencies at least, also or one of can be at least two clock signals of different frequencies, high level signal and the low level signal.
Relevant characteristics and implementation of the present invention, conjunction with figs. is described in detail as follows as most preferred embodiment now.
Description of drawings
Fig. 1 is the summary calcspar according to the configuration initialization circuit of first embodiment of the invention;
Fig. 2 is the summary calcspar according to the configuration initialization circuit of second embodiment of the invention;
Fig. 3 is the running synoptic diagram of determining device according to an embodiment of the invention;
Fig. 4 is the summary calcspar according to the configuration initialization circuit of third embodiment of the invention;
Fig. 5 is the summary calcspar according to the configuration initialization circuit of fourth embodiment of the invention;
Fig. 6 is the summary calcspar according to the configuration initialization circuit of fifth embodiment of the invention;
Fig. 7 is the summary calcspar according to the configuration initialization circuit of sixth embodiment of the invention; And
Fig. 8 is the summary calcspar according to the configuration initialization circuit of seventh embodiment of the invention.
The reference numeral explanation
100...... circuit board
102...... integrated circuit
104...... connector
110...... clock generator
112...... clock generating unit
114...... frequency divider
131-13M...... detecting device
142...... counter
144...... determining device
150...... switch module
170...... multiplexer
190...... controller
N1 1-N1 N... end points
N2 1-N2 M... end points
CK 1-CK N... clock signal
Sc 1-Sc N... input signal
Dc 1-Dc M... configuration data
Df 1-Df N... transmit signal
Df 1-Df M... transmit signal
EN...... control signal
Vdd...... high level signal
GND...... low level signal
Embodiment
Below enumerate specific embodiment describing content of the present invention in detail, and with accompanying drawing as aid illustration.The symbol of mentioning in the explanation is with reference to reference numeral.
With reference to Fig. 1, be according to configuration initialization circuit of the present invention, it is used for producing the required configuration data Dc of configuration that sets integrated circuit (IC) 1-Dc M, include clock generator 110, a plurality of end points N1 1-N1 N, N2 1-N2 M(for example: joint sheet, circuit node etc.) and at least one detecting device 131-13M.Wherein, N, M are positive integers.
Clock generator 110 is used to produce a plurality of clock signal C K 1-CK NWherein, these clock signal C K 1-CK NCan have frequency inequality.Clock generator 110 is coupled with a plurality of end points N1 1-N1 N(for convenience of description, below being referred to as the signal end), these signal ends N1 1-N1 NExport a clock signal (that is clock signal CK, respectively 1-CK NOne of in).
Detecting device 131-13M also is coupled to an end points N2 respectively 1-N2 MThese end points N2 1-N2 M(for convenience of description, be called the first end points N2 1To M end points N2 M) receive an input signal Sc respectively 1-Sc M(for convenience of description, be called the first input signal Sc 1To M input signal Sc M), detect input signal Sc by detecting device 131-13M (for convenience of description, being called first detecting device 131) again to M detecting device 13M 1-Sc MAnd output configuration data Dc according to this 1-Dc M(for convenience of description, be called the first configuration data Dc 1To M configuration data Dc M).In other words, first detecting device 131 can detect the first end points N2 1The first received input signal Sc 1, and produce the first configuration data Dc according to this 1 Second detecting device 132 can detect the second end points N2 2The second received input signal Sc 2, and produce the second configuration data Dc according to this 2In like manner, M detecting device 13M can detect M end points N2 MReceived M input signal Sc M, and produce M configuration data Dc according to this M
At this, detecting device 131-13M is by detecting input signal Sc 1-Sc MFrequency, and output configuration data Dc according to this 1-Dc MThat is to say the configuration data Dc that detecting device 13M is exported MCorresponding to received input signal Sc MFrequency.
One embodiment, each input signal Sc MCan be clock signal C K NOne of in (wherein, N is at least 2), high level signal Vdd or low level signal GND; Another embodiment, each input signal Sc M(for example: N=1-4) one of can be in the different clock signal of four frequencies.
In addition, in one embodiment, each input signal Sc MBe one of in four kinds of unlike signals, each the configuration data Dc that is then produced MCan be two configuration data; If two detecting devices (for example: first detecting device 131 and second detecting device 132) are set, then first detecting device 131 and second detecting device 132 can be respectively according to the first end points N2 1With the second end points N2 2The first received input signal Sc 1With the second input signal Sc 2, and export two the first and second configuration data Dc 1, Dc 2So total configuration data of configuration initialization circuit output then is the four figures certificate.Certainly, if input signal Sc MBe the wherein a kind of of eight kinds of unlike signals, then configuration data Dc MIt is one or three configuration data; If two detecting devices are set, then total configuration data then is six bit data.On the practice, the needs of visual circuit are designed to input signal Sc MBe 2 KOne of them of kind unlike signal and M detecting device, then total configuration data can be K * M position.
In the present embodiment, by at these clock signal C K 1-CK NHave frequency inequality, so detecting device 131-13M can detect received input signal Sc 1-Sc MFrequency, produce configuration data Dc according to this 1-Dc M
One embodiment, each detecting device 13M can comprise counter 142 and determining device 144, as shown in Figure 2.Counter 142 is used to count input signal Sc MUmber of pulse, produce a count results according to this.Determining device 144 is again according to the count results of counter 142, and produces configuration data Dc MAt this, determining device 144 can be a food slicer (slicer), so that the count results of counter 142 is corresponding with a predetermined interval value, to produce configuration data Dc MIn addition, the order of connection of end points, counter and determining device can cooperate actual user demand and adjust.Seeing also Fig. 3, is the running synoptic diagram of determining device 144, and (a) and (b) figure is respectively the running figure at two kinds of clock signals of different frequencies.Certainly, if utilize high level signal or low level signal as a kind of input signal Sc M, then receive this input signal Sc MDetecting device 13M must the appropriateness its design of modification; One embodiment, when determining device 144 finds that the count value of counter 142 is 0 (, input signal Sc MUnderfrequency, may be high level or low level signal), then determining device 144 is directly exported input signal Sc MIn other words, as input signal Sc MBe high level signal and configuration data Dc MWhen being two bit data, the count value of counter 142 is 0, and the configuration data Dc of output MBe " 11 "; And as input signal Sc MBe low level signal and configuration data Dc MWhen being two bit data, the count value of counter 142 is 0, and the configuration data Dc of output MBe " 00 ".
At this, clock generator 110 can comprise clock generating unit 112 and frequency divider 114.Clock generating unit 112 can produce a reference clock signal and give frequency divider 114, and frequency divider 114 produces a plurality of clock signal C K again according to reference clock signal 1-CK NAt this, clock generating unit can be an oscillator or a phaselocked loop (PLL).
In one embodiment, under the configuration and setting pattern and mode of operation of integrated circuit, can share end points N1 according to configuration initialization circuit of the present invention 1-N1 NAnd/or N2 1-N2 MCarry out the transmission of signal, shown in the 4th, 5 and 6 figure.At this, can select circuit (for example: switch module 150 or multiplexer 170) to control end points N1 by one according to mode of operation 1-N1 NAnd/or N2 1-N2 MRunning.
With reference to Fig. 4, this switch module 150 is coupled to clock generator 110 and signal end N1 1-N1 NBetween; When integrated circuit carried out initializing set (that is, in the configuration and setting pattern), this switch module 150 can be with clock generator 110 and end points N1 1-N1 NConducting is so that the clock signal C K that clock generator 110 is produced 1-CK N, and via end points N1 1-N1 NAnd export; And when integrated circuit carries out normal operation (that is, in mode of operation), 150 of switch modules will be correlated with and be operated circuit (not shown) and end points N1 1-N1 NConducting is so that transmit signal Df 1-Df NVia end points N1 1-N1 NAnd transmit.In like manner, with reference to Fig. 5, the principle of work of multiplexer 170 is similar to the switch module 150 of Fig. 4.
With reference to Fig. 6, one selects circuit (for example: switch module 150 or multiplexer) also can be coupled in detecting device 131-13M and end points N2 1-N2 MBetween; When integrated circuit during in the configuration and setting pattern, switch module 150 conducting detector 131-13M and end points N2 1-N2 M, promptly first detecting device 131 is to M detecting device 13M difference conducting to the first end points N2 1To M signal end N2 M, so that input signal Sc M Export detecting device 13M to via end points; And when integrated circuit during in mode of operation, 150 of switch modules will be correlated with running circuit (not shown) and end points N2 1-N2 MConducting is with via end points N2 1-N2 MSignal Df is transmitted in transmission 1-Df MIn like manner, the principle of work of multiplexer is similar to the switch module 150 of Fig. 6.
Refer again to the 4th, 5 and 6 figure, can utilize a controller 190, to produce the running that control signal EN comes gauge tap module 150 (or multiplexer 170) and detecting device 140.In other words, at circuit start initial stage (that is, the configuration and setting pattern), controller 190 gauge tap modules 150 (or multiplexer 170) are to carry out configuration data Dc 1-Dc MInput and setting; Under mode of operation, controller 190 gauge tap modules 150 (or multiplexer 170) are so that working signal Df 1-Df N/ Df 1-Df MVia end points N1 1-N1 N/ N2 1-N2 MAnd transmit.Certainly, under mode of operation, these end points N1 1-N1 N/ N2 1-N2 MCan be the input end of another circuit or the I/O end of the output terminal of another circuit or another circuit.By shared end points N1 1-N1 N/ N2 1-N2 M, or both are to reach the purpose of saving lead-in wire (pin).
In one embodiment, clock generator 110 and detecting device 131-13M are arranged in the integrated circuit (IC) 102, these end points N1 1-N1 N, N2 1-N2 MCan be the lead-in wire (pin) or the joint sheet (bonding pad) of integrated circuit 102, as shown in Figure 7.In another embodiment, detecting device 131-13M is positioned at integrated circuit 102, and 110 of clock generators that is to say outside this integrated circuit 102, and integrated circuit 102 is arranged on the circuit board 100 with clock generator 110, as shown in Figure 8; At this moment, signal end N1 1-N1 NCan be the output terminal of clock generator 110, and second to M end points N2 1-N2 MBe the lead-in wire or the joint sheet of integrated circuit 102, and utilize connector 104 so that input signal Sc MBe these clock signal C K 1-CK NIn one of or be high level signal or for low level signal.The disclosed configuration and setting method of the present invention, its feature is similar to the disclosed configuration initialization circuit of the present invention, does not repeat them here.
Use the present invention, can utilize clock signal that integrated circuit promptly can produce according to original function as the required control signal of initializing set, or utilize the clock signal that originally promptly has on the circuit board as the required control signal of initializing set, suitably design down again, more can with high level signal (for example: operating voltage) or low level signal (for example: ground voltage) be used for, thereby can reduce pin count because of the required extra increase of initializing set as the required control signal of initializing set.
Though technology contents of the present invention discloses as above with preferred embodiment; so it is not to be used to limit the present invention; anyly have the knack of this skill person; do not breaking away from spirit of the present invention a little change and the retouching done; all should be covered by in the category of the present invention, so protection scope of the present invention is as the criterion when looking the present patent application claim person of defining.

Claims (19)

1. configuration initialization circuit comprises:
One clock generator is used to produce a plurality of clock signals, and wherein, the frequency of these a plurality of clock signals is inequality;
A plurality of signal ends are respectively applied for these a plurality of clock signals of output;
One first end points is used to receive one first input signal, and wherein, this first input signal one of comes down in these a plurality of clock signals, a high level signal and the low level signal; And
One first detecting device is coupled to this first end points, is used to detect the frequency of this first input signal and produce one first configuration data according to this, and this first configuration data is one at least two a configuration data.
2. configuration initialization circuit as claimed in claim 1, wherein, this first detecting device comprises:
One counter is used to count the umber of pulse of this first input signal, produces a count results according to this; And
One determining device is used for producing this first configuration data according to this count results.
3. configuration initialization circuit as claimed in claim 1, wherein, this clock generator comprises:
One clock generation unit is used to produce a reference clock signal; And
One frequency divider is coupled to this clock generating unit, is used for producing these a plurality of clock signals according to this reference clock signal.
4. configuration initialization circuit as claimed in claim 1 more comprises:
One selects circuit, is coupled between this signal end and this clock generator, to control the signal transmission of this signal end; And
One control circuit couples this selection circuit, to control the operation of this selection circuit.
5. configuration initialization circuit as claimed in claim 1 more comprises:
One selects circuit, is coupled between this first end points and this first detecting device, transmits this first input signal and with selectivity and transmits signal; And
One control circuit couples this selection circuit, to control the operation of this selection circuit.
6. configuration initialization circuit as claimed in claim 1, these a plurality of clock signals comprise at least two different frequencies.
7. configuration initialization circuit as claimed in claim 1, wherein, when first detecting device detects this first input signal for this high level signal or this low level signal, this first detecting device according to the level of this first input signal to export this first configuration data.
8. configuration initialization circuit comprises:
One first end points is used to receive one first input signal; And
One first detecting device is coupled to this first end points, is used to detect this first input signal and exports one first configuration signaling according to this, and this first configuration signaling is corresponding with the frequency of this first input signal, and this first configuration signaling is one at least two a configuration signaling.
9. configuration initialization circuit as claimed in claim 8, wherein, this first detecting device comprises:
One counter is used to count the umber of pulse of this first input signal, produces a count results according to this; And
One determining device is used for producing this first configuration data according to this count results.
10. configuration initialization circuit as claimed in claim 8 more comprises:
One selects circuit, is coupled between this first end points and this first detecting device, transmits this first input signal and with selectivity and transmits signal; And
One control circuit couples this selection circuit, to control the operation of this selection circuit.
One of 11. configuration initialization circuit as claimed in claim 8, wherein, in the input signal that this first input signal is at least four different frequencies.
12. configuration initialization circuit as claimed in claim 8, wherein, this first input signal is one of at least two clock signals of different frequencies, high level signal and the low level signal.
13. configuration initialization circuit as claimed in claim 12, wherein, when first detecting device detects this first input signal for this high level signal or this low level signal, this first detecting device according to the level of this first input signal to export this first configuration data.
14. a configuration and setting method comprises:
One first end points is provided, and this first end points is used to receive one first input signal; And
Detect this first input signal and export one first configuration signaling according to this, this first configuration signaling is corresponding with the frequency of this first input signal, and this first configuration signaling is one at least two a configuration signaling.
15. configuration and setting method as claimed in claim 14, wherein, this step of exporting one first configuration signaling comprises:
Count the umber of pulse of this first input signal, produce a count results according to this; And
According to this count results to produce this first configuration data.
16. configuration and setting method as claimed in claim 14 more comprises:
Import this first input signal via this first end points or transmit a transmission signal according to a control signal.
One of 17. configuration and setting method as claimed in claim 14, wherein, in the input signal that this first input signal is at least four different frequencies.
18. configuration and setting method as claimed in claim 14, wherein, this first input signal is one of at least two clock signals of different frequencies, high level signal and the low level signal.
19. configuration and setting method as claimed in claim 18, wherein, when detecting this first input signal, when finding this first input signal for this high level signal or this low level signal, then according to the level of this first input signal to export this first configuration data.
CN2007100052237A 2007-02-12 2007-02-12 Configuration initialization circuit and method thereof Active CN101246384B (en)

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Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826871B (en) * 2009-03-03 2015-12-09 瑞昱半导体股份有限公司 Frequency detecting device and method

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JP2002074996A (en) * 2000-08-25 2002-03-15 Mitsubishi Electric Corp Semiconductor integrated circuit
CN1378134A (en) * 2001-04-04 2002-11-06 英业达股份有限公司 Method for selecting note-book computer display panel using sound source signal
US7127631B2 (en) * 2002-03-28 2006-10-24 Advanced Analogic Technologies, Inc. Single wire serial interface utilizing count of encoded clock pulses with reset
CN1303429C (en) * 2003-04-15 2007-03-07 瑞昱半导体股份有限公司 Multiple socket detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826871B (en) * 2009-03-03 2015-12-09 瑞昱半导体股份有限公司 Frequency detecting device and method

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