CN101241380A - Analog/digital circuit - Google Patents
Analog/digital circuit Download PDFInfo
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- CN101241380A CN101241380A CNA2008100048679A CN200810004867A CN101241380A CN 101241380 A CN101241380 A CN 101241380A CN A2008100048679 A CNA2008100048679 A CN A2008100048679A CN 200810004867 A CN200810004867 A CN 200810004867A CN 101241380 A CN101241380 A CN 101241380A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/44—Arrangements characterised by circuits or components specially adapted for broadcast
- H04H20/46—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95
- H04H20/47—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems
- H04H20/48—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems for FM stereophonic broadcast systems
Abstract
A digital filter operates on the basis of a first clock having a first frequency. A stereo modulator operates on the basis of a second clock having a second frequency higher than the first frequency and being asynchronous. The stereo modulator performs a predetermined process on output data of the digital filter. A frequency modulator operates on the basis of a third clock having a third frequency whose origin is the same as that of the second clock, and performs frequency modulation on an output signal of the second digital computing unit. A sampling converter receives output data having the first frequency from the digital filter, converts a sampling frequency to data synchronized with the second clock, and outputs the obtained data to the stereo modulator.
Description
Technical field
The present invention relates to analog and digital circuit.
Background technology
In recent years, the radio broadcasting office of Ou Zhou the FM broadcasting office and the U.S. just sends additional informations such as text with the RDS (radio data system) in Europe or RBDS (RBW Radio Broadcast Data System) information of the U.S..If utilize RDS/RBDS, then in the receiver of vehicle-mounted radio, can use the title of the current broadcasting office that is just receiving, the various information such as type of music (patent documentation 1,2).
On the other hand, known have convert sound signal to the stereo mix signal, the frequency of utilization modulator carries out the FM transmitter (patent documentation 3～5) exported after the frequency modulation (PFM).If use the FM transmitter, then can be not via wiring ground transmit audio signals such as RCA cables, thereby can be used in the CD recorder changer (changer) of onboard audio and the transmission of the signal between automobile audio body (head unit) etc.Particularly in recent years, though hard disc audio equipment, storer audio frequency apparatus, the portable telephone terminal with music reproduction function are extensively popularized, but in the purposes of the music data of the miniaturized electronics such, being stored, also using the FM transmitter from the loudspeaker reproduction of fixed component stereo system etc.
Generally comprise filter section, stereo modulator, frequency modulator in the structure of FM transmitter.Filter section comprises pre-enhancing wave filter, low-pass filter.Stereo modulator carries out stereo modulation to the output of filter section, generates the stereo mix signal.Frequency modulator carries out frequency modulation (PFM) as modulation signal to carrier wave with the stereo mix signal.
Patent documentation 1: the spy opens flat 8-256135 communique
Patent documentation 2: the spy opens flat 8-191232 communique
Patent documentation 3: the spy opens flat 9-069729 communique
Patent documentation 4: the spy opens flat 10-013370 communique
Patent documentation 5: the spy opens flat 9-312588 communique
Non-patent literature 1:NATIONAL RADIO SYSTEMS COMMITTEE, " UNITED STATES RBDS STANDARD ", the U.S., on April 9th, 1998
Discussion is provided with digital to analog converter (hereinafter to be referred as the DA converter) between stereo modulator and frequency modulator in such circuit, the processing till proceeding to stereo modulation and handle with digital form, carry out warbled situation with analog form.
It generally is different carrying out the filter section of digital processing and the Action clock of stereo modulator.In addition, the Action clock of stereo modulator and analog to digital converter is also different.Under these circumstances, each circuit block with which frequency being moved, is an important problem improving S/N aspect circuit characteristics such as (signal to noise ratio (S/N ratio)), aberration rate.
Such problem is not only in the FM transmitter, and existing in the circuit of digital circuit and mimic channel at the same time is the problem that often occurs.
Summary of the invention
The present invention designs in view of such problem, and its overall purpose is to provide a kind of circuit that digital circuit and mimic channel are moved with suitable clock.
A scheme of the present invention relates to a kind of analog and digital circuit.This analog and digital circuit comprises: the 1st digital operation portion, move based on the 1st clock of the 1st frequency; The 2nd digital operation portion moves based on the 2nd clock of frequency ratio the 1st frequency height and asynchronous the 2nd frequency, and the output data of the 1st digital operation portion is applied predetermined processing; Mimic channel moves based on the 3rd clock of the 3rd frequency identical with the 2nd clock origin, and the output signal of the 2nd digital operation portion is applied predetermined processing; Sample conversion portion receives the output data of the 1st frequency from the 1st digital operation portion, and the conversion sample frequency converts the data with the 2nd clock synchronization to, exports to the 2nd digital operation portion.
So-called " moving based on certain clock " is meant the situation of the timing (timing) of this circuit by this clock control, for example comprises the situation by this clock control of inputing or outputing of signal.In addition, the inter-process of this circuit also can be used other clocks.
According to this scheme,, the 1st, the 2nd digital operation portion is moved with different suitable frequency by between the 1st digital operation portion of moving and the 2nd digital operation portion, sample conversion portion being set with asynchronous the 1st, the 2nd clock.
Can also comprise: frequency divider, with variable frequency dividing ratio M the 3rd clock of the 3rd frequency f 3 is carried out frequency division, generate the 2nd clock; The 2nd frequency f 2 based on the value of the 3rd frequency f the 3, the 1st frequency f 1, is set in the frequency dividing ratio configuration part.
The analog and digital circuit of a scheme can be the FM transmitter.In this FM transmitter, the 1st digital operation portion can comprise the digital filter that input signal is carried out filtering.The 2nd digital operation portion can comprise the output signal of digital filter is carried out stereo modulation, generates the digital stereo modulator of stereo mix signal.Mimic channel can comprise: digital to analog converter, carry out digital-to-analog conversion to stereo mixed signal; Frequency modulator as modulation signal, carries out frequency modulation (PFM) to the carrier wave corresponding with the 3rd clock with the stereo mix signal after the digital-to-analog conversion.
Can set the 1st frequency f 1 and the 2nd frequency f 2 makes following relational expression (1) and (2) set up.
fmax＜f2-f1×K×N-fin ......(1)
fmax＜f1×K×(N+1)-f2-fin ......(2)
Herein,
K: the over-sampling rate of sample conversion device
N: integer
Fin: the maximum frequency of input signal
Fmax: the maximum frequency of stereo mix signal.
The FM transmitter can also comprise: frequency divider, with variable frequency dividing ratio M the 3rd clock of frequency f 3 is carried out frequency division, and generate the 2nd clock; The frequency dividing ratio configuration part, the frequency dividing ratio M of setting frequency divider makes the 2nd frequency f 2 that obtains by f2=f3/M satisfy formula (1) and formula (2).
Should be noted that the combination in any of said structure important document or reconfigure etc. all effectively as the embodiment that is proposed, perhaps covered by the embodiment that is proposed.
In addition, this summary of the invention might not have been described whole essential feature, so the present invention can also be the sub-portfolio of these described features.
Description of drawings
Followingly with reference to the mode of accompanying drawing with example embodiment is described, these accompanying drawings are intended to example and are unrestricted, and unit identical in each accompanying drawing is marked with identical label, wherein:
Fig. 1 is the integrally-built block diagram of electronic equipment that the FM transmitter of embodiment of the present invention has been installed in expression.
(a) of Fig. 2 and (b) are the block diagrams of the FM transmitter different with the structure of the FM transmitter of present embodiment.
Fig. 3 is the circuit diagram of FM transmitter and peripheral circuit.
Embodiment
To describe the present invention based on preferred embodiment now, these preferred embodiments are not to be intended to scope of the present invention is limited, but the present invention is carried out illustration.All features of Miao Shuing and combination thereof might not be essential for purposes of the invention in an embodiment.
In this manual, so-called " state that components A is connected with part B " comprises the physically direct-connected situation of components A and part B, and the situation that is connected indirectly via the miscellaneous part that status of electrically connecting is not exerted an influence of components A and part B.
Similarly, so-called " parts C is set at the state between components A and the part B " except that components A and parts C or part B and situation that parts C directly links to each other, also comprises the situation that is connected indirectly via the miscellaneous part that status of electrically connecting is not exerted an influence.
Fig. 1 is the integrally-built block diagram of electronic equipment 200 that the FM transmitter 100 of embodiment of the present invention has been installed in expression.This electronic equipment 200 for example is portable telephone terminal, radio receiver, semiconductor storage formula audio player, has the representational role of audio frequency.Electric sound equipment conversion element itself outputs such as loudspeaker that the sound signal of being reproduced can carry from electronic equipment 200 or earphone.In addition, electronic equipment 200 can also carry out frequency modulation (PFM) to sound signal in order to reproduce the more audio frequency of high tone quality, sends to the outside in the mode of electric wave.The audio player of the enough outsides of user's energy receives the signal that is sent, and reproduces with higher tonequality.
The FM transmitter 100 of present embodiment is the analog-digital hybrid circuit that comprises mimic channel and digital circuit ground formation.FM transmitter 100 also can be the equipment that can also send character data etc. except that voice data.
Source of sound 110 output audio signal S1.For example, sound signal S1 receives broadcast wave and demodulation and the signal that obtains, also can be to reproduce the resulting signal of data that is stored in the storer, and its generation method is not done qualification.Source of sound 110 links to each other with FM transmitter 100 bus 114 in a predefined manner.For example bus 114 is I2S buses.At this moment, between source of sound 110 and FM transmitter 100, sound signal S1 is used as serial data and transmits.
The sound signal S1 that FM transmitter 100 receives from source of sound 110.FM transmitter 100 comprises digital circuit 10, mimic channel 30 and other circuit blocks, integrates on a Semiconductor substrate as analog-digital hybrid circuit.In addition, Fig. 1 only extracts main circuit block to represent that other circuit blocks have been omitted as appropriately.
The sound signal S1 that interface portion 12 receives from source of sound 110 via input terminal 102.Interface portion 12 received audio signal S1 output to digital filter 14 after being transformed into parallel data.Digital filter 14 comprises pre-emphasis circuit and low-pass filter.Digital filter 14 is the 1st digital operation portions, moves based on the 1st clock CK1 of the 1st frequency f 1.Clock generating unit 40 generates the 1st clock CK1 as work clock such as f1=32kHz, 44.1kHz, 48kHz.Clock generating unit 40 also can be arranged on the outside of FM transmitter 100.Digital filter 14 strengthens the component more than the cutoff frequency of sound signal S1, the unwanted high fdrequency component of removing sound signal S1 in low-pass filter in pre-emphasis circuit.Digital circuit 10 utilizes the 1st clock CK1 to latch the sound signal S1 that is imported, and the output of control signal is (timing) regularly.
Frequency divider 42 receives the 3rd clock CK3, with variable frequency dividing ratio M it is carried out frequency division, generates the 2nd clock CK2.That is, f2=f3/M sets up.
Frequency dividing ratio configuration part 46 is transfused to the value of the 1st frequency f the 1, the 3rd frequency f 3.Frequency dividing ratio M is set based on the value of the 1st frequency f the 1, the 3rd frequency f 3 in frequency dividing ratio configuration part 46.Frequency dividing ratio configuration part 46 also can possess the value of expression the 1st frequency f the 1, the 3rd frequency f 3 and the table of the corresponding relation of the frequency dividing ratio M that should set.This table also can be arranged on the outside of FM transmitter 100.
In addition, frequency dividing ratio configuration part 46 can be transfused to the 1st frequency f 1 and both values of the 3rd frequency f 3, perhaps also can only import any one of the 1st frequency f the 1, the 3rd frequency f 3, utilizes known frequency recently to obtain another person's frequency.About frequency dividing ratio M, narration in the back.
For guaranteeing the 1st clock CK1 based on the step that differs from one another, digital filter 14 and the coupling regularly of the signal transmitting and receiving between the stereo modulator 20 that the 2nd clock CK2 moves, between digital filter 14, stereo modulator 20, sample conversion portion 16 is set.
Over-sampling circuit 16a receives the output (to call sound signal S2 in the following text) of digital filter 14, carries out over-sampling.Setting over-sampling rate K makes the frequency of oversampled signals S3 near the 2nd frequency f 2 of the 2nd clock CK2.Below the output of over-sampling circuit 16a is called oversampled signals S3.
Be arranged on mimic channel 30, move based on the 3rd clock CK3 of the 3rd frequency f 3 as the back level of the stereo modulator 20 of the 2nd digital operation portion.The 2nd clock CK2 is to the result behind the 3rd clock CK3 frequency division, so we can say that the 2nd clock CK2 is identical with the origin of the 3rd clock CK3.
The output signal of 30 pairs of stereo modulators 20 of mimic channel applies predetermined processing.In the present embodiment, mimic channel 30 comprises DAC34, frequency modulator 32, power amplifier 36.DAC34 carries out digital-to-analog conversion to stereo mixed signal S5.Frequency modulator 32 is a modulation signal with the stereo mix signal S6 after the digital-to-analog conversion, and the carrier wave corresponding with the 3rd clock CK3 carried out frequency modulation (PFM).For example carrier wave can have the frequency after the 3rd frequency f 3 that makes the 3rd clock CK3 becomes doubly.
36 couples of modulated signals S7 from frequency modulator 32 outputs of power amplifier amplify, from lead-out terminal 104 outputs.Lead-out terminal 104 links to each other with antenna 112 via not shown match circuit.
Next, the relation of the 1st frequency f 1 and the 2nd frequency f 2 is described.Utilize the FM transmitter 100 of present embodiment, have the effect that to set the 1st frequency f the 1, the 2nd frequency f 2 independently of one another.But,, then can overlap noise if having no to set their frequency with concerning.For suppressing noise on noise, the 1st frequency f 1 and the 2nd frequency f 2 are set as follows.
Now the maximum frequency note of sound signal S1 is made fin1.Because common sound signal has frequency component about 0～15kHz, thus this moment fin1=15kHz.
In addition, will make fmax from the maximal value note of the frequency component of the stereo mix signal S5 of stereo modulator 20 output.When sound signal S1 had the frequency component of 0～15kHz, the maximum frequency fmax of the frequency component of stereo mix signal S5 became
fmax＝fs1+fin1。
Here, fs1 is the frequency of the subcarrier of stereo modulation.If establish fin1=15kHz, fs1=38kHz, then about fmax=53kHz.
In addition, when stereo modulator 20 carried out the modulation of RDS/RBDS data, the maximum frequency fmax of stereo mix signal S5 got following value.
In the modulation of RDS/RBDS data, the RDS/RBDS data of the subcarrier of frequency f s2=57kHz about by fin2=1～3kHz are carried out Modulation and Amplitude Modulation.Therefore, the maximum frequency fmax of Ci Shi stereo mix signal S5 becomes
fmax＝fs2+fin2。
Here, fin2 is the maximum frequency (about 3kHz) of RDS/RBDS data.Therefore, when stereo mix signal S5 comprised the RDS/RBDS data, its maximum frequency fmax became
About fmax=57+3=60kHz.
Be parameter preferably, become the relation of vertical (1), formula (2) between the 1st frequency f 1 and the 2nd frequency f 2 with the maximum frequency fmax of stereo mix signal S5, the maximum frequency fin=15kHz of input signal.
fmax＜f2-f1×K×N-fin ......(1)
fmax＜f1×K×(N+1)-f2-fin ......(2)
N is an integer herein.
Any one of the 1st frequency f 1 or the 2nd frequency f 2 is determined, and just can determine another person according to formula (1), formula (2).When the 1st frequency f 1 is set to any one of work clock 32kHz, 44.1kHz, 48kHz, determine the 2nd frequency f 2 according to this value.For example, when f1=44.1kHz, fmax=53kHz (no RDS/RBDS data), the 2nd frequency f 2 is set at 430～460kHz gets final product.
For obtaining needed the 2nd frequency f 2, the frequency dividing ratio M of frequency dividing ratio configuration part 46 control frequency dividers 42.That is, determine the 2nd frequency f 2 based on formula (1), formula (2).Set up between the 2nd frequency f 2 and the 3rd frequency f 3
f2＝f3/M ......(3)。
Therefore, as long as f1, f3 are determined, just can suitably set needed frequency dividing ratio M according to formula (1)～formula (3).
The structure and the action of FM transmitter 100 more than have been described.Below by with (a) of Fig. 2 and the FM transmitter of other structures (b) compare, make the effect of FM transmitter 100 of present embodiment clearer and more definite.
(a) of Fig. 2 and (b) are the FM transmitter 300a different with the structure of the FM transmitter 100 of present embodiment, the block diagram of 300b.
In the FM transmitter 300a of Fig. 2 (a), the 1st clock CK1 and the 2nd clock CK2 are become doubly common clock signal or frequency division and the signal that generates is synchronized with each other by not shown PLL.Therefore, no longer need the sample conversion device 16b of Fig. 1, over-sampling circuit 16a only is set.Other structures are identical substantially with Fig. 1.
In the FM transmitter 300a of Fig. 2 (a), the 3rd clock CK3 that offers the 2nd clock CK2 of stereo modulator 20 and offer frequency modulator 32 irrespectively is generated, so asynchronous.Therefore, non-synchronously carry out the stereo modulation of stereo modulator 20 and the frequency modulation (PFM) of frequency modulator 32, (α * f3-β * f2) is beat (beat) of composition, the characteristic variation with abs so produce.α, β are integers, and abs () represents signed magnitude arithmetic(al).
Different therewith, in the FM transmitter 100 of Fig. 1 of present embodiment, stereo modulator 20 and frequency modulator 32 are based on that the 2nd identical clock CK2 of origin and the 3rd clock CK3 move, so the generation that can suppress to beat can improve characteristic.
And then, in the FM of present embodiment transmitter 100, satisfy formula (1), formula and determine the 1st frequency f the 1, the 2nd frequency f 2 (2), so can suppress noise on noise well.When the 1st frequency f 1 is switched,, can set the 2nd frequency f 2 suitably according to the 1st frequency f 1 by frequency dividing ratio configuration part 46 is set between several values.
Specifically, if make fmax=60kHz, fin=15kHz, f1=48kHz, K=4, N=2, the scope that then is set at f2=460～500kHz gets final product.On the contrary, by setting the scope of the 2nd frequency f 2 suitably,, also can obtain desired characteristic even set the over-sampling rate K of over-sampling circuit 16a than the lowland.
Compare with the FM transmitter 300b of Fig. 2 (b), have the following advantages.
The FM transmitter 300b of (b) of Fig. 2 is different on the order of signal Processing with the FM transmitter 100 of Fig. 1.That is, in the FM transmitter 300b of Fig. 2 (b), sample conversion portion 16 is set in the back one-level of interface portion 12.Move as the digital filter 14 of the 1st digital operation portion with as the stereo modulator 20 of the 2nd digital operation portion the 2nd clock CK2 based on the 2nd frequency f 2 higher than the 1st frequency f 1.In the circuit of Fig. 2 (b), the 2nd clock CK2 and the 3rd clock CK3 are synchronous.According to this structure, stereo modulator 20 and frequency modulator 32 synchronously move, so can suppress to beat.But because stereo modulator 20 not only, digital filter 14 also moves with the 2nd higher frequency f 2, so that power consumption becomes is big.
Different therewith, FM transmitter 100 by present embodiment, the 1st digital operation portion (digital filter 14) is moved with the 1st relatively low frequency f 1, the 2nd digital operation portion (stereo modulator 20) is moved, so can reduce power consumption with the 2nd frequency f 2 that is higher than the 1st frequency f 1.
Fig. 3 is the circuit diagram of FM transmitter 100 and peripheral circuit.The IC of FM transmitter 100 has pin～No. 28 pin No. 1.
No. 1 pin, No. 2 pins, No. 7 pins, No. 8 pins, No. 27 pins are provided supply voltage VCC, the ground voltage GND at the mimic channel in the FM transmitter 100.12,13, No. 23 pins are provided supply voltage VDD, the ground voltage GND at digital circuit.
Biasing circuit (BIAS) 326 generates bias voltage, offers each circuit block of FM transmitter.Bias voltage carries out smoothing by the capacitor that links to each other with No. 3 pins.
Regulator (REG) 304 generates the employed voltage of internal logic of FM transmitter 100.From the voltage of No. 11 pin output by regulator 304 generations.
19～No. 21 pin connects source of sound 110 via the 12S bus.No. 19 pins are pins that data are used, and No. 20 pins are pins that clock is used, and No. 21 pins are pins that the LR clock is used.I2S bus interface oral area 306 and source of sound 110 transceive data.
17, No. 18 pins connect primary processor 120 via the I2C bus.No. 17 pins are pins that clock signal is used, and No. 18 pins are pins that data-signal is used.
No. 15 pins, No. 16 pins are connected with crystal vibrator 344.Oscillator 302 provides system clock.
No. 14 pin is transfused to chip enable signal.By chip enable signal, FM transmitter 100 switches the pattern and the energy-saving mode (power down mode) of work usually.Under energy-saving mode, internal circuit is closed, and current sinking almost becomes 0, becomes the state that does not receive the signal that comes the outside.
No. 22 pins are transfused to address of devices and select signal.Be when also having the LSI that controls with common I2C bus except that FM transmitter 100, they establish in order to distinguish.
No. 24 pins are test terminals.
No. 25 pins are that RDS is with triggering lead-out terminal.RDS digital modulator (RDS) 312 will send this situation of RDS signal to FM transmitter 100 from the outside and be notified to FM transmitter 100 circuit block in addition via No. 25 pins.
DAC316 carries out digital-to-analog conversion to the output of totalizer 314.By the amplitude of degree of modulation adjusting portion (MODADJ) 318 adjusting DAC316, offer PLL322 via No. 5 pins, outside capacitor C100, No. 6 pins.No. 6 pin is connected with recursive filter (LOOP FIL) 324 with No. 4 pins (PLL time constant switched terminal) via capacitor C102.By the capacitor C102 that is connected with No. 4 pins and the not shown resistance of FM transmitter 100 inside, form recursive filter 324, according to being to change the capacitance of capacitor C102 or changing resistance value regulates time constant.
VCO320 by with from the vibration of the signal correspondent frequency of PLL, the signal after the FM modulation is offered divider (divider) (DIV) 328.VCO320 connects varactor and inductor via 9, No. 10 pins.
The corresponding relation of Fig. 1 and Fig. 3 is as follows.
Interface portion 12: interface portion 306
Digital filter 14: not shown
Sample conversion portion 16: not shown
Stereo modulator 20: stereo modulator 310
DAC34：DAC316
Frequency modulator 32: degree of modulation adjusting portion 318, recursive filter 324, PLL322, VCO320
Power amplifier 36: divider 328, power amplifier 330,332
More than based on embodiment the present invention has been described.This embodiment is an illustration, and the combination that those skilled in the art can understand its each structure important document and variety of processes can have various variation, and these variation are also contained in the scope of the present invention.The following describes such variation.
In embodiment, be example with FM transmitter 100, the 1st digital operation portion that illustrated is that digital filter 14, the 2 digital operation portions are stereo modulators 20, the processing that mimic channel carried out is warbled situation, but the invention is not restricted to this.That is, the 1st digital operation portion, the 2nd digital operation portion, mimic channel can carry out other processing respectively.If it is, then as described below with FM transmitter 100 abstracts, the generalization of embodiment.
The 1st digital operation portion (14) moves based on the 1st clock of the 1st frequency f 1.The 2nd digital operation portion (20) moves based on the 2nd clock f2 than the 1st frequency f 1 height and asynchronous the 2nd frequency f 2.The 2nd digital operation portion (20) applies predetermined processing to the output data of the 1st digital operation portion (14).Mimic channel (32) moves based on the 3rd clock CK3 of the 3rd frequency f 3 identical with the 2nd clock CK2 origin.Mimic channel (30) applies predetermined processing to the output signal of the 2nd digital operation portion (20).Sample conversion portion (16) is from the output data of the 1st digital operation portion 14 receptions the 1st frequency f 1, and the conversion sample frequency converts to and the 2nd clock CK2 data in synchronization, exports to the 2nd digital operation portion (20).
By this circuit, can set the operating frequency of the 1st, the 2nd digital operation portion independently, can make the 2nd digital operation portion and frequency modulator synchronization action again.
Although used particular term to describe the preferred embodiments of the present invention, this description only is used for illustrative purposes, and should be understood to, and under the situation of essence that does not depart from claims and scope, can make amendment and change.
Claims (5)
1. an analog and digital circuit is characterized in that, comprising:
The 1st digital operation portion moves based on the 1st clock of the 1st frequency;
The 2nd digital operation portion moves based on the 2nd clock of and asynchronous the 2nd frequency higher than above-mentioned the 1st frequency, and the output data of above-mentioned the 1st digital operation portion is applied predetermined processing;
Mimic channel moves based on the 3rd clock of the 3rd frequency identical with above-mentioned the 2nd clock origin, and the output signal of above-mentioned the 2nd digital operation portion is applied predetermined processing; And
Sample conversion portion receives the output data of the 1st frequency from above-mentioned the 1st digital operation portion, and the conversion sample frequency converts the data with above-mentioned the 2nd clock synchronization to, exports to above-mentioned the 2nd digital operation portion.
2. analog and digital circuit according to claim 1 is characterized in that, also comprises:
Frequency divider carries out frequency division with variable frequency dividing ratio M to above-mentioned the 3rd clock of the 3rd frequency f 3, generates above-mentioned the 2nd clock; With
Above-mentioned the 2nd frequency f 2 based on the value of above-mentioned the 3rd frequency f 3 and above-mentioned the 1st frequency f 1, is set in the frequency dividing ratio configuration part.
3. analog and digital circuit according to claim 1 is characterized in that:
Above-mentioned analog and digital circuit is the FM transmitter;
Above-mentioned the 1st digital operation portion comprises the digital filter that input signal is carried out filtering;
Above-mentioned the 2nd digital operation portion comprises the output signal of above-mentioned digital filter is carried out stereo modulation, generates the digital stereo modulator of stereo mix signal;
Above-mentioned mimic channel comprises
Digital to analog converter, to above-mentioned stereo mix signal carry out digital-to-analog conversion and
Frequency modulator as modulation signal, carries out frequency modulation (PFM) to the carrier wave corresponding with above-mentioned the 3rd clock with the above-mentioned stereo mix signal after the digital-to-analog conversion.
4. analog and digital circuit according to claim 3 is characterized in that:
Above-mentioned the 1st frequency f 1 and above-mentioned the 2nd frequency f 2 are set to following relational expression (1) and (2) are set up, and wherein K is the over-sampling rate of above-mentioned sample conversion device, and N is an integer, and fin is the maximum frequency of input signal, and fmax is the maximum frequency of stereo mix signal,
fmax＜f2-f1×K×N-fin ......(1)
fmax＜f1×K×(N+1)-f2-fin ......(2)。
5. analog and digital circuit according to claim 4 is characterized in that, also comprises:
Frequency divider carries out frequency division with variable frequency dividing ratio M to above-mentioned the 3rd clock of frequency f 3, generates above-mentioned the 2nd clock; With
The frequency dividing ratio M of above-mentioned frequency divider is set in the frequency dividing ratio configuration part, makes the 2nd frequency f 2 that obtains by f2=f3/M satisfy formula (1) and formula (2).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP031016/07 | 2007-02-09 | ||
| JP2007031016 | 2007-02-09 | ||
| JP309116/07 | 2007-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101241380A true CN101241380A (en) | 2008-08-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100048679A Pending CN101241380A (en) | 2007-02-09 | 2008-02-05 | Analog/digital circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4892466B2 (en) |
| CN (1) | CN101241380A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016178601A (en) | 2015-03-23 | 2016-10-06 | セイコーエプソン株式会社 | Data processing circuit, circuit for physical quantity detection, physical quantity detection device, electronic equipment, and mobile body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0377542A (en) * | 1989-08-19 | 1991-04-03 | Shimadzu Corp | X-ray ct apparatus |
| JP3849892B2 (en) * | 1996-09-09 | 2006-11-22 | ソニー株式会社 | Filter device and wireless communication terminal device |
| JP3949081B2 (en) * | 2003-06-09 | 2007-07-25 | 株式会社東芝 | Sampling frequency converter |
-
2007
- 2007-11-29 JP JP2007309116A patent/JP4892466B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| JP4892466B2 (en) | 2012-03-07 |
| JP2008219859A (en) | 2008-09-18 |
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