CN101234255A - Counter system for multiple game machines network statistics marks - Google Patents
Counter system for multiple game machines network statistics marks Download PDFInfo
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- CN101234255A CN101234255A CNA2007100325094A CN200710032509A CN101234255A CN 101234255 A CN101234255 A CN 101234255A CN A2007100325094 A CNA2007100325094 A CN A2007100325094A CN 200710032509 A CN200710032509 A CN 200710032509A CN 101234255 A CN101234255 A CN 101234255A
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Abstract
The invention discloses the counter system used for summing up scores of inter-connecting a plurality of game machines, which can collect the upper scores and the lower scores of each game machine so as to converse and sum up the collected data, and the invention can display former turnovers in terms and accurately collect the scoring results of each game machine in time, which then converse the results into turnover according to the proportion which has been set, and the encrypting treatment can be given to statistic result data which can be printed out by a bill printer. The counter adopts an AVR single chip microcomputer as a core component, which comprises at least one host computer with an ATmega16L single chip microcomputer as the core, and a plurality of game machines which are sub-computers with ATmega8 single chip microcomputers as the core correspondingly, each sub-computer is in serial connection, which can count the scores with a serial port communication mode and converse the results into turnover data according to each conversing ratio set by the computer then send the data to the host computer for gathering treatment.
Description
Technical field
The present invention relates to a kind of counter system of multiple game machines network statistics marks, be applied to present various score game machines.
Background technology
At present, the game machine in each play place all adopts the mode of score value to calculate player's operation note, and these game machines all are to go up by simple mechanical count table or digital accumulator statistics to divide and following fractional value, and function is single addition.This mode needs a large amount of craft that the count value of each game machine is converted and is aggregated into the turnover, and manual statistics both had been easy to make mistakes and also has been easy to cause managerial dispute.
It is core that the present invention adopts the AVR single-chip microcomputer, forms the counter of multiple game machines network statistics marks with main frame and the next slave serial connection.The technology of required employing comprises singlechip technology, the network communications technology and relevant software engineering.Independently calculate at current each game machine and to divide and following minutes and the manual deficiency that is converted into the turnover, this counter branch and be converted into the turnover of uniting automatically of can realizing networking.
Summary of the invention
Can not correctly in time add up the deficiency of various game machine score situations in order to overcome existing games system counter, the present invention has designed a kind of counter system of multiple game machines network statistics marks, comprises some the next slave and at least one main frames that the signal tabulate statistics shows that are used for the signal acquisition process of each game terminal.Wherein the next slave not only can correctly be gathered the score situation of each game machine unit, and can be to the data of gathering according to the processing that converts of the different score pattern of different game machines, and the data of finishing dealing with are sent to main frame.Main frame then receives the data that each the next slave sends over by the communications protocol of agreement, and carries out aggregation process and demonstration.
The technical solution adopted for the present invention to solve the technical problems is: it is core that this games system counter adopts 8 AVR single-chip microcomputers of Low-Power CMOS, adopt multi-computer system to constitute distributed control, main frame mainly manages, the next slave is finished the collection and the processing of game terminal score signal, comprises at least one main frame and some the next slaves (the next slave can add as required).The single-chip microcomputer that main frame adopts is ATmega16L, and the single-chip microcomputer that the next slave adopts is ATmega8, is equipped with the RS-232C transmitter-receiver between main frame and the next slave and carries out long-distance transmissions, and its communication pattern The general frame as shown in Figure 1.Below mainly be to set about setting forth each functional module of this games system counter from hardware design and software design aspect.
One, system hardware circuit
(1) the master-plan block diagram of main frame is as shown in Figure 2:
1. power circuit
The AVR series monolithic is the single-chip microcomputer of wide voltage-type, and (as ATmega16L) voltage range of model suffix band L is: 2.7V 5.5V, (as the ATmega16) voltage range with L is not 4.5V 5.5V.All circuit of native system main frame all adopt the design of 5V voltage, and core controller adopts the ATmega16L single-chip microcomputer.The power circuit of main frame as shown in Figure 3.
For guaranteeing the system stability power supply, should be from the voltage of J1 input between the 6V to 12V, too small or excessive voltage all can cause system's irregular working.Behind correct connection power supply, the POWER indicator lamp should be lighted.
2. power down protection circuit
The analog comparator of ATmega16L compares the value of anodal AIN0 and the value of negative pole AIN1, and when the voltage on the voltage ratio negative pole AIN1 on the AIN0 wanted high, the output ACO of analog comparator was set; Native system utilizes this function of analog comparator; realize the power down Data Protection; big capacitor C 9 is to be used for keeping the data that will preserve when cutting off the power supply to store EPPROM into; need preserve 10 byte datas during the power down of native system main frame; the EPPROM that writes a byte is for up to 8mS, so power filtering capacitor should not be too little.
The analog comparator of ATmega16L compares the value of anodal AIN0 and the value of negative pole AIN1.When the voltage on the voltage ratio negative pole AIN1 on the AIN0 wanted high, the output ACO of analog comparator was set.Native system utilizes this function of analog comparator, realizes the power down Data Protection, and the power down protection circuit as shown in Figure 4.
3.DS1302 clock chip circuit
DS1302 is the clock chip of the band trickle charge of DALLS company release, contains a real-time clock/calendar and 31 byte static RAM (SRAM)s, communicates by simple serial line interface and single-chip microcomputer.Real-time clock/calendar circuit provide second, branch, the time, day, Month And Year information, every month the fate and the fate in leap year can be adjusted automatically, clock operation can be adopted 24 or 12 hours forms by AM/PM indication decision, can adopt the mode of synchronous serial to communicate between DS1302 and the single-chip microcomputer simply, only need use three IO mouth lines.Circuit theory diagrams as shown in Figure 5.
Power down leaves battery tray and the battery of 3.6V on the native system main frame, so in case after the clock operation, can not stop yet.The function of this module in main frame mainly is date, the time that is used for calibration system current date, time and record employee changing shifts.
4.12864-12 LCD interface circuit
The liquid crystal that the LCD MODULE of native system main frame adopts is HS12864-12_V4.0, and this liquid crystal has two kinds of parallel drive mode and driven in series modes, and the native system main frame adopts the driven in series mode, and its interface circuit as shown in Figure 6.
Variable resistor VR2 among Fig. 6 is used for regulating the contrast of liquid crystal, and pin LEDA and LEDK ground connection and power supply respectively make the backlight Chang Liang of liquid crystal.Pin PSB ground connection represents to adopt the driven in series mode, the driven in series mode only takies three IO mouths of single-chip microcomputer, be respectively the chip selection signal (LCD_CS) of serial, the data port (LCD_SID) of serial, the synchronised clock (LCD_CLK) of serial, all directly link to each other with the IO mouth of single-chip microcomputer.
5. mini-printer interface circuit
The mini-printer that the native system main frame uses is: Galaxy Miniature Printer YH245B, adopt the parallel drive mode, and its parallel interface is as shown in Figure 7.
These signals of PRINT_D1 to PRINT_D8 among Fig. 7 are represented first to the 8th signal of parallel data respectively, and each signal is " height " level when its logic is " 1 ", are " low " level when logic is " 0 ".PRINT_STB is the data gate trigger pulse, reads in data during rising edge.PRINT_BUSY represents that for " height " level printer just " is doing ", can not receive data.
6. keyboard circuit
The native system main frame has adopted 4 * 4 dynamic keyboard scanning circuits, as shown in Figure 8.
Dynamic scan principle: the input port is changed to high level, putting delivery outlet then respectively successively is low level (once having only a delivery outlet is low level), and when certain certain row delivery outlet is low level, judge whether the level of input port has low level, this is called single pass.If a button is pressed for that row keyboard that is scanned, the level that then has the input port is dragged down, and judges it is which button is pressed according to the state of input port then actually.
Because the IO mouth of AVR single-chip microcomputer all has selectable internal pull-up resistor, so the pull-up resistor of keyboard circuit input port is omitted.
7.RS232 serial port circuit
Native system adopts the serial communication mode to carry out transfer of data, if adopt the Transistor-Transistor Logic level of singlechip directly to transmit information, its transmission range generally is no more than 1.5m, therefore the native system main frame communicates with the next slave employing RS-232C standard and is connected, signal adopts the RS-232C level transmissions, electrical level transferring chip adopts MAX232, and its circuit as shown in Figure 9.
In sum, the master-plan schematic diagram of main frame as shown in figure 10.
(2) the master-plan block diagram of the next slave is as shown in figure 11:
1. power circuit
The next slave is as the expansion board of each game terminal, and power supply is drawn+5V from game terminal, uses for the next slave through too small capacitor filtering.When certain game terminal energising was used, the POWER indicator lamp of corresponding the next slave of expansion board should be lighted.
2. power down protection circuit
The power down protection circuit of the next slave is the same with the mentality of designing of main frame, as shown in Figure 4.
3.1602A LCD interface circuit
The liquid crystal that the LCD MODULE of the next slave of native system adopts is 1602A_V1.0, and this liquid crystal has two kinds of data wire 4 line transmission means and data wire 8 line transmission means, and the native system main frame adopts data wire 4 line transmission means, and its interface circuit as shown in figure 12.
Variable resistor VR1 among Figure 12 is used for regulating the contrast of liquid crystal, pin LEDA and LEDK connect respectively power supply and make the backlight Chang Liang of liquid crystal.LCD_D4 to LCD_D7 is the high 4 of liquid crystal data wire, and LCD_RS is data/command selection end (H/L), and LCD_EN is an enable signal, and R/W is read/write selecting side (H/L), and ground connection represents only to be used to write data/order liquid crystal.
4. game terminal score signal acquisition circuit
The topmost function of the next slave of native system is exactly the collection of game terminal score signal, and its circuit as shown in figure 13.Because the score signal voltage that extracts of game terminal is up to 12V, and AVR single-chip microcomputer IO port generally can only bear the following voltage of 5.5V, therefore, the score signal by the potentiometer dividing potential drop after filtering just be input to the external counting port of AVR single-chip microcomputer.
5. keyboard circuit
The button inputting circuits of the next slave of native system only needs three buttons, the S1 button is used to enter change conversion scale pattern or does to reduce key and use when changing the conversion scale pattern, the S2 button is used to enter to be checked the conversion scale pattern or make to increase key usefulness when changing the conversion scale pattern, the S3 button is as acknowledgement key, and its circuit as shown in figure 14.
6.RS232 serial port circuit
The RS232 serial port circuit of the next slave is the same with the mentality of designing of main frame, as shown in Figure 9.
In sum, the master-plan schematic diagram of the next slave as shown in figure 15.
Two, Design of System Software
Main each functional module that realizes of host software design is as follows:
(1) system is provided with function
1. adopt 12864-15 liquid crystal Chinese and English to show.
2. adopt the menu preference pattern to carry out man-machine interactive operation.
3. adopt Chinese and English menu to switch and select operation.
(2) statistical summaries function
1. the data that each the next slave is transmitted are carried out tabulate statistics, form the current turnover.
(3) send command function
1. can send clear command to each the next slave, will divide on the next slave of correspondence and following minute statistics zero clearing.
(4) real-time clock function
1. calibration system current date and time.
2. write down the date and time of employee's changing shifts.
(5) encryption function
1. encryption function comprises person in charge's password (at least 8) and employee's password (at least 4).
2. being responsible for password and employee's password can change as required.The person in charge can change own and employee's password, and employee's password distributes by being responsible for.The employee can not change the password of oneself.
3. distinguish the person in charge and employee's authority.The person in charge can check statistics, also can delete or the zero clearing data.The employee only checks the statistics authority.
4. statistics is encrypted and check.
(6) trading record operating function
1. check trading record on the same day: comprise that branch business record, following minutes business write down and the same day profit, need employee's password or person in charge's password just can check.
2. check historical trading record: can check historical trading record of nearest 10 phases, the date and time mark is arranged, need employee's password or person in charge's password just can check.
3. the historical trading record of zero clearing: can historical trading record of nearest 10 phases of zero clearing, but and going up of each slave computer of zero clearing divide and following minute historical record.Have only the person in charge just can carry out this operation.
4. deleting history trading record: the person in charge can be to historical trading record selectively removing.
(7) printing function
1. can print the trading record of nearest 10 phases, comprise date and time.
2. can print Chinese and English data message according to the language that menu is selected.
(8) button changes the phase function
1. by button, the input password was realized the storage of current-period data information when the employee changed shifts, and new first phase data are started from scratch and added up.
(9) power-down protection
1. current going up can be divided statistics during power down, add up in following minute and the turnover stores among the EEPROM.
2. when re-powering data are read from EEPROM, recover the preceding numerical value of power down.
(10) communication function
1. realize by serial ports and special-purpose communication interface (MAX232) and many next from captain's distance communication (at least 30 meters).
(11) reset function
1. setting resets to the original default setting to host computer system, comprises the person in charge and employee's password zero clearing.
The main function that realizes of the next slave software design is as follows:
(1) video data function
1, fractional value about 1602 liquid crystal displays, the demonstration that adds up can be by the control command zero clearing of main frame.
2, switch the conversion scale that shows between the corresponding game machine scoring value and the turnover by button.
(2) signals collecting function
1. pass through the signals collecting interface from each game machine collection score statistical signal.
2. collect the signal of divided data up and down of each game machine like clockwork.
(3) change conversion scale function
1. can change the conversion scale of the current scoring value of each game machine and the turnover, and change scope and precision reach 2 significant digits.
(4) power-down protection
1. can store current last score value and following score value into EEPROM during power down.
2. when re-powering data are read from EEPROM, recover the preceding numerical value of power down.
(5) communication function
1. realize and the long distance communication of main frame (at least 30 meters) by serial ports and special-purpose communication interface (MAX232).
2. the turnover data after converting can be passed to main frame gathers.The precision of transmission data is 2 significant digits at least.
(6) scaling function
1. the score data-signal of gathering statistics can be converted into the turnover by the conversion scale that is provided with.
The invention has the beneficial effects as follows that this counter system is applied to present various score game machines, the last score value that can gather each game machine and following score value, and then the data of collection are converted and add up, and can show the historical turnover by stages.
Description of drawings
Fig. 1 is a system communication pattern The general frame.Fig. 2 is the master-plan block diagram of system host.
Fig. 3 is the power circuit diagram of system host.Fig. 4 is the power down protection circuit diagram of system host.
Fig. 5 is the DS1302 clock chip circuit diagram of system host.
Fig. 6 is the 12864-12 LCD interface circuit diagram of system host.
Fig. 7 is the mini-printer interface circuit figure of system host.Fig. 8 is the keyboard circuit figure of system host.
Fig. 9 is the RS232 serial port circuit figure of system host.Figure 10 is the master-plan schematic diagram of system host.
Figure 11 is the master-plan block diagram of the next slave of system.
Figure 12 is the 1602A LCD interface circuit diagram of the next slave of system.
Figure 13 is the next slave game terminal score signal acquisition circuit figure of system.
Figure 14 be the next slave of system keyboard circuit figure.Figure 15 is the master-plan schematic diagram of the next slave of system.
The specific embodiment
It is core that this games system counter adopts 8 AVR single-chip microcomputers of Low-Power CMOS, adopt multi-computer system to constitute distributed control, main frame mainly manages, the next slave is finished the collection and the processing of game terminal score signal, comprises 1 main frame and 30 the next slaves (the next slave can add as required).The single-chip microcomputer that main frame adopts is ATmega16L, and the single-chip microcomputer that the next slave adopts is ATmega8, is equipped with the RS-232C transmitter-receiver between main frame and the next slave and carries out long-distance transmissions, and its communication pattern The general frame as shown in Figure 1.Below mainly be to set about setting forth each functional module of this games system counter from hardware design and software design aspect.
The concrete enforcement of native system can be divided into two parts: upper main frame and the next slave.
(1) upper main frame.The master-plan block diagram is as shown in Figure 2:
1. power circuit
The AVR series monolithic is the single-chip microcomputer of wide voltage-type, and (as ATmega16L) voltage range of model suffix band L is: 2.7V 5.5V, (as the ATmega16) voltage range with L is not 4.5V 5.5V.All circuit of native system main frame all adopt the design of 5V voltage, and core controller adopts the ATmega16L single-chip microcomputer.The power circuit of main frame as shown in Figure 3.
For guaranteeing the system stability power supply, should be from the voltage of J1 input between the 6V to 12V, too small or excessive voltage all can cause system's irregular working.3 port power interface JP5 connect external power source, and inner the 1st electrode line connects the diode of IN4148, and the 2nd and the 3rd line is made minus earth altogether; Diode connects one 7805 voltage-stabiliser tube, and outside 9V voltage voltage stabilizing is become inner 5V operating voltage, and the voltage-stabiliser tube two ends respectively connect two filter capacitors, all are 220 μ F and 0.1 μ F; Behind correct connection power supply, the POWER indicator lamp should be lighted.
2. power down protection circuit
The analog comparator of ATmega16L compares the value of anodal AIN0 and the value of negative pole AIN1, and when the voltage on the voltage ratio negative pole AIN1 on the AIN0 wanted high, the output ACO of analog comparator was set; Native system utilizes this function of analog comparator; realize the power down Data Protection; big capacitor C 9 is to be used for keeping the data that will preserve when cutting off the power supply to store EPPROM into; need preserve 10 byte datas during the power down of native system main frame; the EPPROM that writes a byte is for up to 8mS, so power filtering capacitor should not be too little.
The analog comparator of ATmega16L compares the value of anodal AIN0 and the value of negative pole AIN1.When the voltage on the voltage ratio negative pole AIN1 on the AIN0 wanted high, the output ACO of analog comparator was set.Native system utilizes this function of analog comparator, realizes the power down Data Protection, and the power down protection circuit as shown in Figure 4.
3.DS1302 clock chip circuit
DS1302 is the clock chip of the band trickle charge of DALLS company release, contains a real-time clock/calendar and 31 byte static RAM (SRAM)s, communicates by simple serial line interface and single-chip microcomputer.Real-time clock/calendar circuit provide second, branch, the time, day, Month And Year information, every month the fate and the fate in leap year can be adjusted automatically, clock operation can be adopted 24 or 12 hours forms by AM/PM indication decision, can adopt the mode of synchronous serial to communicate between DS1302 and the single-chip microcomputer simply, only need use three IO mouth lines.Circuit theory diagrams as shown in Figure 5.
Power down leaves battery tray and the battery of 3.6V on the native system main frame, so in case after the clock operation, can not stop yet.The function of this module in main frame mainly is date, the time that is used for calibration system current date, time and record employee changing shifts.SCLK among the clock chip DS1302, RST, three clock chip control of I/O pin is received the pin of ATmega16L, and VCC1 connects the 3.3-3.6V battery, and VCC2 connects operating voltage; Clock chip connects the wrist-watch crystal oscillator of a 32.768KHz, for chip provides reference pulse.
4.12864-12 LCD interface circuit
The liquid crystal that the LCD MODULE of native system main frame adopts is HS12864-12_V4.0, and this liquid crystal has two kinds of parallel drive mode and driven in series modes, and the native system main frame adopts the driven in series mode, and its interface circuit as shown in Figure 6.
Variable resistor VR2 among Fig. 6 is used for regulating the contrast of liquid crystal, and pin LEDA and LEDK ground connection and power supply respectively make the backlight Chang Liang of liquid crystal.Pin PSB ground connection represents to adopt the driven in series mode, the driven in series mode only takies three IO mouths of single-chip microcomputer, be respectively the chip selection signal (LCD_CS) of serial, the data port (LCD_SID) of serial, the synchronised clock (LCD_CLK) of serial, all directly link to each other with the IO mouth of single-chip microcomputer.
5. mini-printer interface circuit
The mini-printer that the native system main frame uses is: Galaxy Miniature Printer YH245B, adopt the parallel drive mode, and its parallel interface is as shown in Figure 7.
These signals of PRINT_D1 to PRINT_D8 among Fig. 7 are represented first to the 8th signal of parallel data respectively, and each signal is " height " level when its logic is " 1 ", are " low " level when logic is " 0 ".PRINT_STB is the data gate trigger pulse, reads in data during rising edge.PRINT_BUSY represents that for " height " level printer just " is doing ", can not receive data.The 11st pin senses printer modes in the 25 needle printer interfaces received an I/O pin of ATmega16L chip; The 1st pin is enable pin, also receives an I/O pin of ATmega16L chip; The 2-8 pin is a data output.
6. keyboard circuit
The native system main frame has adopted 4 * 4 dynamic keyboard scanning circuits, as shown in Figure 8.
Dynamic scan principle: the input port is changed to high level, putting delivery outlet then respectively successively is low level (once having only a delivery outlet is low level), and when certain certain row delivery outlet is low level, judge whether the level of input port has low level, this is called single pass.If a button is pressed for that row keyboard that is scanned, the level that then has the input port is dragged down, and judges it is which button is pressed according to the state of input port then actually.
Because the IO mouth of AVR single-chip microcomputer all has selectable internal pull-up resistor, so the pull-up resistor of keyboard circuit input port is omitted.4 line leads in the keyboard and 4 row go between and all receive the I/O pin of ATmega16L.
7.RS232 serial port circuit
Native system adopts the serial communication mode to carry out transfer of data, if adopt the Transistor-Transistor Logic level of singlechip directly to transmit information, its transmission range generally is no more than 1.5m, therefore the native system main frame communicates with the next slave employing RS-232C standard and is connected, signal adopts the RS-232C level transmissions, electrical level transferring chip adopts MAX232, and its circuit as shown in Figure 9.MAX232 pin T1IN or T2IN connect the serial ports output pin of single-chip microcomputer ATmega16L, and R10UT or R20UT connect the serial ports input pin of single-chip microcomputer; The R10UT of T1IN or T2IN and another MAX232 or R20UT interconnection; The positive and negative pin of positive and negative pin of the C1 of MAX232 and C2 respectively connects the electric capacity of one 0.1 μ F.
In sum, the master-plan schematic diagram of main frame as shown in figure 10.
(2) the next slave.The master-plan block diagram is as shown in figure 11:
1. power circuit
The next slave is as the expansion board of each game terminal, and power supply is drawn+5V from game terminal, uses for the next slave through too small capacitor filtering.When certain game terminal energising was used, the POWER indicator lamp of corresponding the next slave of expansion board should be lighted.
2. power down protection circuit
The power down protection circuit of the next slave is the same with the mentality of designing of main frame, as shown in Figure 4.Power supply can from the game machine terminal draw+5V, use for the next slave through too small capacitor filtering; Also can obtain external power source with host computer; When certain game terminal energising was used, the POWER indicator lamp of corresponding the next slave of expansion board should be lighted.
3.1602A LCD interface circuit
The liquid crystal that the LCD MODULE of the next slave of native system adopts is 1602A_V1.0, and this liquid crystal has two kinds of data wire 4 line transmission means and data wire 8 line transmission means, and the native system main frame adopts data wire 4 line transmission means, and its interface circuit as shown in figure 12.
Variable resistor VR1 among Figure 12 is used for regulating the contrast of liquid crystal, pin LEDA and LEDK connect respectively power supply and make the backlight Chang Liang of liquid crystal.LCD_D4 to LCD_D7 is the high 4 of liquid crystal data wire, and LCD_RS is data/command selection end (H/L), and LCD_EN is an enable signal, and R/W is read/write selecting side (H/L), and ground connection represents only to be used to write data/order liquid crystal.The 4th pin read control end from ATmega8 and allowed its data of external read in the slave LCD1602 Liquid Crystal Module; The 6th pin is an Enable Pin; The the 4th and the 6th pin all connects the I/O pin of ATmega8; The 11-14 pin is the data input pin, also connects the I/O pin of ATmega8.
4. game terminal score signal acquisition circuit
The topmost function of the next slave of native system is exactly the collection of game terminal score signal, and its circuit as shown in figure 13.Because the score signal voltage that extracts of game terminal is up to 12V, and AVR single-chip microcomputer IO port generally can only bear the following voltage of 5.5V, therefore, the score signal by the potentiometer dividing potential drop after filtering just be input to the external counting port of AVR single-chip microcomputer.Two data wires of signals collecting are received the data output end of game host by one 2 port; Divided data in reception in 2 ports, another receives divided data down.
5. keyboard circuit
The button inputting circuits of the next slave of native system only needs three buttons, the S1 button is used to enter change conversion scale pattern or does to reduce key and use when changing the conversion scale pattern, the S2 button is used to enter to be checked the conversion scale pattern or make to increase key usefulness when changing the conversion scale pattern, the S3 button is as acknowledgement key, and its circuit as shown in figure 14.
6.RS232 serial port circuit
The RS232 serial port circuit of the next slave is the same with the mentality of designing of main frame, as shown in Figure 9.
In sum, the master-plan schematic diagram of the next slave as shown in figure 15.
Claims (3)
1. the counter system of a multiple game machines network statistics marks comprises some the next slave and at least one main frames that the signal tabulate statistics shows that are used for the game terminal signal acquisition process; Wherein the next slave is gathered the score data of each game machine unit, and the data of gathering according to the processing that converts of the different score pattern of each game machine, and are sent to main frame with the data of finishing dealing with; Main frame receives the data that each the next slave sends over, and carries out aggregation process and demonstration;
It is core that this counter system adopts the AVR single-chip microcomputer, adopt multi-computer system to constitute distributed control, the single-chip microcomputer that main frame adopts is ATmega16L, and the single-chip microcomputer that the next slave adopts is ATmega8, is equipped with the RS-232C transmitter-receiver between main frame and the next slave and carries out long-distance transmissions;
Above-mentioned main frame comprises host power supply circuit, main frame power down protection circuit, main frame DS1302 clock chip circuit, main frame 12864-12 LCD interface circuit, main frame RS232 serial port circuit, mini-printer interface circuit and host keyboard circuit; Foregoing circuit is relatively independent, is connected to the acp chip ATmega16L of main frame;
Above-mentioned the next slave comprises the next slave power circuit, the next slave power down protection circuit, the next slave 1602A LCD interface circuit, game terminal score signal acquisition circuit, the next slave keyboard circuit and the next slave RS232 serial port circuit; Foregoing circuit is relatively independent, is connected to the acp chip ATmega8 of the next slave.
2. counter system according to claim 1 is characterized in that the circuit of above-mentioned main frame comprises:
1) host power supply circuit
Core controller adopts the ATmega16L single-chip microcomputer, and all circuit of native system main frame all adopt the design of 5V voltage, from the voltage of J1 input between the 6V to 12V; 3 port power interface JP5 connect external power source, and inner the 1st electrode line connects the diode of IN4148, and the 2nd and the 3rd line is made minus earth altogether; Diode connects one 7805 voltage-stabiliser tube, and outside 9V voltage voltage stabilizing is become inner 5V operating voltage, and the voltage-stabiliser tube two ends respectively connect two filter capacitors, all are 220 μ F and 0.1 μ F;
2) main frame power down protection circuit
Native system main frame capacitor C 9 is selected the electrochemical capacitor of 1000uF, can reliablely and stablely preserve data; Diode IN4007 is when allowing system's power down, and big electric capacity only is used to keep single-chip microcomputer storage data and the work of not keeping other peripheral hardwares; The centre cap of potentiometer is received the negative pole AIN1 of analog comparator, enables the ACBG of analog comparator by software, utilizes the inner energy gap a reference source of 1.23V to replace AIN0 to make the positive input terminal of analog comparator; Potentiometer transfers to AIN1 and triggers analog comparator in the time of can working as system's power down about 3V to interrupt, and data are saved among the EPPROM;
3) main frame DS1302 clock chip circuit
Adopt the mode of synchronous serial to communicate between DS1302 and the single-chip microcomputer, use three IO mouth lines; Power down leaves battery tray and the battery of 3.6V on the native system main frame, in case after the clock operation, can not stop yet; SCLK among the clock chip DS1302, RST, three clock chip control of I/O pin is received the pin of ATmega16L, and VCC1 connects the 3.3-3.6V battery, and VCC2 connects operating voltage; Clock chip connects the wrist-watch crystal oscillator of a 32.768KHz, for chip provides reference pulse;
4) main frame 12864-12 LCD interface circuit
The liquid crystal that the LCD MODULE of native system main frame adopts is HS12864-12_V4.0, and the native system main frame adopts the driven in series mode, and variable resistor VR2 is used for regulating the contrast of liquid crystal, and pin LEDA and LEDK ground connection and power supply respectively make the backlight Chang Liang of liquid crystal; Pin PSB ground connection represents to adopt the driven in series mode, the driven in series mode only takies three IO mouths of single-chip microcomputer, be respectively the chip selection signal (LCD_CS) of serial, the data port (LCD_SID) of serial, the synchronised clock (LCD_CLK) of serial, all directly link to each other with the IO mouth of single-chip microcomputer;
5) main frame RS232 serial port circuit
The native system main frame communicates with the next slave employing RS-232C standard and is connected, and signal adopts the RS-232C level transmissions, and electrical level transferring chip adopts MAX232; MAX232 pin T1IN or T2IN connect the serial ports output pin of single-chip microcomputer ATmega16L, and R10UT or R20UT connect the serial ports input pin of single-chip microcomputer; The R10UT of T1IN or T2IN and another MAX232 or R20UT interconnection; The positive and negative pin of positive and negative pin of the C1 of MAX232 and C2 respectively connects the electric capacity of one 0.1 μ F;
6) mini-printer interface circuit
The mini-printer that the native system main frame uses is: Galaxy Miniature Printer YH245B, adopt the parallel drive mode; The 11st pin senses printer modes in the 25 needle printer interfaces received an I/O pin of ATmega16L chip; The 1st pin is enable pin, also receives an I/O pin of ATmega16L chip; The 2-8 pin is a data output;
7). keyboard circuit
The native system main frame has adopted 4 * 4 dynamic keyboard scanning circuits; 4 line leads in the keyboard and 4 row go between and all receive the I/O pin of ATmega16L.
3. counter system according to claim 1 is characterized in that the circuit of above-mentioned the next slave comprises:
1) the next slave power circuit
The next slave is as the expansion board of each game machine terminal, power supply can from the game machine terminal draw+5V, use for the next slave through too small capacitor filtering; Also can obtain external power source with host computer; When certain game terminal energising was used, the POWER indicator lamp of corresponding the next slave of expansion board should be lighted;
2) the next slave power down protection circuit
The power down protection circuit of the next slave is identical with the power down protection circuit structure of above-mentioned main frame;
3) the next slave 1602A LCD interface circuit
The liquid crystal that the LCD MODULE of the next slave of native system adopts is 1602A_V1.0, adopts data wire 4 line transmission means; The 4th pin read control end from ATmega8 and allowed its data of external read in the slave LCD1602 Liquid Crystal Module; The 6th pin is an Enable Pin; The the 4th and the 6th pin all connects the I/O pin of ATmega8; The 11-14 pin is the data input pin, also connects the I/O pin of ATmega8;
Variable resistor VR1 is used for regulating the contrast of liquid crystal, pin LEDA and LEDK connect respectively power supply and make the backlight Chang Liang of liquid crystal, LCD_D4 to LCD_D7 is the high 4 of liquid crystal data wire, LCD_RS is data/command selection end (H/L), LCD_EN is an enable signal, R/W is read/write selecting side (H/L), and ground connection represents only to be used to write data/order liquid crystal;
4) game terminal score signal acquisition circuit
The score signal voltage that game terminal extracts is up to 12V, and AVR single-chip microcomputer IO port generally can only bear the following voltage of 5.5V, therefore, the score signal by the potentiometer dividing potential drop after filtering just be input to the external counting port of AVR single-chip microcomputer; Two data wires of signals collecting are received the data output end of game host by one 2 port; Divided data in reception in 2 ports, another receives divided data down;
5) the next slave keyboard circuit
The button inputting circuits of the next slave of native system has three buttons, the S1 button is used to enter change conversion scale pattern or does to reduce key and use when changing the conversion scale pattern, the S2 button is used to enter checks the conversion scale pattern or makes increase key usefulness that when changing the conversion scale pattern S3 button is as acknowledgement key;
6) the next slave RS232 serial port circuit
The RS232 serial port circuit structure of the RS232 serial port circuit of the next slave and above-mentioned main frame is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100325094A CN101234255A (en) | 2007-12-14 | 2007-12-14 | Counter system for multiple game machines network statistics marks |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100325094A CN101234255A (en) | 2007-12-14 | 2007-12-14 | Counter system for multiple game machines network statistics marks |
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| Publication Number | Publication Date |
|---|---|
| CN101234255A true CN101234255A (en) | 2008-08-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100325094A Pending CN101234255A (en) | 2007-12-14 | 2007-12-14 | Counter system for multiple game machines network statistics marks |
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| Country | Link |
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| CN (1) | CN101234255A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290039A (en) * | 2011-09-02 | 2011-12-21 | 天津津伯仪表技术有限公司 | Liquid crystal display circuit based on AVR singlechip |
| CN104011778A (en) * | 2011-12-21 | 2014-08-27 | 计算R有限公司 | System for exchanging a ticket with chips and vice versa at a gaming table in a casino |
-
2007
- 2007-12-14 CN CNA2007100325094A patent/CN101234255A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290039A (en) * | 2011-09-02 | 2011-12-21 | 天津津伯仪表技术有限公司 | Liquid crystal display circuit based on AVR singlechip |
| CN104011778A (en) * | 2011-12-21 | 2014-08-27 | 计算R有限公司 | System for exchanging a ticket with chips and vice versa at a gaming table in a casino |
| US9846876B2 (en) | 2011-12-21 | 2017-12-19 | Count R Gmbh | System for exchanging a ticket with chips and vice versa at a gaming table in a casino |
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Open date: 20080806 |