CN101232011B - Stack type chip packaging structure and manufacturing method thereof - Google Patents
Stack type chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN101232011B CN101232011B CN2008100810501A CN200810081050A CN101232011B CN 101232011 B CN101232011 B CN 101232011B CN 2008100810501 A CN2008100810501 A CN 2008100810501A CN 200810081050 A CN200810081050 A CN 200810081050A CN 101232011 B CN101232011 B CN 101232011B
- Authority
- CN
- China
- Prior art keywords
- chip
- package structure
- stack type
- metalwork
- support plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A stacked chip package structure comprises a carrier plate, a first chip, a second chip, a barrier layer and a metal part. The carrier plate is provided with an upper surface and a lower surface corresponding to each other; the first chip is arranged on the upper surface of the carrier plate and electrically connected with the carrier plate; the second chip is arranged on the first chip and electrically connected with the carrier plate; the barrier layer is arranged between the first chip and the second chip and made of a conductive material; and the metal part is connected with the outer periphery of the barrier layer and is electrically connected with a grounding terminal, thus grounding the barrier layer through the metal part. The invention further provides the fabrication method of the stacked chip package structure.
Description
Technical field
The invention relates to a kind of chip-packaging structure and method for packing thereof, and particularly relevant for a kind of stack type chip package structure and method for packing thereof that is applicable to radio frequency chip (RF chip).
Background technology
Because electronic industry is flourish, most electronic product is all constantly towards miniaturization, the target of lightweight and high speed strides forward, wherein more there are many electronic products must use radio frequency chip, for example with radio frequency chip and digital IC, radio frequency chip and digital signal processor (Digital SignalProcessor, DSP), or radio frequency chip and fundamental frequency chip (Base Band, BB) etc. combine, use the target that reaches miniaturization or high speed, only because radio frequency chip is a high frequency, therefore must carry out electromagnetic shielding (shielding) and handle, to avoid the interference of signal.
Fig. 1 is the generalized section of known a kind of stack type chip package structure.Please refer to Fig. 1, stack type chip package structure 100 comprises a support plate 110, one first chip 120, one second chip 130 and a sheet metal 140.Support plate 110 has a upper surface 112 and a lower surface 114.First chip 120 is disposed at upper surface 112, and electrically connects with support plate 110.Second chip 130 is a radio frequency chip, and it is disposed at first chip top, and electrically connects with support plate 110.Sheet metal 140 is disposed between first chip 120 and second chip 130, and is connected to an earth terminal 150, in order to isolated and prevent the interference of the signal of first chip 120 for radio frequency chip.Yet the sheet metal 140 that is arranged between first chip 120 and second chip 130 can make the thickness of whole stack type chip package structure 100 increase, and can't reach the miniaturization of required by electronic product, light-weighted requirement.
Summary of the invention
The invention provides a kind of stack type chip package structure and preparation method thereof, this encapsulating structure is a technology of utilizing chip stack with a chip (as a fundamental frequency chip) and a radio frequency chip storehouse together, and utilize one to block of the interference of the signal of this chip, and can not increase the thickness of whole stack type chip package structure for radio frequency chip by the formed isolation layer of conducting epoxy resin.
For addressing the above problem, the present invention proposes a kind of stack type chip package structure, comprises a support plate, one first chip, one second chip, a barrier layer and a metalwork.Support plate has a corresponding upper surface and a lower surface.First chip configuration and electrically connects with support plate on upper surface of said carrier plate.Second chip configuration is in first chip top, and electrically connects with support plate.Barrier layer is disposed between first chip and second chip, and wherein barrier layer is made up of an electric conducting material.Metalwork is connected in the outside of barrier layer, and wherein a metalwork and an earth terminal electrically connect, and make barrier layer pass through metalwork and ground connection.
In one embodiment of this invention, above-mentioned support plate comprises most the soldered balls that are disposed on the lower surface.
In one embodiment of this invention, above-mentioned first chip comprises a digital integrated circuit, a digital signal processor or a fundamental frequency chip.
In one embodiment of this invention, above-mentioned first chip is by chip bonding mode or routing juncture and support plate electric connection.
In one embodiment of this invention, above-mentioned second chip comprises a radio frequency chip.
In one embodiment of this invention, above-mentioned second chip electrically connects by routing juncture and support plate.
In one embodiment of this invention, above-mentioned barrier layer is made up of conducting epoxy resin.
In one embodiment of this invention, above-mentioned earth terminal is positioned on the support plate.
In one embodiment of this invention, above-mentioned metalwork electrically connects by a routing lead and earth terminal.
In one embodiment of this invention, above-mentioned stack type chip package structure more comprises a packing colloid, and wherein packing colloid is to be disposed on the support plate, and covers first chip, second chip, barrier layer and metalwork.
The present invention proposes a kind of manufacture method of stack type chip package structure in addition, and it comprises the following steps: at first, and a circuit base plate is provided, and it has a corresponding upper surface and a lower surface.Next, one first chip is set on the upper surface of circuit base plate.Then, electrically connect first chip and circuit base plate.Then, a metalwork is set on first chip, wherein metalwork has an opening.Come, dispose an electric conducting material in the opening of metalwork, and be covered on first chip, wherein electric conducting material system is electrically conducted with metalwork.Afterwards, dispose one second chip in metalwork and electric conducting material top; At last, electrically connect second chip and circuit base plate.
In one embodiment of this invention, before the step of above-mentioned configuration first chip, more comprising provides the upper surface of an adhesion material in circuit base plate.
In one embodiment of this invention, after the step of above-mentioned configuration first chip, more comprise the heating adhesion material, with set first chip on circuit base plate.
In one embodiment of this invention, after the step of above-mentioned configuration second chip, more comprise heating adhesion material and electric conducting material, with while set first chip and second chip.
Stack type chip package structure of the present invention is a technology of utilizing chip stack, and storehouse together with radio frequency chip and other chip (as the fundamental frequency chip), and the barrier layer that utilizes one deck to form by conducting epoxy resin, with the interference of the signal that intercepts the chip be positioned at the radio frequency chip below effectively, and can not increase the thickness of whole stack type chip package structure for radio frequency chip.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of known a kind of stack type chip package structure.
Fig. 2 is the profile of the stack type chip package structure of one embodiment of the invention.
Fig. 3 is the profile of the stack type chip package structure of another embodiment of the present invention.
Fig. 4 A to Fig. 4 H is the manufacture method flow chart of the stack type chip package structure of Fig. 2.
Embodiment
Fig. 2 illustrates and is the generalized section according to the stack type chip package structure of one embodiment of the invention.Please refer to Fig. 2, stack type chip package structure 200 is applicable to the stack type chip package structure with radio frequency chip, to reduce the interference that radio frequency chip is subjected to.
Stack type chip package structure 200 mainly comprises a support plate 210, one first chip 220, one second chip 230, a barrier layer 240 and a metalwork 250.Support plate 210 has a corresponding upper surface 212 and a lower surface 214, and above-mentioned support plate 210 can be printed circuit board (PCB) (printedcircuit board, PCB), circuit base plate or chip support plate (chip carrier) etc.In addition, the lower surface 214 of support plate 210 optionally disposes a plurality of soldered balls 216, and stack type chip package structure 200 can be electrically connected with other assembly by soldered ball 216.
Metalwork 250 is connected in the outside of barrier layer 240, and is connected with earth terminal 260 on being positioned at support plate 210 by a routing lead 254, makes barrier layer 240 by metalwork 250 and ground connection.In this embodiment, metalwork 250 is one to be surrounded on the cyclic metal piece of the outer peripheral edges of barrier layer 240.Yet metalwork 250 also can be the metalwork of a strip, is connected in the part outer peripheral edges of barrier layer 240, and ground connection gets final product by the metalwork of strip to make barrier layer 240.The present invention does not impose any restrictions for the shape of metalwork 250.
In addition, stack type chip package structure 200 more can comprise a packing colloid 270, and this packing colloid 270 covers first chip 220, second chip 230, barrier layer 240 and metalwork 250, avoids being undermined with each assembly on the protection support plate 210 and makes moist.
Because radio frequency chip is responsive to noise, so, be to utilize the barrier layer 240 that is disposed between the radio frequency chip and first chip 220 in this embodiment, be positioned at of the interference of the signal of first chip 220 to intercept effectively for radio frequency chip.Because barrier layer 240 itself promptly is in order to second chip 230 being fixed in the adhesion material on first chip 220, therefore, the existence of barrier layer 240 can't increase the thickness of whole stack type chip package structure 200.
Fig. 3 is the generalized section of the stack type chip package structure of another embodiment of the present invention.Please refer to Fig. 3, this stack type chip package structure 200a is identical with the stack type chip package structure 200 shown in Fig. 2 haply, but, in the stack type chip package structure 200a shown in Fig. 3, the first chip 220a electrically connects by routing lead 222a and support plate 210a.
Below will the arrange in pairs or groups manufacture method of the above-mentioned stack type chip package structure of illustration.Fig. 4 A to Fig. 4 H is the manufacture method flow chart of the stack type chip package structure of Fig. 1.Please refer to Fig. 4 A to Fig. 4 H, the manufacture method of stack type chip package structure 200 may further comprise the steps: at first, shown in Fig. 4 A, provide a circuit base plate (being support plate) 210, it has a corresponding upper surface 212 and a lower surface 214.
Come again, shown in Fig. 4 B, first chip 220 is arranged on the upper surface 212 of circuit base plate 210.Next, first chip 220 and circuit base plate 210 are electrically connected.The mode that first chip 220 and circuit base plate 210 are electrically connected for example is that heating is with projection 222 meltings, so that first chip 220 electrically connects by projection 222 and circuit base plate 210.
After first chip 220 and circuit base plate 210 electrically connect, please refer to shown in Fig. 4 C, can between first chip 220 and circuit base plate 210, insert an adhesion material 280 (as primer), to improve the reliability that is connected between first chip 220 and the circuit base plate 210.
Afterwards, shown in Fig. 4 D, a metalwork 250 is set on first chip 220, wherein metalwork 250 has an opening 252.Metalwork 250 can electrically connect with earth terminal 260 by routing lead 254.
Come again, shown in Fig. 4 E, dispose an electric conducting material (being barrier layer) 240 in opening 252, and be covered on first chip 220, and electric conducting material 240 and metalwork 250 are electrically conducted.Electric conducting material 240 can be in order to second chip 230 is fixed in the colloid on first chip 220, and its material for example is conducting epoxy resin, photo-curing epoxy resin or heat-curable epoxy resin.
Then, shown in Fig. 4 F, second chip 230 is disposed at the top of metalwork 250 and electric conducting material 240.Afterwards, can heat or ultraviolet light polymerization, so that first chip 220 and second chip 230 solidify electric conducting material 240.In addition, above-mentioned adhesion material 280 step of curing that make also can be carried out in the lump in the curing of this and electric conducting material 240.
Next, shown in Fig. 4 G, electrically connect second chip 230 and circuit base plate 210.At this embodiment, second chip 230 electrically connects by the signal contact on routing lead 232 and the circuit base plate 210 218.So far, promptly finish the basic making flow process of stack type chip package structure.
In addition; please refer to shown in Fig. 4 H; after electrically connecting second chip 230 and circuit base plate 210; optionally on support plate 210, form a packing colloid 270; this packing colloid 270 is to cover first chip 220, second chip 230, barrier layer 240 and metalwork 250, avoids being undermined with each assembly on the protection support plate 210 and makes moist.
Moreover, please refer to shown in Figure 2ly, optionally in most soldered balls 216 of lower surface 214 configuration of circuit base plate 210, stack type chip package structure 200 is electrically connected by soldered ball 216 and with other assembly.
In this embodiment, first chip 220 electrically connects by the mode and the circuit base plate 210 of chip bonding, yet first chip 220 can also alternate manner and circuit base plate 210 electric connection, for example routing junctures.When electrically connecting first chip 220 with circuit base plate 210 with the routing juncture, can add an adhesion material earlier on circuit base plate 210, adhesion material can be heat-curable epoxy resin or photo-curing epoxy resin.Then, be arranged on first chip 220 on the adhesion material and adhesion material is solidified.Then, the mode of utilizing routing to engage makes first chip 220 be connected with signal contact 218 on the circuit base plate 210.
In sum, stack type chip package structure of the present invention is a technology of utilizing chip stack, and storehouse together with radio frequency chip and other chip (as the fundamental frequency chip), and the barrier layer that one deck is formed by conducting epoxy resin is set in the two, this barrier layer is disposed at its peripheral metalwork and ground connection by one, with the interference for radio frequency chip of the signal that intercepts other chip be positioned at the radio frequency chip below effectively.Because barrier layer itself promptly is the adhesion material in order to fixed chip, therefore, the existence of barrier layer can't increase the thickness of whole stack type chip package structure.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (14)
1. stack type chip package structure comprises:
Support plate has corresponding upper surface and lower surface;
First chip is disposed on this upper surface of this support plate, and electrically connects with this support plate;
Second chip is disposed at this first chip top, and electrically connects with this support plate;
Barrier layer is disposed between this first chip and this second chip, and wherein this barrier layer is made up of electric conducting material; And
Metalwork is connected in the outside of this barrier layer, and wherein this metalwork and an earth terminal electrically connect, and makes this barrier layer by this metalwork and ground connection.
2. stack type chip package structure as claimed in claim 1, wherein this substrate comprises most the soldered balls that are disposed on this lower surface.
3. stack type chip package structure as claimed in claim 1, wherein this first chip comprises digital integrated circuit, digital signal processor or fundamental frequency chip.
4. stack type chip package structure as claimed in claim 1, wherein this first chip is by chip bonding mode or routing juncture and the electric connection of this support plate.
5. stack type chip package structure as claimed in claim 1, wherein this second chip comprises radio frequency chip.
6. stack type chip package structure as claimed in claim 1, wherein this second chip electrically connects by routing juncture and this support plate.
7. stack type chip package structure as claimed in claim 1, wherein this barrier layer is made up of conducting epoxy resin.
8. stack type chip package structure as claimed in claim 1, wherein this earth terminal is positioned on this support plate.
9. stack type chip package structure as claimed in claim 8, wherein this metalwork electrically connects by a routing lead and this earth terminal.
10. stack type chip package structure as claimed in claim 1 more comprises packing colloid, and wherein this packing colloid is to be disposed on this support plate, and covers this first chip, this second chip, this barrier layer and this metalwork.
11. the manufacture method of a stack type chip package structure comprises:
One circuit base plate is provided, has corresponding upper surface and lower surface;
First chip is set on this upper surface of this circuit base plate;
Electrically connect this first chip and this circuit base plate;
Metalwork is set on this first chip, wherein this metalwork has opening;
Dispose electric conducting material in this opening of metalwork, and be covered on this first chip, wherein this electric conducting material system is electrically conducted with this metalwork;
Dispose second chip in this metalwork and this electric conducting material top; And
Electrically connect this second chip and this circuit base plate.
12. the manufacture method of stack type chip package structure as claimed in claim 11, wherein before the step of this first chip of configuration, more comprising provides the upper surface of an adhesion material in this circuit base plate.
13. the manufacture method of stack type chip package structure as claimed in claim 12, wherein the configuration this first chip step after, more comprise the heating this adhesion material, with this first chip of set on this circuit base plate.
14. the manufacture method of stack type chip package structure as claimed in claim 12 wherein after the step of this second chip of configuration, more comprises this adhesion material of heating and this electric conducting material, with this first chip of while set and this second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100810501A CN101232011B (en) | 2008-02-21 | 2008-02-21 | Stack type chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100810501A CN101232011B (en) | 2008-02-21 | 2008-02-21 | Stack type chip packaging structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101232011A CN101232011A (en) | 2008-07-30 |
| CN101232011B true CN101232011B (en) | 2010-09-08 |
Family
ID=39898337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100810501A Active CN101232011B (en) | 2008-02-21 | 2008-02-21 | Stack type chip packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101232011B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8592973B2 (en) * | 2009-10-16 | 2013-11-26 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof |
| US9418974B2 (en) * | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
| CN105206591A (en) * | 2015-08-31 | 2015-12-30 | 中国科学院自动化研究所 | Circuit board with digital signal isolation circuit chip and packaging method |
-
2008
- 2008-02-21 CN CN2008100810501A patent/CN101232011B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101232011A (en) | 2008-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101874057B1 (en) | Integrated circuit package system with package stacking and method of manufacture thereof | |
| KR102245003B1 (en) | Semiconductor packages capable of overcoming overhangs and methods for fabricating the same | |
| KR102210332B1 (en) | Semiconductor package | |
| US8569869B2 (en) | Integrated circuit packaging system with encapsulation and method of manufacture thereof | |
| US7566962B2 (en) | Semiconductor package structure and method for manufacturing the same | |
| US20080083960A1 (en) | Package structure and packaging method of mems microphone | |
| CN101814484A (en) | Chip package and manufacturing method thereof | |
| US20090108431A1 (en) | Inverted package-on-package (POP) assemblies and packaging methods for integrated circuits | |
| CN104600055A (en) | Fingerprint recognition sensor | |
| US7692313B2 (en) | Substrate and semiconductor package for lessening warpage | |
| US20080217759A1 (en) | Chip package substrate and structure thereof | |
| KR101407614B1 (en) | Printed circuit board, semiconductor package, card and system | |
| US7701046B2 (en) | Stacked type chip package structure | |
| CN101232011B (en) | Stack type chip packaging structure and manufacturing method thereof | |
| US20140374901A1 (en) | Semiconductor package and method of fabricating the same | |
| US20080009104A1 (en) | Semiconductor package having electromagnetic interference shielding and fabricating method thereof | |
| US20080122059A1 (en) | Stacked chip package structure and fabricating method thereof | |
| US20090184404A1 (en) | Electromagnetic shilding structure and manufacture method for multi-chip package module | |
| US8703535B2 (en) | Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof | |
| KR20160091084A (en) | System-in-Package module | |
| US9502377B2 (en) | Semiconductor package and fabrication method thereof | |
| US7589405B2 (en) | Memory cards and method of fabricating the memory cards | |
| US7374967B2 (en) | Multi-stack chip size packaging method | |
| US20160081234A1 (en) | Package structure | |
| US8476135B2 (en) | Integrated circuit packaging system with vertical interconnects and method of manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |