CN101226567A - Design method and system of a reliable on-chip bus and its working method - Google Patents

Abstract

The invention discloses a design method and system of a reliable on-chip bus and its working method. A design method for a reliable on-chip bus is to use the parity check matrix of the group code to select a subset with error correction capability from the crosstalk avoidance codeword set to form a crosstalk avoidance codeword set with error correction capability, which is applied on-chip The circuit design of the bus, which includes the following steps: generating a code word set according to the rules of crosstalk avoidance coding; deriving the attributes of the parity check matrix of the group code according to the requirements; optimizing all parity check matrices that meet the attributes to obtain the best parity check matrix to generate a set of crosstalk-avoiding encoded codewords with error-correcting capability. Under the premise of not introducing secondary crosstalk, it can ensure that the bus avoids the influence of crosstalk delay with a small wiring overhead and power consumption overhead, and can correct signal inversion caused by noise on the bus.

Description

Design method and system of a reliable on-chip bus and its working method

technical field

The present invention relates to the technical field of semiconductor technology, mainly the method and design of VLSI fault tolerance (Fault Tolerance), in particular to a design method and system of a reliable on-chip bus and its working method.

Background technique

With the continuous reduction of the gate delay, the delay of the long bus in the system on chip (SOC) has an increasingly significant effect on whether the system can achieve high overall performance. However, in the ultra-deep submicron process and GHZ operating frequency, parasitic elements such as coupling capacitance and parasitic inductance play a significant role in the circuit. When the signal jumps, they will charge and discharge (in the ultra-deep sub-micron process, the coupling capacitor plays a major role), so that the correct response of the signal cannot be obtained at the output end. These effects mainly include crosstalk delay (Crosstalk-InducedDelay) and crosstalk peak (Crosstalk-Induced Glitch). Among them, the crosstalk delay causes some signals on the bus to fail to reach the output terminal within the specified time, which seriously affects the synchronization of the signals. According to the international semiconductor technology roadmap, when the system clock reaches 10GHZ, the delay of this on-chip bus can even be comparable to the clock frequency. In order to eliminate the impact of bus crosstalk and ensure the reliability of long buses, the industry needs to continuously optimize system wiring, or adopt a conservative bus structure, that is, add shielded wires between adjacent wires. The former method requires multiple evaluations and improvements, and the complexity of auxiliary tools is extremely high; the latter method not only increases the area overhead, but also increases the delay and power consumption of the bus.

Therefore, researchers design corresponding crosstalk avoidance codes (Crosstalk Avoidance Code, CAC for short) to avoid bad transition combinations of bus signals, thereby avoiding crosstalk delays. Figure 1 shows the relative delays caused by different hopping combinations. The worst hopping combination (↓, ↑, ↓) has 4λ more delay than the best hopping combination (↑, ↑, ↑), where λ is The ratio of wire coupling capacitance to ground capacitance. Using relative delay as the upper limit of CAC delay, CAC encoding can be divided into Delay=1+λ (accelerated encoding), Delay=1+2λ (common encoding) and Delay=1+3λ (avoiding maximum delay encoding). The commonly used coding rules are divided into two categories, namely Forbidden Transition Code (FTC for short) and Forbidden Pattern Code (FPC for short). Among them, when the FTC requires its codeword and the reference codeword (composed of alternate 01) to form a vector pair, the adjacent signal lines are prohibited from jumping at the same time; ". These methods can greatly reduce the delay overhead of the bus, and at the same time, the area overhead is small, which is an ideal on-chip bus fault-tolerant method.

However, the current coding method CAC can only avoid crosstalk delay faults, but cannot correct signal inversions caused by circuit noise. If noise on the bus is to be tolerated, including crosstalk spikes caused by crosstalk, a new Hamming check code needs to be added to CAC to form a combined code with error correction capabilities, as shown in Figure 2. However, the encoding bus generated by the CAC unit 001 and the verification bus generated by the ECC unit 002 have multi-stage gate delays, so the width of the system clock pulse needs to be increased. This will restrict the improvement of the main frequency of the system. More importantly, the signal transition of the verification bus Kc also lags behind the encoding bus L. This late signal transition can cause secondary crosstalk on the encoded bus. It increases the transition delay of the signal, resulting in a decrease in the performance of the bus system.

At the same time, the newly generated Hamming check code does not have the ability to avoid crosstalk delay. Moreover, the information on the check bus is used for error correction and cannot be changed during signal transmission, so the Hamming check code cannot be CAC encoded. As shown in Figure 2, the verification bus needs to add a protection line through unit 003 to protect the verification line from the influence of bus crosstalk. With this approach, the wiring overhead of the system is increased, resulting in unnecessary power consumption on the on-chip bus.

Contents of the invention

The purpose of the present invention is to provide a design method and system of a reliable on-chip bus and its working method, which can ensure that the bus avoids crosstalk delay with less wiring overhead and power consumption overhead without introducing secondary crosstalk and can correct for signal upsets on the bus due to noise.

The design method of a kind of reliable on-chip bus provided for realizing the purpose of the present invention is to utilize the parity check matrix of the group code to select the subset with error-correcting ability from the crosstalk-avoiding coding codeword collection, constitute the crosstalk with error-correcting ability Avoid encoding codeword set, be applied to the circuit design of on-chip bus, it comprises the following steps:

A. Generate a codeword set according to the rules of crosstalk avoidance coding;

B. According to the requirements, deduce the attribute of the parity check matrix of the group code;

C. Optimizing all parity check matrices satisfying the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capability.

Described step A also further comprises:

A1. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate inclusions, the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk are obtained;

A2. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay;

A3. Generate a codeword set according to the selected crosstalk avoidance code.

Described step B also further comprises:

B1. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code;

B2. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying the attribute.

In the step B1, if and only when the code distance is greater than or equal to 2K+1, the encoding can correct the K-bit fault.

In described step B2, if and only if in the generation matrix of group codes, the column vector group equal to ^0T is added, their minimum column vector number is equal to a, then the code distance of group codes is equal to a; the dimension of matrix column vector m must be no less than log ₂ (n+1), where n is the number of bits of the codeword.

Described step C also further comprises:

C1. according to the method described in step A1, generate the crosstalk avoiding codeword set of N bits;

C2. Judging whether all check matrices satisfying the attributes have been judged, if all judgments have been made, then perform step C3; otherwise, perform step C4;

C3. Add 1 to N;

C4. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set;

C5. If the number of codewords that meet the requirements meets the number of encoded M-bit information, then step C6 is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2;

C6. Outputting a crosstalk-avoiding coding codeword set that meets requirements and has error correction capability.

In the step C4, in the process of selecting a codeword, if the codeword in the N-bit crosstalk avoidance codeword set satisfies the verification equation formed by the matrix to be determined, the codeword is added to the codeword set that meets the requirements; Otherwise, the codeword is deleted.

Also provide a kind of reliable on-chip bus system for realizing the purpose of the present invention, comprise:

Coding unit, which is set on the input port of the bus system, and is used to convert the information to be transmitted into the code on the bus;

The bus system unit is designed according to the crosstalk-avoiding coding codeword set with error correction capability, and is used for transmission coding;

A decoding unit, which is arranged on the input port of the bus system, is used to convert the code transmitted on the bus into information;

The check unit is used to find and correct errors encoded in transmission.

The encoding unit is a circuit that uses the SIS logic optimization tool to generate optimized encoding logic from the codebook that contains the information set and the mapping relationship of the optimal codeword set, and realizes the circuit through a combinational circuit or a codeable logic array.

In the bus system unit, the crosstalk-avoiding code word set with error correction capability is a code word set determined according to a reliable on-chip bus design method.

The design method of the reliable on-chip bus is to use the parity check matrix of the group code to select a subset with error correction capability from the crosstalk-avoiding coding codeword set to form a crosstalk-avoiding coding codeword set with error-correcting capability, which is applied to the on-chip The circuit design of the bus, which includes the following steps:

A. Generate a codeword set according to the rules of crosstalk avoidance coding;

B. According to the requirements, deduce the attribute of the parity check matrix of the group code;

C. Optimizing all parity check matrices satisfying the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capability.

Described step A also further comprises:

A1. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate inclusions, the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk are obtained;

A2. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay;

A3. Generate a codeword set according to the selected crosstalk avoidance code.

Described step B also further comprises:

B1. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code;

B2. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying the attribute.

In the step B1, if and only when the code distance is greater than or equal to 2K+1, the encoding can correct the K-bit fault.

In described step B2, if and only if in the generation matrix of group codes, the column vector group equal to ^0T is added, their minimum column vector number is equal to a, then the code distance of group codes is equal to a; the dimension of matrix column vector m must be no less than log ₂ (n+1), where n is the number of bits of the codeword.

Described step C also further comprises:

C1. according to the method described in step A1, generate the crosstalk avoiding codeword set of N bits;

C2. Judging whether all check matrices satisfying the attributes have been judged, if all judgments have been made, then perform step C3; otherwise, perform step C4;

C3. Add 1 to N;

C4. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set;

C5. If the number of codewords that meet the requirements meets the number of encoded M-bit information, then step C6 is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2;

C6. Outputting a crosstalk-avoiding coding codeword set that meets requirements and has error correction capabilities.

In the step C4, in the process of selecting a codeword, if the codeword in the N-bit crosstalk avoidance codeword set satisfies the verification equation formed by the matrix to be determined, the codeword is added to the codeword set that meets the requirements; Otherwise, the codeword is deleted.

The decoding unit is a circuit that uses the SIS logic optimization tool to generate optimized decoding logic from the decoding book containing the mapping relationship between the optimal codeword set and the information set, and implements it through a combinational circuit or an editable logic array.

The verification unit further includes:

Check matrix unit: recalculate the output code word of the bus system unit and the corresponding check matrix, and input the obtained result to the error decoding unit;

Error decoding unit: judge whether there is an error according to the input operation result, and input the error correction information to the correction unit;

Correction unit: correct the error of the corresponding bit of the code word according to the error correction information.

The corresponding parity check matrix refers to a matrix that selects a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set, and each parity check matrix is associated with a set of codeword sets that meet the parity check matrix correspond.

Also provide a kind of working method of reliable on-chip bus system for realizing the purpose of the present invention, comprise the following steps:

A. According to the crosstalk-avoiding codeword set with error correction capability, the information to be transmitted is mapped to the codewords in the set one by one, and transmitted on the system bus;

B. Check and correct the outgoing codeword;

C. Convert the codeword into corresponding information and output it.

In step A, the crosstalk-avoiding codeword set with error correction capability is a codeword set determined according to a reliable on-chip bus design method.

In the step A, the information to be transmitted is converted into codes on the bus by using the codebook containing the mapping relationship between the information set and the codeword set.

The design method of described reliable on-chip bus comprises the following steps:

A'. Generate a codeword set according to the rules of crosstalk avoidance coding;

B'. According to the requirements, deduce the attribute of the check matrix of the group code;

C'. Optimizing all parity check matrices that meet the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capabilities.

Described step A' also further comprises:

A1'. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate doping, get the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk;

A2'. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay;

A3'. According to the selected crosstalk avoidance coding, a codeword set is generated.

Described step B' also further comprises:

B1'. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code;

B2'. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying this attribute.

In the step B1', if and only when the code distance is greater than or equal to 2K+1, the encoding can correct the K-bit fault.

In the step B2', if and only if the group of column vectors equal to 0 ^T is added in the generation matrix of the group code, their minimum column vector number is equal to a, then the code distance of the group code is equal to a; the dimension of the matrix column vector The number m must be no smaller than _log2 (n+1), where n is the number of bits of the codeword.

Described step C ' also further comprises:

C1'. according to the method described in step A1', generate N-bit crosstalk avoiding codeword sets;

C2'. Judging whether all check matrices satisfying the attribute have been judged, if all judgments have been made, then execute step C3'; otherwise execute step C4';

C3'. Add 1 to N;

C4'. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select the codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set;

C5'. If the number of codewords that meet the requirements meets the number of encoded M-bit information, step C6' is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2';

C6'. Output a crosstalk-avoiding encoding codeword set that meets the requirements and has error correction capabilities.

In the step C4', in the process of selecting a codeword, if the codeword in the N-bit crosstalk avoidance codeword set satisfies the verification equation formed by the matrix to be determined, add the codeword to the codeword set that meets the requirements ; Otherwise, the codeword is deleted.

Said step B further comprises the steps of:

B1. Calculate the bus output codeword and the corresponding parity check matrix again, and judge whether the output operation result is wrong;

B2. According to the error correction information, correct the error of the corresponding bit of the code word.

The corresponding parity check matrix refers to a matrix that selects a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set, and each parity check matrix is associated with a set of codeword sets that meet the parity check matrix correspond.

In the step B1, if the output result is equal to 0 ^T , there is no error in the codeword transmission, and all outputs remain 0; otherwise, find out the column vector equal to the output result from the parity check matrix, and compare the position of the column vector The same output is set to 1 as error correction information.

In the step B2, when the error correction information is input as 0, it means that the corresponding bit in the code word has no error and remains unchanged; when the error correction information is input as 1, it means that the corresponding bit in the code word has an error, and the signal is reversed.

In the step C, the code transmitted on the bus is converted into information by using the decoding book including the mapping relationship between the codeword set and the information set, and then output.

The beneficial effects of the present invention are:

1. It can ensure the efficient and reliable operation of the global bus in integrated circuits below the ultra-deep submicron process;

2. It can correct the signal reversal caused by noise on the bus, and has high commercial and academic value.

3. Avoid adding new Hamming codes and shielded wires to provide error correction capabilities, with less wiring overhead and lower power consumption;

4. The signals on the bus will change at the same time, which can avoid the secondary crosstalk effect caused by the direct introduction of Hamming code, and ensure the performance of the bus;

Description of drawings

Figure 1 is a diagram of the relationship between jump combinations and relative delays;

Fig. 2 is a schematic diagram of CAC coding directly combined with Hamming code;

Fig. 3 is the flowchart of the design method of reliable on-chip bus of the present invention;

Fig. 4 is to determine to have the crosstalk of error correcting ability and avoid the code word set algorithm flowchart;

Fig. 5 is a diagram of the number of codewords selected by different parity check matrices;

Fig. 6 is the example of codeword selection rule;

Fig. 7 is a schematic structural diagram of a reliable on-chip bus system;

Fig. 8 is a schematic structural diagram of a verification unit;

Fig. 9 is a flow chart of the method of operation of the reliable on-chip bus system.

Figure 10 is a wiring overhead diagram of different fault-tolerant buses based on the FTC principle;

Figure 11 is a wiring overhead diagram of different fault-tolerant buses based on the FPC principle;

Fig. 12 is the average power consumption diagram of directly combining coding mode and codeword selection coding mode wire;

Fig. 13 is a time delay analysis circuit sectional view;

Fig. 14 is a waveform diagram of bus level signal falling.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the design method and system of a reliable on-chip bus and its working method of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The design method and system of a reliable on-chip bus of the present invention and its working method are to determine the crosstalk-avoiding codeword set with error correction capability through the design method of a reliable on-chip bus based on codeword selection, and according to the error correction capability A reliable on-chip bus system is designed to avoid crosstalk encoding codeword sets, and the designed reliable on-chip bus system is used to transmit information.

The design method of a kind of reliable on-chip bus of the present invention is introduced in detail below in conjunction with above-mentioned object, and it is to utilize the parity check matrix of group code to select the sub-collection that possesses error-correcting capability from the crosstalk-avoiding encoding code word collection, constitutes the crosstalk possessing error-correcting capability Avoid encoding code word set, apply to the circuit design of on-chip bus.

As shown in Figure 3 and Figure 4, the following steps are included:

Step S100, generating a codeword set according to the rules of Crosstalk Avoidance Code (CAC for short);

Step S110, according to the semiconductor device process library instructions for the bus wiring information, including physical size, wire material and substrate doping, to obtain the ratio (λ) of the coupling capacitance to the ground capacitance and the transmission delay without crosstalk (t ₀ );

Step S120, combining the delay avoidance performance of different CAC codes, predicting the upper limit of CAC delay;

Using relative delay as the upper limit of CAC delay, CAC coding can be divided into accelerated coding (Delay=1+λ), common coding (Delay=1+2λ) and maximum delay avoidance coding (Delay=1+3λ). Among them, the commonly used codes are divided into two categories, namely Forbidden Jump Coding (FTC) and Forbidden Vector Coding (FPC). Calculate the upper limit of the actual delay of different CACs, where the actual delay is the product of the transmission delay (t ₀ ) and the relative delay (Delay).

Refer to the requirements of the design specification for the signal transition delay, and select the appropriate CAC code.

Step S130, generate a codeword set according to the selected CAC code;

Step S200, according to requirements, deduce the attributes of the parity check matrix of the group code;

Step S210, referring to the requirements of the design specification for error correction capability, and determining the code distance of the corresponding group code;

Suppose the algebraic system <Sn, o> is a group, Sn is the complete set of n-bit codewords, and the addition operation o is a bitwise XOR operator.

Definition 1 Let Cn be a non-empty subset of Sn, if Cn is also a group and a subgroup of Sn, then Cn is called a group code. Ham(X, Y) represents the Hamming distance of two codewords in Cn, where X, Y represent two arbitrary codewords. The smallest non-zero Hamming distance is called the code distance of Cn. The number of signal 1s in a codeword is called the weight of the codeword. Because the sum of any two codewords X and Y in the group code Cn still belongs to the group code Cn, their Hamming distance Ham(X, Y) is equal to the weight W(Z) of a certain codeword Z of the group code, as By analogy, the code distance of the group codes also has a corresponding relationship with the weight of the code word.

Theorem 1 If and only when the code distance is greater than or equal to 2K+1, the code can correct K-bit faults.

Theorem 2 The code distance of the group code Cn is equal to the minimum weight of non-zero codewords in the group code, as shown in Equation 2.

等式2

Equation 2

Step S220, according to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying the attribute;

Corollary 1 If and only if the sum of the column vector groups equal to 0 ^T in the generator matrix of the group code is equal to a, then the code distance of the group code is equal to a.

Meanwhile, the dimension m of the matrix column vector must not be less than log ₂ (n+1), where n is the number of bits of the codeword.

There are many matrices that meet the above requirements. Preferably, the present invention obtains all matrices that meet the requirements by selecting column vectors and rearranging the column vectors for optimization in step S300.

As a possible implementation, assuming that the reference design specification requires the circuit to have the ability to correct a single error, according to the derivation of Theorem 1 and Corollary 1, the code distance of the group code should be equal to 3, and there are at least 3 column vectors in its parity check matrix Addition equals 0 ^T . Therefore, the corresponding parity check matrix must satisfy the following two properties:

1 The check matrix does not have the same column vector, nor does it have vector 0 ^T .

2 There is a vector group consisting of 3 column vectors in the parity check matrix, and their sum is equal to 0 ^T .

Meanwhile, the dimension m of the matrix column vector must not be less than log ₂ (n+1), where n is the number of bits of the codeword.

Step S300, optimize all parity check matrices that meet the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capabilities, see Figure 4, Figure 5 and Figure 6;

As shown in FIG. 5 , the numbers of codewords obtained by different check matrix selections are different. When the parity check matrix is appropriate, the number of selected codewords is larger. Optimizing the parity check matrix ensures that when encoding M-bit information, a set of codewords with the total number of codewords meeting the requirements and the minimum number of codeword bits is searched. This ensures a low wiring overhead for the bus system and at the same time a low power consumption overhead.

Step S310, according to the method described in step S100, generate an N-bit CAC code word set;

Step S320, judging whether all parity check matrices satisfying the attributes have been judged, if all judgments have been made, then execute step S330; otherwise execute step S340;

Step S330, adding 1 to N;

Step S340, from all matrices that meet the requirements, select a matrix to be determined as a parity check matrix, and select a codeword set that meets the requirements from the N-bit CAC codeword set;

In the process of selecting a codeword, if the codeword in the N-bit CAC codeword set satisfies the verification equation formed by the matrix to be determined, the codeword is added to the codeword set that meets the requirements; otherwise, the codeword is deleted .

Definition 2 If the group code Cn={X|H X ^T ＝0 ^T }, wherein the multiplication operation is a bitwise AND operator, any code word of the X group code, T represents transposition, and H is the generation matrix of the group code (consistency check matrix), then the equation {X|H·X ^T =0 ^T } is the generation equation (consistency check equation) of the group code Cn, and all codewords are generated through the equation.

As an implementable manner, Fig. 6 is an example of codeword selection for 5-bit encoding. Sub-graph (a) removes the codewords containing "101" or "010" from the complete set of 5-bit codewords according to the FPC rule, and the remaining 16 codewords are the FPC codeword set. Subgraph (b) is the check matrix H of the group code whose code distance is equal to 3, and the FPC code word needs to be judged by the check equation {X|H·X ^T =0 ^T } constituted by it. If the code word conforms to the check equation, the code word belongs to a group code with error correction capability. For example, the code word "00111" of FPC is substituted into the check equation operation. First, the multiplication operation, the column vector (h3, h4, h5) of the matrix H is selected; then the addition operation, the sum of the column vectors (h3, h4, h5) is equal to 0 ^T , so the code word "00111" conforms to the verification equation, it Belongs to the group code. When the FPC code word "10011" is substituted into the check equation operation, the column vector (h1, h4, h5) is selected during the multiplication operation, and the sum of the column vectors is equal to (1, 1, 0) ^T during the addition operation, then the code word "10011" does not belong to the group code. Subgraph (c) is the selected SFPC set (Selected FPC), which contains 4 codewords, and the code distance is equal to 3. If the 2-bit input information is encoded with this codeword set, the on-chip bus can avoid crosstalk delay and provide error correction capability at the same time.

Step S350, if the number of code words that meet the requirements meets the number of encoded M-bit information, then execute step S360; otherwise, delete the matrix to be determined from the matrix set, and return to step S320;

Step S360, outputting a set of crosstalk-avoiding coding codewords that meet the requirements and have error correction capability.

By adopting the design method of a reliable on-chip bus of the present invention, it is possible to avoid adding an extra protection bus for the verification bus, and the wiring overhead is relatively small. Figure 10 shows the wiring overhead required for code word selection FTC (Selected FTC) using a suitable matrix, an inappropriate matrix, and FTC+HC coding directly adding Hamming codes. Using a suitable matrix can save 1 or more wires than an unsuitable matrix. Compared with FTC+HC, Good SFTC can save wiring overhead from 5% to 33%, and these saved wires are equivalent to the shielded wires used to protect the verification bus in the combined coding method. Figure 11 shows the wiring overhead required for FPC (Selected FPC) code word selection using a suitable matrix and an inappropriate matrix and FPC+HC coding directly adding Hamming codes. Also compared with FPC+HC, the encoding method of code word selection can save wiring overhead from 9% to 44%, and these saved wires are equivalent to the shielding wire used to protect the verification bus in combination with the encoding method.

By adopting the design method of a reliable on-chip bus of the present invention, the wiring overhead is small, and the power consumption on the bus is also small. Figure 12 shows the average power consumption on the bus when jumping from one codeword to another codeword when using the combined encoding method and the selective encoding method. The power consumption here is relative power consumption, it has nothing to do with the drive level of the bus and the capacitance of the bus. Compared with FTC+HC encoding, SFTC can save power consumption from 5% to 18%. Compared with FPC+HC, SFPC can save power consumption from 10% to 20%. Therefore, the encoding method based on codeword selection can save nearly 10% power consumption when the bus signal is transformed from one codeword to another.

The most important thing is that by adopting a reliable on-chip bus design method of the present invention, secondary crosstalk can be avoided, thereby ensuring the performance of time delay avoidance coding in the worst case. Figure 13 is a cross-sectional view of an integrated circuit under a 130nm process, which is used to simulate the falling waveform of the signal, and then evaluate the worst-case performance of the two CAC codes. The experimental environment uses the Field Solver in HSPICE, which can directly extract circuit parameters according to the size and doping of the circuit material. The physical size of the circuit is set according to the SMIC130 technology library, and the bus in this experiment is set on the second metal layer. As shown in Figure 13, the wire uses copper as the medium, the dielectric constant of the upper layer is set to 2.5, and the dielectric constant of the lower layer is 10. The width of the wires is set to the minimum value of 0.2um in the technical library, the spacing of the wires is 0.1um, the height of the wires is 0.6um, and the distance between the wires and the underlying silicon is 0.4um. According to the calculation formula of parallel plate capacitance C=ε*S/(4πkd), the ratio of the coupling capacitance to the ground capacitance is 3, and the common CAC rule can be used, and the influence of bus crosstalk is obvious.

Under 130nm process conditions, there will be obvious crosstalk effects between five adjacent wires. The experiment established a five-wire bus model, in which the third wire bus is the victim wire. Taking the FTC-based CAC as an example, when the codeword selection method is adopted, the vector pair <01110, 11011> can stimulate the worst time delay situation on the victim line. When the direct combination encoding method is adopted, the encoding line closest to the verification bus is subject to secondary crosstalk, and the influence of crosstalk will be the most serious. In the experiment, this line is set as the third wire of the bus model as the victim line. Likewise, the vector pair <01110, 11011> can excite the worst case delay on the victim line. However, the first three wires belong to the encoding bus, the last two buses belong to the verification bus, and the fourth wire is VDD as a shielding wire. According to the gate delay parameter of SMIC130, the time difference between the two bus lines will be within the transition delay. The jump time delay of this experiment is set to 0.5ns, and the time difference between the two groups of buses is set to 0.4ns. In addition, add the MA test vector pair <00100, 11011> to the experimental bus to obtain the worst crosstalk effect of the original bus, as a reference experiment.

Fig. 14 is the descending waveform diagram of three experiments obtained by using HSPICE. When using FTC+HC, the victim line is only affected by the crosstalk of the encoding bus at first, and the falling waveform is steep. When the level is close to the threshold level, the second crosstalk effect occurs, and the falling waveform suddenly becomes gentle, resulting in a larger falling delay. However, when the code word is used to select the encoding method, there will be no secondary crosstalk phenomenon, and the drop delay is small. Using the scale to measure, the worst time delay of codeword selection encoding is 0.82ns, combined encoding is 0.93ns, and the worst case of no encoding is 1.03ns. Therefore, the codeword selection encoding method can achieve a higher crosstalk delay avoidance effect.

Corresponding to a design method of a reliable on-chip bus of the present invention, the present invention also provides a reliable on-chip bus system, as shown in Figure 7, which includes:

The encoding unit 410 is a circuit that uses the SIS logic optimization tool to generate an optimized encoding logic from the codebook that contains the mapping relationship between the information set and the optimal codeword set, and implements it through a combinational circuit or a codeable logic array (PLA). It is set on the input port of the bus system to convert the information to be transmitted into the code on the bus;

The bus system unit 420 is designed according to the crosstalk-avoiding coding codeword set with error correction capability, and is used for transmission coding;

The crosstalk-avoiding codeword set with error correction capability is a codeword set determined according to the above-mentioned method for designing a reliable on-chip bus, and will not be repeated here.

The decoding unit 430 is a decoding book that will contain the mapping relationship between the optimal codeword set and the information set, and utilizes the S&S logic optimization tool to generate optimized decoding logic, and through a combinational circuit or an editable logic array (PLA) realized circuit. It is set on the input port of the bus system and is used to convert the code transmitted on the bus into information;

The checking unit 440 is used for finding and correcting errors encoded in transmission.

The verification unit, as shown in Figure 8, further includes:

Check matrix unit 441: recalculate the bus output codeword and the corresponding check matrix, and input the obtained result to the error decoding unit 442;

Error decoding unit 442: judge whether there is an error according to the input operation result, and input the error correction information to the correction unit;

Correction unit 443: correct the error of the corresponding bit of the codeword according to the error correction information;

The check matrix unit 441 calculates the code word output by the bus system unit 420 and the corresponding check matrix again, and the result obtained is input to the error decoding unit 442; the error decoding unit 442 determines whether there is an error according to the input operation result, and The error correction information is input to the correction unit, if the output result is equal to 0 ^T , there is no error in the code word transmission, and all outputs remain 0; otherwise, find out the column vector equal to the output result from the parity check matrix, and compare the column vector Outputs with the same vector position are set to 1 as error correction information. The correcting unit 443 corrects the error of the corresponding bit of the codeword according to the error correction information. When the error correction information is input as 0, it means that the corresponding bit in the codeword has no error and remains unchanged; when the error correction information is input as 1, it means that the corresponding bit in the codeword A bit goes wrong and the signal flips.

The corresponding parity check matrix refers to a matrix that selects a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set, and each parity check matrix is associated with a set of codeword sets that meet the parity check matrix correspond.

The present invention also provides a working method of a reliable on-chip bus system, as shown in Figure 9, comprising the following steps:

Step S100', according to the crosstalk-avoiding codeword set with error correction capability, map the information to be transmitted to the codewords in the set one by one, and transmit on the system bus;

The crosstalk-avoiding codeword set with error correction capability is a codeword set determined according to the above-mentioned method for designing a reliable on-chip bus, and will not be repeated here.

The information to be transmitted is converted into codes on the bus by using the codebook that contains the mapping relationship between the information set and the code word set.

Step S200', check and correct the outgoing codeword;

Step S210', the bus output code word and the corresponding parity check matrix are re-operated, and it is judged whether there is an error in the output operation result;

If the output result is equal to 0 ^T , there is no error in the codeword transmission, and all outputs remain 0; otherwise, find the column vector equal to the output result from the parity check matrix, and set the output at the same position as the column vector to 1 as error correction information.

Step S220', according to the error correction information, correct the error of the corresponding bit of the code word.

When the error correction information is input as 0, it means that the corresponding bit in the codeword has no error and remains unchanged; when the error correction information is input as 1, it means that the corresponding bit in the codeword has an error, and the signal is reversed.

As a possible implementation manner, as shown in the figure, it is assumed that an error occurs in the last bit of the code word "00111" during transmission, causing the code word to become "00110" at the receiving end. If the received codeword is operated with the verification equation {X|H·X ^T =0 ^T }, the result of the multiplication operation is that the column vector (h3, h4) is selected, and the result of the addition operation is (0, 0 , 1) ^T , so the error is found. At the same time, as shown in Figure 8(b), the result of the addition operation is exactly equal to the last column vector of the matrix H, so the error occurs in the last bit of the codeword. In this way, the last output line signal is set to 1, and the last bit of the codeword is flipped to correct errors. If the fault occurs in the first bit of the code word "00111", then the receiving end gets the code word "10111". The result of its operation with the check matrix is (0, 1, 0) ^T , which is the same as the first column vector of the check matrix H. Therefore, no matter any bit of the code word is wrong, the operation result with the parity check matrix can indicate the position of the error.

Step S300', converting the codeword into corresponding information and outputting it.

Utilize the decoding book containing the mapping relationship between the code word set and the information set, convert the code transmitted on the bus into information and output it.

The beneficial effects of the present invention are: 1. It can ensure the efficient and reliable operation of the global bus in the integrated circuit below the ultra-deep submicron process;

2. It can correct the signal reversal caused by noise on the bus, and has high commercial and academic value.

3. Avoid adding new Hamming codes and shielded wires to provide error correction capabilities, with less wiring overhead and lower power consumption;

4. The signals on the bus will change at the same time, which can avoid the secondary crosstalk effect caused by the direct introduction of Hamming code, and ensure the performance of the bus;

Other aspects and features of the present invention will be apparent to those skilled in the art by describing specific embodiments of the present invention in conjunction with the accompanying drawings.

The specific embodiments of the present invention have been described and illustrated above, and these embodiments should be considered as exemplary only, and are not used to limit the present invention, and the present invention should be interpreted according to the appended claims.

Claims (35)

1. a design method of reliable on-chip bus, it is characterized in that, utilize the parity check matrix of group code to avoid the sub-collection that has error-correcting ability from crosstalk avoiding encoding codeword set, constitute the crosstalk that possesses error-correcting ability and avoid encoding codeword The set is applied to the circuit design of the on-chip bus, which includes the following steps: A. Generate a codeword set according to the rules of crosstalk avoidance coding; B. According to the requirements, deduce the attribute of the parity check matrix of the group code; C. Optimizing all parity check matrices satisfying the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capability. 2. the design method of reliable on-chip bus according to claim 1, is characterized in that, described step A also further comprises: A1. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate inclusions, the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk are obtained; A2. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay; A3. Generate a codeword set according to the selected crosstalk avoidance code. 3. the design method of reliable on-chip bus according to claim 2, is characterized in that, described step B also further comprises: B1. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code; B2. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying the attribute. 4. The method for designing a reliable on-chip bus according to claim 3, characterized in that, in the step B1, if and only when the code distance is greater than or equal to 2K+1, the encoding can correct K-bit faults. 5. the design method of reliable on-chip bus according to claim 4, it is characterized in that, in described step B2, if and only if in the generating matrix of group code, add up to be equal to the column vector group of ^0T , their minimum row If the number of vectors is equal to a, the code distance of the group code is equal to a; the dimension m of the matrix column vector must not be less than log ₂ (n+1), where n is the number of bits of the code word. 6. the design method of reliable on-chip bus according to claim 5, is characterized in that, described step C also further comprises: C1. according to the method described in step A1, generate the crosstalk avoiding codeword set of N bits; C2. Judging whether all check matrices satisfying the attributes have been judged, if all judgments have been made, then perform step C3; otherwise, perform step C4; C3. Add 1 to N; C4. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set; C5. If the number of codewords that meet the requirements meets the number of encoded M-bit information, then step C6 is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2; C6. Outputting a crosstalk-avoiding coding codeword set that meets requirements and has error correction capabilities. 7. the design method of reliable on-chip bus according to claim 6, is characterized in that, in described step C4, in the process of selecting code word, if the code word in N bit crosstalk avoids the code word set to satisfy matrix to be determined In the check equation formed, the codeword is added to the set of codewords that meet the requirements; otherwise, the codeword is deleted. 8. A reliable on-chip bus system, characterized in that it comprises: Coding unit, which is set on the input port of the bus system, and is used to convert the information to be transmitted into the code on the bus; The bus system unit is designed according to the crosstalk-avoiding coding codeword set with error correction capability, and is used for transmission coding; A decoding unit, which is arranged on the input port of the bus system, is used to convert the code transmitted on the bus into information; The check unit is used to find and correct errors encoded in transmission. 9. The reliable on-chip bus system according to claim 8, characterized in that, the encoding unit is a code book that will contain information sets to the best code word set mapping relationship, and utilizes the SIS logic optimization tool to generate optimized encoding logic , and circuits realized by combinational circuits or programmable logic arrays. 10. The reliable on-chip bus system according to claim 8, characterized in that, in the bus system unit, the crosstalk with error correction capability avoids the encoding codeword set, which is a codeword determined according to the design method of the reliable on-chip bus gather. 11. reliable on-chip bus system according to claim 10, it is characterized in that, the design method of described reliable on-chip bus is to utilize the parity check matrix of group code to avoid crosstalk from crosstalk and select the subset that possesses error correction capability The set constitutes a set of crosstalk-avoiding encoded codewords with error correction capability, which is applied to the circuit design of the on-chip bus, which includes the following steps: A. Generate a codeword set according to the rules of crosstalk avoidance coding; B. According to the requirements, deduce the attribute of the parity check matrix of the group code; C. Optimizing all parity check matrices satisfying the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capability. 12. The reliable on-chip bus system according to claim 11, wherein said step A further comprises: A1. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate inclusions, the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk are obtained; A2. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay; A3. Generate a codeword set according to the selected crosstalk avoidance code. 13. The reliable on-chip bus system according to claim 12, wherein said step B further comprises: B1. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code; B2. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying the attribute. 14. The reliable on-chip bus system according to claim 13, characterized in that, in the step B1, if and only when the code distance is greater than or equal to 2K+1, the encoding can correct K-bit faults. 15. reliable on-chip bus system according to claim 14, it is characterized in that, in described step B2, if and only if in the generation matrix of group code, add and be equal to the column vector group of 0 ^T , their minimum column vector number is equal to a, then the code distance of the group code is equal to a; the dimension m of the matrix column vector must not be less than log ₂ (n+1), where n is the number of code words. 16. The reliable on-chip bus system according to claim 15, wherein said step C further comprises: C1. according to the method described in step A1, generate the crosstalk avoiding codeword set of N bits; C2. Judging whether all check matrices satisfying the attributes have been judged, if all judgments have been made, then perform step C3; otherwise, perform step C4; C3. Add 1 to N; C4. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select a codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set; C5. If the number of codewords that meet the requirements meets the number of encoded M-bit information, then step C6 is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2; C6. Outputting a crosstalk-avoiding coding codeword set that meets requirements and has error correction capabilities. 17. reliable on-chip bus system according to claim 16, it is characterized in that, in described step C4, in the process of selecting code word, if the code word in N bit crosstalk avoids the code word set to satisfy the matrix formation to be determined Check the equation, add the codeword to the set of codewords that meet the requirements; otherwise, the codeword is deleted. 18. The reliable on-chip bus system according to claim 8, characterized in that, the decoding unit is to utilize the SIS logic optimization tool to generate an optimized codebook that includes the optimal codeword set to the information set mapping relationship. Decoding logic and circuits implemented by combinational circuits or programmable logic arrays. 19. The reliable on-chip bus system according to claim 8, wherein the verification unit further comprises: Check matrix unit: recalculate the output code word of the bus system unit and the corresponding check matrix, and input the obtained result to the error decoding unit; Error decoding unit: judge whether there is an error according to the input operation result, and input the error correction information to the correction unit; Correction unit: correct the error of the corresponding bit of the code word according to the error correction information. 20. reliable on-chip bus system according to claim 19, is characterized in that, described corresponding parity check matrix, refers to from N bit crosstalk and avoids the codeword set, selects the matrix of the codeword set that meets the requirements, every A parity check matrix corresponds to a set of code words conforming to the parity check matrix. 21. A working method of a reliable on-chip bus system, characterized in that, comprising the following steps: A. According to the crosstalk-avoiding codeword set with error correction capability, the information to be transmitted is mapped to the codewords in the set one by one, and transmitted on the system bus; B. Check and correct the outgoing codeword; C. Convert the codeword into corresponding information and output it. 22. The working method of the reliable on-chip bus system according to claim 21 is characterized in that, in step A, the crosstalk avoiding code word set with error correction capability is determined according to the design method of the reliable on-chip bus collection of codewords. 23. The working method of the reliable on-chip bus system according to claim 22, characterized in that, in the step A, the information to be transmitted is converted into the code book on the bus by utilizing the codebook comprising the mapping relation of the information set to the codeword set encoding. 24. the working method of reliable on-chip bus system according to claim 22, is characterized in that, the design method of described reliable on-chip bus, comprises the following steps: A'. Generate a codeword set according to the rules of crosstalk avoidance coding; B'. According to the requirements, deduce the attribute of the check matrix of the group code; C'. Optimize all parity check matrices that satisfy the attributes to obtain the best parity check matrix to generate a crosstalk-avoiding codeword set with error correction capabilities. 25. The working method of reliable on-chip bus system according to claim 24, is characterized in that, described step A ' also further comprises: A1'. According to the semiconductor device process library instructions for bus wiring information, including physical size, wire material and substrate doping, get the ratio of coupling capacitance to ground capacitance and transmission delay without crosstalk; A2'. Combining the delay avoidance performance of different crosstalk avoidance codes, predict the upper limit of crosstalk avoidance delay; A3'. According to the selected crosstalk avoidance coding, a codeword set is generated. 26. The working method of reliable on-chip bus system according to claim 25, is characterized in that, described step B ' also further comprises: B1'. Refer to the requirements of the design manual for error correction capability, and determine the code distance of the corresponding group code; B2'. According to the code distance of the group code, deduce the attribute of the parity check matrix of the group code, so as to obtain all parity check matrices satisfying this attribute. 27. The working method of a reliable on-chip bus system according to claim 26, characterized in that, in said step B1', if and only when the code distance is greater than or equal to 2K+1, the encoding can correct the K-bit fault. 28. the working method of reliable on-chip bus system according to claim 27, it is characterized in that, in described step B2 ', if and only if in the generating matrix of group code, be equal to the column vector group of 0 ^T , their The minimum number of column vectors is equal to a, then the code distance of the group code is equal to a; the dimension m of the matrix column vector must not be less than log ₂ (n+1), where n is the number of bits of the code word. 29. The working method of reliable on-chip bus system according to claim 28, is characterized in that, described step C ' also further comprises: C1'. according to the method described in step A1', generate N-bit crosstalk avoiding codeword sets; C2'. Judging whether all check matrices satisfying the attribute have been judged, if all judgments have been made, then execute step C3'; otherwise execute step C4'; C3'. Add 1 to N; C4'. From all matrices that meet the requirements, select a matrix to be determined as the parity check matrix, and select the codeword set that meets the requirements from the N-bit crosstalk avoidance codeword set; C5'. If the number of codewords that meet the requirements meets the number of encoded M-bit information, step C6' is performed; otherwise, the matrix to be determined is deleted from the matrix set, and returns to step C2'; C6'. Output a crosstalk-avoiding encoding codeword set that meets the requirements and has error correction capabilities. 30. The working method of a reliable on-chip bus system according to claim 29, characterized in that, in the step C4', in the process of selecting a code word, if the code word in the N-bit crosstalk avoidance code word set meets the The check equation formed by the decision matrix adds the codeword to the set of codewords that meet the requirements; otherwise, the codeword is deleted. 31. The working method of reliable bus system on chip according to claim 29, is characterized in that, described step B also further comprises the step: B1. Calculate the bus output codeword and the corresponding parity check matrix again, and judge whether the output operation result is wrong; B2. According to the error correction information, correct the error of the corresponding bit of the code word. 32. the working method of reliable on-chip bus system according to claim 31, is characterized in that, described corresponding parity check matrix, refers to from N bit crosstalk avoids code word set, selects the code word set that meets requirements matrix, and each parity check matrix corresponds to a set of codewords conforming to the parity check matrix. 33. The working method of a reliable on-chip bus system according to claim 31, characterized in that, in the step B1, if the output result is equal to 0 ^T , then the code word transmission has no error, and all outputs remain 0; otherwise, from Find the column vector equal to the output result in the parity check matrix, and set the output at the same position as the column vector to 1 as error correction information. 34. The working method of the reliable on-chip bus system according to claim 33 is characterized in that, in the step B2, when the error correction information is input 0, it means that the corresponding bit in the code word has no error and remains unchanged; When the error information is input as 1, it means that there is an error in the corresponding bit in the code word, and the signal is reversed. 35. The working method of the reliable on-chip bus system according to claim 21, characterized in that, in the step C, the codes transmitted on the bus are transformed by utilizing the decoding book comprising the mapping relationship between the code word set and the information set After the information is output.

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