CN101226567A - Design method and system for reliable on-chip bus as well as working method thereof - Google Patents
Design method and system for reliable on-chip bus as well as working method thereof Download PDFInfo
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Abstract
The invention discloses a reliable on-chip bus design method, a system and a work method. The on-chip bus design method selects sub sets provided with error correcting ability from crosstalk coding-avoiding codeword sets by use of a check matrix of group code, forms a crosstalk coding-avoiding codeword set provided with error correcting ability, and is applied in on-chip bus circuit design. The method of the invention comprises: generating a codeword set according to the rules of crosslink coding-avoiding; deducing check matrix properties of group code; optimizing all check matrixes which satisfy the properties to obtain a best check matrix to generate crosstalk coding-avoiding codeword sets provided with error correcting ability. The invention can ensure that bus is free from impact of crosstalk delay at a lower wiring cost and power consumption under the condition that no secondary crosstalk is introduced and can correct signal turnover resulted by noises on the bus.
Description
Technical field
The present invention relates to the semiconductor process techniques field, mainly is the method and the design of VLSI (very large scale integrated circuit) (VLSI) fault tolerance (Fault Tolerance), particularly relates to a kind of method for designing and system and method for work thereof of reliable on-chip bus.
Background technology
Along with the door time delay constantly reduces, the time delay of long bus is remarkable day by day to the effect that can system reach high overall performance in the SOC (system on a chip) (SOC).Yet under sub-micro technology and GHZ frequency of operation, the effect of parasitic elements such as coupling capacitance and stray inductance is remarkable in the circuit.When signal generation saltus step, they can discharge and recharge (under sub-micro technology, mainly being that coupling capacitance plays a major role), make the correct response that can not get signal at output terminal.These influences mainly comprise crosstalk time-delay (Crosstalk-InducedDelay) and the spike of crosstalking (Crosstalk-Induced Glitch).Wherein, crosstalk time-delay has caused the part signal of bus to arrive output terminal at the appointed time, has a strong impact on the synchronous of signal.According to international semiconductor technology path figure, when system clock arrives 10GHZ, the time delay of this on-chip bus even can be suitable with clock frequency.In order to eliminate the influence that bus interference brings, guarantee the reliability of long bus, industry member need be continued to optimize system wiring, perhaps adopts conservative bus structure, promptly adds shielding line between adjacent wires.Preceding a kind of method need repeatedly be assessed and improve, and the complexity of aid is high; A kind of method in back not only increases area overhead, and can increase the time-delay and the power consumption of bus.
Therefore, the researcher designs to crosstalk accordingly and avoids coding (Crosstalk Avoidance Code is called for short CAC), avoids bus signals bad saltus step combination to occur, and then avoids crosstalk time-delay.Fig. 1 has provided the relative time delay that different saltus steps combination causes, and the saltus step combination of worst (↓, ↑, ↓) is than many 4 λ of time delay of best saltus step combination (↑, ↑, ↑), and wherein λ is the ratio of lead coupling capacitance and ground capacitance.Adopt the time delay upper limit of relative time delay, Delay=1+ λ (speech coding), Delay=1+2 λ that the CAC coding can be divided into (coding commonly used) and Delay=1+3 λ (avoiding the maximum delay coding) as CAC.And the rule of coding commonly used is divided into two classes, promptly forbids saltus step coding (Forbidden Transition Code is called for short FTC) and forbids vector coding (Forbidden Pattern Code is called for short FPC).Wherein, FTC require it code word and benchmark code word (constituting) composition of vector by alternate 01 to the time, forbid that saltus step appears in adjacent signals line simultaneously; FPC forbids subvector " 010 " and " 101 " occurring in its code word.These methods can greatly reduce the time delay expense of bus, and area overhead is less simultaneously, is a kind of desirable on-chip bus fault-tolerance approach.
Yet present coding method CAC can only avoid the crosstalk time-delay fault, can not correct because the signal upset that circuit noise brings.If the noise on the tolerance bus, the spike fault of crosstalking that comprising crosstalks brings then need be added new Hamming check sign indicating number on CAC, forms the combination coding with error correcting capability, as shown in Figure 2.But by the coding bus of CAC unit 001 generation and the check bus that is produced by ECC unit 002, there is multistage gate delay in two groups of buses, therefore need to increase the width of system clock pulse.The raising of meeting system for restricting dominant frequency like this.The more important thing is that the signal saltus step takes place check bus Kc, also can lag behind coding bus L.This late signal saltus step meeting cause the encoding secondary of bus is crosstalked.It has increased the saltus step time delay of signal, causes the bus system performance to reduce.
Simultaneously, newly-generated Hamming check sign indicating number is not possess the ability of avoiding crosstalk time-delay.And the information of check bus is used for error correction, can not change in signals transmission, therefore can not carry out the CAC coding to the Hamming check sign indicating number.As shown in Figure 2, check bus need add protective wire by unit 003, and the protection checkout line is avoided the influence of bus interference.Adopt this method, can increase the wiring expense of system, cause power consumption unnecessary on on-chip bus.
Summary of the invention
The object of the present invention is to provide a kind of method for designing and system and method for work thereof of reliable on-chip bus, it can not introduced under the prerequisite that secondary crosstalks, with less wiring expense and power consumption expense, guarantee that bus avoids the influence of crosstalk time-delay, and can correct on the bus because the signal that noise causes upset.
For realizing the method for designing of a kind of reliable on-chip bus that purpose of the present invention provides, be to utilize the check matrix of group code to avoid selecting to possess the coding codeword set subclass of error correcting capability from crosstalking, formation possesses crosstalking of error correcting capability and avoids the coding codeword set, be applied to the circuit design of on-chip bus, it comprises the following steps:
A. the regular generated codeword of avoiding according to crosstalking encoding is gathered;
B. as requested, the attribute of the check matrix of derivation group code;
C. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
Described steps A also further comprises:
A1. according to semiconductor device technology storehouse instructions to route bus information, comprise that physical size, lead material and substrate mix situation, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time crosstalk;
A2. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3. avoid coding according to selected crosstalking, the generated codeword set.
Described step B also further comprises:
B1. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2. according to group code code distance, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
Among the described step B1, code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
Among the described step B2, addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
Described step C also further comprises:
C1. according to steps A 1 described method, generate crosstalking of N position and avoid codeword set;
C2. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 then; Otherwise execution in step C4;
C3. N is added 1;
C4. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
If C5. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6; Otherwise matrix to be determined is deleted from set of matrices, returned step C2;
C6. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
Among the described step C4, in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes, this code word is added in the satisfactory codeword set if the N bit string is disturbed the code word of avoiding in the codeword set; Otherwise this code word is deleted.
For realizing that purpose of the present invention also provides a kind of reliable on-chip bus system, comprising:
Coding unit, it is set on the input port of bus system, and being used for to need information transmitted to change into coding on the bus;
The bus system unit avoids the coding codeword set to design according to possessing crosstalking of error correcting capability, is used for transfer encoding;
Decoding unit, it is set on the input port of bus system, and the coding that is used for transmitting on bus changes into information;
Verification unit, be used for finding and correcting encoder in the mistake of transmission.
Described coding unit is to comprise the code book that optimal codes set mapping relations are arrived in ensemble of communication, utilizes SIS logic optimization instrument to generate the codimg logic of optimizing, and passes through the circuit of combinational circuit or the realization of codified logic array.
In the bus system unit, described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of reliable on-chip bus and definite codeword set.
The method for designing of described reliable on-chip bus, be to utilize the check matrix of group code to avoid selecting to possess the coding codeword set subclass of error correcting capability from crosstalking, formation possesses crosstalking of error correcting capability and avoids the coding codeword set, is applied to the circuit design of on-chip bus, and it comprises the following steps:
A. the regular generated codeword of avoiding according to crosstalking encoding is gathered;
B. as requested, the attribute of the check matrix of derivation group code;
C. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
Described steps A also further comprises:
A1. according to semiconductor device technology storehouse instructions to route bus information, comprise that physical size, lead material and substrate mix situation, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time crosstalk;
A2. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3. avoid coding according to selected crosstalking, the generated codeword set.
Described step B also further comprises:
B1. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2. according to group code code distance, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
Among the described step B1, code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
Among the described step B2, addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
Described step C also further comprises:
C1. according to steps A 1 described method, generate crosstalking of N position and avoid codeword set;
C2. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 then; Otherwise execution in step C4;
C3. N is added 1;
C4. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
If C5. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6; Otherwise matrix to be determined is deleted from set of matrices, returned step C2;
C6. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
Among the described step C4, in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes, this code word is added in the satisfactory codeword set if the N bit string is disturbed the code word of avoiding in the codeword set; Otherwise this code word is deleted.
Described decoding unit is to gather the code book of ensemble of communication mapping relations with comprising optimal codes, the decoding logic of utilizing SIS logic optimization instrument generate to optimize, but and the circuit of realizing by combinational circuit or editorial logic array.
Described verification unit also further comprises:
The check matrix unit: with described bus system unit output code word and the computing once more of corresponding check matrix, the result who obtains is input to the mistake decoding unit;
The mistake decoding unit: whether the operation result judgement according to input is wrong, and error correction information is input to the correction unit;
Correct the unit:, correct the mistake of code word corresponding positions according to error correction information.
Described corresponding check matrix is meant to disturb from the N bit string and avoids the codeword set that select the matrix of satisfactory codeword set, each check matrix is all corresponding with one group of codeword set that meets this check matrix.
For realizing that purpose of the present invention also provides a kind of method of work of reliable on-chip bus system, comprises the following steps:
A. avoid coding codeword set according to possessing crosstalking of error correcting capability, information to be passed is mapped to code word in the set one by one, on system bus, transmit;
B. the code word that spreads out of is carried out verification and correct;
C. export after code word being converted into corresponding information.
In the steps A, described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of reliable on-chip bus and definite codeword set.
In the described steps A, utilize to comprise the code book of ensemble of communication, will need information transmitted to change into coding on the bus to the codeword set mapping relations.
The method for designing of described reliable on-chip bus comprises the following steps:
A '. avoid the regular generated codeword set of encoding according to crosstalking;
B '. as requested, the attribute of the check matrix of derivation group code;
C '. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
Described steps A ' also further comprise:
A1 '. to route bus information, comprise that physical size, lead material and substrate mix situation according to semiconductor device technology storehouse instructions, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time of crosstalking;
A2 '. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3 '. avoid coding according to selected crosstalking, the generated codeword set.
Described step B ' also further comprises:
B1 '. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2 '. according to group code code distance, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
Among the described step B1 ', code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
Among the described step B2 ', addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
Described step C ' also further comprises:
C1 '. according to steps A 1 ' described method, generate crosstalking of N position and avoid codeword set;
C2 '. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 ' then; Otherwise execution in step C4 ';
C3 '. N is added 1;
C4 '. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
C5 ' if. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6 '; Otherwise matrix to be determined is deleted from set of matrices, returned step C2 ';
C6 '. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
Among the described step C4 ', in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes, this code word is added in the satisfactory codeword set if the N bit string is disturbed the code word of avoiding in the codeword set; Otherwise this code word is deleted.
Described step B also further comprises step:
B1. bus is exported code word and the computing once more of corresponding check matrix, judged whether the operation result of output is wrong;
B2. according to error correction information, correct the mistake of code word corresponding positions.
Described corresponding check matrix is meant to disturb from the N bit string and avoids the codeword set that select the matrix of satisfactory codeword set, each check matrix is all corresponding with one group of codeword set that meets this check matrix.
Among the described step B1, if the output result equals 0
T, then codeword transmission does not have mistake, and all outputs remain 0; Otherwise, from check matrix, find out and export the column vector that the result equates, and the output identical with this column vector position is arranged to 1 as error correction information.
Among the described step B2, when error correction information imported 0, corresponding positions did not have mistake in the expression code word, remains unchanged; When error correction information imported 1, mistake appearred in corresponding positions in the expression code word, the signal upset.
Among the described step C, utilize to comprise the code book of codeword set, will after the coding that transmits on the bus changes into information, export to the ensemble of communication mapping relations.
Beneficial effect of the present invention is:
1. can guarantee global bus's high-efficiency reliable operation in the following integrated circuit of sub-micro technology;
2. can correct on the bus because the signal that noise causes upset possesses higher commerce and learning value.
3. avoided adding new Hamming code and shielding line provides error correcting capability, the wiring expense is less, and power consumption is lower;
4. the signal on the bus can change simultaneously, can avoid having guaranteed the performance of bus owing to directly introducing the secondary cross talk effects that Hamming code brings;
Description of drawings
Fig. 1 is the saltus step combination and the graph of a relation in relative time delay;
Fig. 2 is direct CAC coding synoptic diagram in conjunction with Hamming code;
Fig. 3 is the process flow diagram of the method for designing of the reliable on-chip bus of the present invention;
Fig. 4 determines to possess crosstalking of error correcting capability to avoid coding codeword set algorithm flow chart;
Fig. 5 is the number of codewords figure that the different check matrix is selected;
Fig. 6 is the example of code word selective rule;
Fig. 7 is reliable on-chip bus system structural representation;
Fig. 8 is the verification unit structural representation;
Fig. 9 is the process flow diagram of the method for work of reliable on-chip bus system.
Figure 10 is based on the wiring expense figure of the different fault-tolerant bus of FTC principle;
Figure 11 is based on the wiring expense figure of the different fault-tolerant bus of FPC principle;
Figure 12 is direct average power consumption figure in conjunction with coded system and code word selection coded system lead;
Figure 13 is a time-delay analysis circuit sectional view;
Figure 14 is bus level signal falling waveform figure.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the method for designing of a kind of reliable on-chip bus of the present invention and system and method for work thereof are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The method for designing of a kind of reliable on-chip bus of the present invention and system and method for work thereof, be to determine to possess crosstalking of error correcting capability by the method for designing of the reliable on-chip bus selected based on code word to avoid the coding codeword set, and avoid coding codeword set reliable design on-chip bus system, and utilize the reliable on-chip bus system transmission information that designs according to possessing crosstalking of error correcting capability.
Introduce the method for designing of a kind of reliable on-chip bus of the present invention in detail below in conjunction with above-mentioned target, it is to utilize the check matrix of group code to avoid selecting to possess the coding codeword set subclass of error correcting capability from crosstalking, formation possesses crosstalking of error correcting capability and avoids the coding codeword set, is applied to the circuit design of on-chip bus.
As shown in Figure 3 and Figure 4, comprise the following steps:
Step S100 avoids the regular generated codeword set of coding (Crosstalk Avoidance Code is called for short CAC) according to crosstalking;
Step S110 to route bus information, comprises that physical size, lead material and substrate mix situation according to semiconductor device technology storehouse instructions, obtains the ratio (λ) of coupling capacitance and direct earth capacitance and does not have the propagation delay time (t that crosstalks
0);
Step S120 avoids performance in conjunction with the time delay of different CAC codings, the prediction CAC time delay upper limit;
Adopt relative time delay as the CAC time delay upper limit, the CAC coding can be divided into speech coding (Delay=1+ λ), coding commonly used (Delay=1+2 λ) and avoid maximum delay coding (Delay=1+3 λ).Coding wherein commonly used is divided into two classes again, promptly forbids saltus step coding (FTC) and forbids vector coding (FPC).Calculate the actual time delay upper limit of different CAC, wherein actual time delay is propagation delay time (t
0) with the product in relative time delay (Delay).
The reference design instructions is selected appropriate C AC coding to the requirement of signal saltus step time delay.
Step S130 is according to selected CAC coding, generated codeword set;
Step S200, as requested, the attribute of the check matrix of derivation group code;
Step S210, reference design instructions determine the code distance of corresponding group code to the requirement of error correcting capability;
If algebra system＜Sn, o〉be a group, Sn is the code word complete or collected works of n position, add operation o is the step-by-step xor operator.
The non-empty subset that Cn is Sn is established in definition 1, if Cn also is a group, and is the subgroup of Sn, and then Cn is called group code.Ham (X, Y) the hamming distance of two code words of expression among the Cn, X wherein, Y represents two any code words.Minimum non-zero hamming distance is called the code distance of Cn.The number of signal 1 is called the weight of code word in the code word.Because among the group code Cn any two code word X and Y and still belong to group code Cn, so (X Y) equals the weight W (Z) of certain code word Z of group code to their hamming distance H am, and the code distance of group code also has corresponding relation with the weight of code word by that analogy.
The code distance of theorem 2 group code Cn equals the minimum weight of non-zero codeword in the group code, shown in equation 2.
Step S220, according to group code code distance, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute;
Addition equals 0 in the generator matrix of inference 1 and if only if group code
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a.
Simultaneously, the dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
Meeting the matrix that as above requires has a lot, and preferably, the present invention obtains the matrix that all meet the demands by selecting column vector and column vector permutatation, is optimized for step S300.
As a kind of embodiment, the hypothetical reference design instruction requires circuit to have the ability of correcting single error, and according to the derivation of theorem 1 and inference 1, the code distance of group code should equal 3, and the rarest 3 column vector additions equal 0 in its check matrix
TTherefore, corresponding check matrix must satisfy following two attributes:
1 check matrix does not have identical column vector, does not have vector 0 yet
T
There is the Vector Groups of being made up of 3 column vectors in 2 check matrixes, they with equal 0
T
Simultaneously, the dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
Step S300 is optimized all check matrixes that satisfy attribute, obtains best check matrix, possesses crosstalking of error correcting capability with generation and avoids the coding codeword set, sees also Fig. 4, Fig. 5 and Fig. 6;
As shown in Figure 5, different check matrix is selected the number of codewords difference that obtains.When check matrix was suitable, the number of codewords that selection obtains was more.Optimize check matrix and guaranteed when the information of coding M position, to search the code word sum and meet the requirements, and the minimum codeword set of the figure place of code word.The wiring expense that can guarantee bus system like this is less, and the power consumption expense is also less simultaneously.
Step S310 according to the described method of step S100, generates the CAC codeword set of N position;
Step S320 judges whether all check matrixes satisfy attribute are judged, if all judge, and execution in step S330 then; Otherwise execution in step S340;
Step S330 adds 1 with N;
Step S340 from all satisfactory matrixes, chooses a matrix to be determined as check matrix, from the CAC codeword set of N position, selects satisfactory codeword set;
In the process of selecting code word,, this code word is added in the satisfactory codeword set if the code word in the CAC codeword set of N position satisfies the check equations that matrix to be determined constitutes; Otherwise this code word is deleted.
If definition 2 group code Cn={X|HX
T=0
T, wherein taking advantage of operation is the step-by-step AND operator, any code word of X group code, and T represents transposition, H is the generator matrix (consistency desired result matrix) of group code, then equation { X|HX
T=0
TBe the growth equation (consistency desired result equation) of group code Cn, all code words all are to generate by equation.
As a kind of embodiment, Fig. 6 is that the code word of 5 codings is selected example.Subgraph (a) is according to the FPC rule, removes the code word that comprises " 101 " or " 010 " from 5 code word complete or collected works, and remaining 16 code words are exactly the FPC codeword set.Subgraph (b) is the check matrix H that code distance equals 3 group code, the check equations { X|HX that the code word of FPC need constitute by its
T=0
TJudge.If code word meets check equations, then code word belongs to the group code with error correcting capability.For example, the code word of FPC " 00111 " substitution check equations computing.At first take advantage of operation, and the column vector of matrix H (h3, h4, h5) selected; Add operation then, column vector (h3, h4, h5) and equal 0
TSo code word " 00111 " meets check equations, it belongs to group code.When code word " 10011 " the substitution check equations computing of FPC, column vector during multiplication (h1, h4, h5) selected, when adding computing column vector and equal (1,1,0)
T, then code word " 10011 " does not belong to group code.Subgraph (c) is to select the SFPC that obtains to gather (Selected FPC), and it comprises 4 code words, and code distance equals 3.If with 2 input informations of encoding with this codeword set, then on-chip bus can be avoided crosstalk time-delay simultaneously and error correcting capability is provided.
Step S350 is if the number of satisfactory code word satisfies the number of coding M position information, then execution in step S360; Otherwise matrix to be determined is deleted from set of matrices, returned step S320;
Step S360 exports and satisfactoryly possesses crosstalking of error correcting capability and avoid coding codeword set.
Adopt the method for designing of a kind of reliable on-chip bus of the present invention, can avoid to check bus adds extra protection bus, the wiring expense is less.Figure 10 utilizes suitable matrix, the wiring expense that the code word of inappropriate matrix is selected FTC (Selected FTC) and directly added the FTC+HC coding needs of Hamming code.Adopt suitable matrix to save 1 or multiple conducting wires more than inappropriate matrix.Compare with FTC+HC, Good SFTC can save from 5% to 33% wiring expense, the lead of these savings with combine coded system in be used to protect the shielding line of check bus suitable.Figure 11 adopts to utilize suitable matrix, the wiring expense that the code word of inappropriate matrix is selected FPC (Selected FPC) and directly added the FPC+HC coding needs of Hamming code.Compare with FPC+HC equally, the coded system that code word is selected can be saved from 9% to 44% wiring expense, the lead of these savings with combine coded system in also be used to protect the shielding line of check bus suitable.
Adopt the method for designing of a kind of reliable on-chip bus of the present invention, the wiring expense is less, and power consumed is also less on bus.When Figure 12 represents to adopt in conjunction with coded system and selection coded system, jump to the average power consumption that another code word consumes in bus from a code word.The power consumption here is relative power consumption, and it has nothing to do with the drive level of bus and the electric capacity of bus.Compare with the FTC+HC coding, SFTC can save from 5% to 18% power consumption expense.Compare with FPC+HC, SFPC can save from 10% to 20% power consumption expense.Therefore, when bus signals when a code word transforms to another code word, the coding method of selecting based on code word can be saved nearly 10% power consumption expense.
The most important thing is, adopt the method for designing of a kind of reliable on-chip bus of the present invention, can avoid secondary to crosstalk, and then guarantee that under worst case time delay avoids the performance of encoding.Figure 13 is the integrated circuit sectional view under the 130nm technology, and it is used to the falling waveform of simulating signal, and then assesses two kinds of CAC and be coded in performance under the worst case.Experimental situation adopts the Field Solver among the HSPICE, and it can be according to circuit material size, the direct extraction circuit parameter of doping situation.The physical size of circuit is provided with according to the SMIC130 technology bank, and the bus of this experiment all is arranged on the second layer metal layer.As shown in figure 13, lead adopts copper as medium, and the specific inductive capacity on upper strata is arranged to 2.5, and the specific inductive capacity of lower floor is 10.The width of lead is set to the minimum value 0.2um of technology bank, and the spacing of lead is 0.1um, and the lead height is 0.6um, and the distance of conductor spacing lower floor silicon is 0.4um.According to the computing formula C=ε * S/ (4 π kd) of parallel plate capacitor, coupling capacitance is 3 with the ratio of direct earth capacitance, adopts CAC rule commonly used to get final product, and the bus interference obvious effect.
Under the 130nm process conditions, have tangible cross talk effects between five adjacent leads.One five line bus model has been set up in experiment, and wherein the privates bus is the line of being injured.With the CAC based on FTC is example, when adopting the code word selection mode, vector is right＜and 01110,11011〉can be activated at the worst time delay situation on the line of being injured.When adopting directly in conjunction with coded system, crosstalk owing to being subjected to secondary with the line of codes that check bus is the most contiguous, cross talk effects can be the most serious.In experiment, this root line is arranged to the 3rd lead of bus model, as the line of being injured.Equally, the vector right＜01110,11011 can be activated at the worst time delay situation on the line of being injured.But first three root lead belongs to the coding bus, and latter two bus belongs to check bus, and wherein the 4th lead is the VDD as shielding line.According to the door delay parameter of SMIC130, the mistiming of two groups of buses can be within the saltus step time delay.The saltus step time delay of this experiment is made as 0.5ns, and the mistiming of two groups of buses is set to 0.4ns.In addition, on the experiment bus, add the MA test vector right＜00100,11011, obtain the worst cross talk effects of original bus, as with reference to experiment.
Figure 14 is the falling waveform figure that utilizes three experiments that HSPICE obtains.When adopting FTC+HC, the line of being injured at first only be subjected to the encoding cross talk effects of bus, falling waveform is steeper.When level during near threshold level, cross talk effects takes place for the second time, and falling waveform becomes suddenly gently, and the time delay that causes descending becomes greatly.And when adopting code word to select coded system, the secondary crosstalk phenomenon then can not appear, the decline time delay is less.Utilize scale to record, it is 0.82ns that code word is selected the worst time delay of coding, is 0.93ns in conjunction with coding, and the worst case when not encoding is 1.03ns.So code word is selected coded system can reach higher crosstalk time-delay and is avoided effect.
Corresponding to the method for designing of a kind of reliable on-chip bus of the present invention, the present invention also provides a kind of reliable on-chip bus system, and as shown in Figure 7, it comprises:
Described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of above-mentioned a kind of reliable on-chip bus and definite codeword set does not repeat them here.
Decoding unit 430 is to gather the code book of ensemble of communication mapping relations with comprising optimal codes, the decoding logic of having utilized S worker S logic optimization instrument to generate to optimize, but and the circuit of realizing by combinational circuit or editorial logic array (PLA).It is set on the input port of bus system, and the coding that is used for transmitting on bus changes into information;
Described verification unit as shown in Figure 8, also further comprises:
Check matrix unit 441: bus is exported code word and the computing once more of corresponding check matrix, and the result who obtains is input to mistake decoding unit 442;
Mistake decoding unit 442: whether the operation result judgement according to input is wrong, and error correction information is input to the correction unit;
Correct unit 443:, correct the mistake of code word corresponding positions according to error correction information;
Check matrix unit 441 is with 420 output code word and the computings once more of corresponding check matrix of bus system unit, and the result who obtains is input to mistake decoding unit 442; Whether mistake decoding unit 442 is judged wrong according to the operation result of input, and error correction information is input to the correction unit, if the output result equals 0
T, then codeword transmission does not have mistake, and all outputs remain 0; Otherwise, from check matrix, find out and export the column vector that the result equates, and the output identical with this column vector position is arranged to 1 as error correction information.Correct unit 443 according to error correction information, correct the mistake of code word corresponding positions, when error correction information imported 0, corresponding positions did not have mistake in the expression code word, remains unchanged; When error correction information imported 1, mistake appearred in corresponding positions in the expression code word, the signal upset.
Described corresponding check matrix is meant to disturb from the N bit string and avoids the codeword set that select the matrix of satisfactory codeword set, each check matrix is all corresponding with one group of codeword set that meets this check matrix.
The present invention also provides a kind of method of work of reliable on-chip bus system, as shown in Figure 9, comprises the following steps:
Step S100 ' avoids coding codeword set according to possessing crosstalking of error correcting capability, and information to be passed is mapped to code word in the set one by one, transmits on system bus;
Described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of above-mentioned a kind of reliable on-chip bus and definite codeword set does not repeat them here.
Utilization comprises ensemble of communication to the code book of codeword set mapping relations, will need information transmitted to change into coding on the bus.
Step S200 ' carries out verification and corrects the code word that spreads out of;
Step S210 ' exports code word and the computing once more of corresponding check matrix with bus, judges whether the operation result of output is wrong;
If the output result equals 0
T, then codeword transmission does not have mistake, and all outputs remain 0; Otherwise, from check matrix, find out and export the column vector that the result equates, and the output identical with this column vector position is arranged to 1 as error correction information.
Step S220 ' according to error correction information, corrects the mistake of code word corresponding positions.
When error correction information imported 0, corresponding positions did not have mistake in the expression code word, remains unchanged; When error correction information imported 1, mistake appearred in corresponding positions in the expression code word, the signal upset.
As a kind of embodiment, as shown in the figure, suppose to make a mistake in last position of code word in transmission course " 00111 ", cause code word to become " 00110 " at receiving end.If with the code word that receives again with check equations { X|HX
T=0
TCarrying out computing, the result who takes advantage of operation is that (h3, h4) selected, the result of add operation is (0,0,1) to column vector
T, so just find wrong.Shown in Fig. 8 (b), the result of add operation just in time equals last column vector of matrix H simultaneously, so wrong last position that occurs in code word.Like this, last root output line signal is put 1, and last bit flipping of code word is corrected a mistake.If fault occurs in first of code word " 00111 ", receiving end obtains code word " 10111 " so.The result of it and check matrix computing is (0,1,0)
T, first column vector of it and check matrix H is identical.So, no matter be to make a mistake in any position of code word, with the operation result of check matrix can misdirection the position.
Step S300 ' exports after code word is converted into corresponding information.
Utilization comprises the code book of codeword set to the ensemble of communication mapping relations, will export after the coding that transmits on the bus changes into information.
Beneficial effect of the present invention is: can guarantee global bus's high-efficiency reliable operation in the following integrated circuit of sub-micro technology 1.;
2. can correct on the bus because the signal that noise causes upset possesses higher commerce and learning value.
3. avoided adding new Hamming code and shielding line provides error correcting capability, the wiring expense is less, and power consumption is lower;
4. the signal on the bus can change simultaneously, can avoid having guaranteed the performance of bus owing to directly introducing the secondary cross talk effects that Hamming code brings;
In conjunction with the drawings to the description of the specific embodiment of the invention, others of the present invention and feature are conspicuous to those skilled in the art.
More than specific embodiments of the invention are described and illustrate it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (35)
1. the method for designing of a reliable on-chip bus, it is characterized in that, utilize the check matrix of group code to avoid selecting to possess the coding codeword set subclass of error correcting capability from crosstalking, formation possesses crosstalking of error correcting capability and avoids the coding codeword set, be applied to the circuit design of on-chip bus, it comprises the following steps:
A. the regular generated codeword of avoiding according to crosstalking encoding is gathered;
B. as requested, the attribute of the check matrix of derivation group code;
C. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
2. the method for designing of reliable on-chip bus according to claim 1 is characterized in that, described steps A also further comprises:
A1. according to semiconductor device technology storehouse instructions to route bus information, comprise that physical size, lead material and substrate mix situation, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time crosstalk;
A2. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3. avoid coding according to selected crosstalking, the generated codeword set.
3. the method for designing of reliable on-chip bus according to claim 2 is characterized in that, described step B also further comprises:
B1. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2. according to the code distance of group code, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
4. the method for designing of reliable on-chip bus according to claim 3 is characterized in that, among the described step B1, code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
5. the method for designing of reliable on-chip bus according to claim 4 is characterized in that, among the described step B2, addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
6. the method for designing of reliable on-chip bus according to claim 5 is characterized in that, described step C also further comprises:
C1. according to steps A 1 described method, generate crosstalking of N position and avoid codeword set;
C2. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 then; Otherwise execution in step C4;
C3. N is added 1;
C4. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
If C5. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6; Otherwise matrix to be determined is deleted from set of matrices, returned step C2;
C6. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
7. the method for designing of reliable on-chip bus according to claim 6, it is characterized in that, among the described step C4, in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes if the N bit string is disturbed the code word of avoiding in the codeword set, this code word is added in the satisfactory codeword set; Otherwise this code word is deleted.
8. a reliable on-chip bus system is characterized in that, comprising:
Coding unit, it is set on the input port of bus system, and being used for to need information transmitted to change into coding on the bus;
The bus system unit avoids the coding codeword set to design according to possessing crosstalking of error correcting capability, is used for transfer encoding;
Decoding unit, it is set on the input port of bus system, and the coding that is used for transmitting on bus changes into information;
Verification unit, be used for finding and correcting encoder in the mistake of transmission.
9. reliable on-chip bus system according to claim 8, it is characterized in that, described coding unit, be to comprise the code book of ensemble of communication to optimal codes set mapping relations, utilize SIS logic optimization instrument to generate the codimg logic of optimizing, and pass through the circuit of combinational circuit or the realization of codified logic array.
10. reliable on-chip bus system according to claim 8 is characterized in that, in the bus system unit, described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of reliable on-chip bus and definite codeword set.
11. reliable on-chip bus system according to claim 10, it is characterized in that, the method for designing of described reliable on-chip bus, be to utilize the check matrix of group code to avoid selecting to possess the coding codeword set subclass of error correcting capability from crosstalking, formation possesses crosstalking of error correcting capability and avoids the coding codeword set, be applied to the circuit design of on-chip bus, it comprises the following steps:
A. the regular generated codeword of avoiding according to crosstalking encoding is gathered;
B. as requested, the attribute of the check matrix of derivation group code;
C. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
12. reliable on-chip bus system according to claim 11 is characterized in that, described steps A also further comprises:
A1. according to semiconductor device technology storehouse instructions to route bus information, comprise that physical size, lead material and substrate mix situation, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time crosstalk;
A2. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3. avoid coding according to selected crosstalking, the generated codeword set.
13. reliable on-chip bus system according to claim 12 is characterized in that, described step B also further comprises:
B1. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2. according to the code distance of group code, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
14. reliable on-chip bus system according to claim 13 is characterized in that, among the described step B1, code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
15. reliable on-chip bus system according to claim 14 is characterized in that, among the described step B2, addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
16. reliable on-chip bus system according to claim 15 is characterized in that, described step C also further comprises:
C1. according to steps A 1 described method, generate crosstalking of N position and avoid codeword set;
C2. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 then; Otherwise execution in step C4;
C3. N is added 1;
C4. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
If C5. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6; Otherwise matrix to be determined is deleted from set of matrices, returned step C2;
C6. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
17. reliable on-chip bus system according to claim 16, it is characterized in that, among the described step C4, in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes if the N bit string is disturbed the code word of avoiding in the codeword set, this code word is added in the satisfactory codeword set; Otherwise this code word is deleted.
18. reliable on-chip bus system according to claim 8, it is characterized in that, described decoding unit, be to comprise the code book that optimal codes is gathered the ensemble of communication mapping relations, the decoding logic of utilizing SIS logic optimization instrument generate to optimize, but and the circuit of realizing by combinational circuit or editorial logic array.
19. reliable on-chip bus system according to claim 8 is characterized in that, described verification unit also further comprises:
The check matrix unit: with described bus system unit output code word and the computing once more of corresponding check matrix, the result who obtains is input to the mistake decoding unit;
The mistake decoding unit: whether the operation result judgement according to input is wrong, and error correction information is input to the correction unit;
Correct the unit:, correct the mistake of code word corresponding positions according to error correction information.
20. reliable on-chip bus system according to claim 19, it is characterized in that, described corresponding check matrix, be meant to disturb and avoid the codeword set from the N bit string, select the matrix of satisfactory codeword set, each check matrix is all corresponding with one group of codeword set that meets this check matrix.
21. the method for work of a reliable on-chip bus system is characterized in that, comprises the following steps:
A. avoid coding codeword set according to possessing crosstalking of error correcting capability, information to be passed is mapped to code word in the set one by one, on system bus, transmit;
B. the code word that spreads out of is carried out verification and correct;
C. export after code word being converted into corresponding information.
22. the method for work of reliable on-chip bus system according to claim 21 is characterized in that, in the steps A, described possess crosstalking of error correcting capability and avoid coding codeword set, is according to the method for designing of reliable on-chip bus and definite codeword set.
23. the method for work of reliable on-chip bus system according to claim 22 is characterized in that, in the described steps A, utilizes to comprise the code book of ensemble of communication to the codeword set mapping relations, will need information transmitted to change into coding on the bus.
24. the method for work of reliable on-chip bus system according to claim 22 is characterized in that, the method for designing of described reliable on-chip bus comprises the following steps:
A '. avoid the regular generated codeword set of encoding according to crosstalking;
B '. as requested, the attribute of the check matrix of derivation group code;
C '. all check matrixes that satisfy attribute are optimized, obtain best check matrix, possess crosstalking of error correcting capability with generation and avoid the coding codeword set.
25. the method for work of reliable on-chip bus system according to claim 24 is characterized in that, described steps A ' also further comprise:
A1 '. to route bus information, comprise that physical size, lead material and substrate mix situation according to semiconductor device technology storehouse instructions, obtain the ratio of coupling capacitance and direct earth capacitance and do not have the propagation delay time of crosstalking;
A2 '. avoid performance in conjunction with the different time delays of avoiding encoding of crosstalking, prediction is crosstalked and is avoided the time delay upper limit;
A3 '. avoid coding according to selected crosstalking, the generated codeword set.
26. the method for work of reliable on-chip bus system according to claim 25 is characterized in that, described step B ' also further comprises:
B1 '. the reference design instructions is determined the code distance of corresponding group code to the requirement of error correcting capability;
B2 '. according to the code distance of group code, the attribute of the check matrix of derivation group code is to draw all check matrixes that satisfy this attribute.
27. the method for work of reliable on-chip bus system according to claim 26 is characterized in that, among the described step B1 ', code distance that and if only if is during more than or equal to 2K+1, and coding can be corrected K position fault.
28. the method for work of reliable on-chip bus system according to claim 27 is characterized in that, among the described step B2 ', addition equals 0 in the generator matrix of group code that and if only if
TThe column vector group, their minimum column vector number equals a, then the code distance of group code equals a; The dimension m of rectangular array vector must be not less than log
2(n+1), wherein n is the figure place of code word.
29. the method for work of reliable on-chip bus system according to claim 28 is characterized in that, described step C ' also further comprises:
C1 '. according to steps A 1 ' described method, generate crosstalking of N position and avoid codeword set;
C2 '. judge whether all check matrixes satisfy attribute are judged, if all judge, execution in step C3 ' then; Otherwise execution in step C4 ';
C3 '. N is added 1;
C4 '. from all satisfactory matrixes, choose a matrix to be determined, disturb from the N bit string and avoid the codeword set, select satisfactory codeword set as check matrix;
C5 ' if. the number of satisfactory code word satisfies the number of coding M position information, then execution in step C6 '; Otherwise matrix to be determined is deleted from set of matrices, returned step C2 ';
C6 '. export and satisfactoryly possess crosstalking of error correcting capability and avoid coding codeword set.
30. the method for work of reliable on-chip bus system according to claim 29, it is characterized in that, among the described step C4 ', in the process of selecting code word, satisfy the check equations that matrix to be determined constitutes if the N bit string is disturbed the code word of avoiding in the codeword set, this code word is added in the satisfactory codeword set; Otherwise this code word is deleted.
31. the method for work of reliable on-chip bus system according to claim 29 is characterized in that, described step B also further comprises step:
B1. bus is exported code word and the computing once more of corresponding check matrix, judged whether the operation result of output is wrong;
B2. according to error correction information, correct the mistake of code word corresponding positions.
32. the method for work of reliable on-chip bus system according to claim 31, it is characterized in that, described corresponding check matrix, be meant to disturb and avoid the codeword set from the N bit string, select the matrix of satisfactory codeword set, each check matrix is all corresponding with one group of codeword set that meets this check matrix.
33. the method for work of reliable on-chip bus system according to claim 31 is characterized in that, among the described step B1, if the output result equals 0
T, then codeword transmission does not have mistake, and all outputs remain 0; Otherwise, from check matrix, find out and export the column vector that the result equates, and the output identical with this column vector position is arranged to 1 as error correction information.
34. the method for work of reliable on-chip bus system according to claim 33 is characterized in that, among the described step B2, when error correction information imported 0, corresponding positions did not have mistake in the expression code word, remains unchanged; When error correction information imported 1, mistake appearred in corresponding positions in the expression code word, the signal upset.
35. the method for work of reliable on-chip bus system according to claim 21 is characterized in that, among the described step C, utilizes to comprise the code book of codeword set to the ensemble of communication mapping relations, will export after the coding that transmits on the bus changes into information.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103444144A (en) * | 2011-02-17 | 2013-12-11 | 洛桑联邦理工学院 | Methods and systems for noise resilient, pin-fficient and low power communications with sparse signaling codes |
| CN104699578A (en) * | 2015-01-09 | 2015-06-10 | 同济大学 | Constant-temperature instruction level self-testing method for testing time delay faults in inner heating manner |
| CN103780266B (en) * | 2012-12-21 | 2016-11-23 | 北京信息科技大学 | One does not increase number of buses purpose and avoids crosstalk coded method and device |
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| US6529979B1 (en) * | 1999-11-08 | 2003-03-04 | International Business Machines Corporation | Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement |
| CN1975635B (en) * | 2006-12-28 | 2011-01-05 | 陈曦 | Enhanced wishbone on-chip bus for leading-in bus code |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103444144A (en) * | 2011-02-17 | 2013-12-11 | 洛桑联邦理工学院 | Methods and systems for noise resilient, pin-fficient and low power communications with sparse signaling codes |
| CN103444144B (en) * | 2011-02-17 | 2016-12-14 | 洛桑联邦理工学院 | Sparse signaling code is utilized to carry out noise resilience, high pin efficiency and the method and system of low power communication |
| CN103780266B (en) * | 2012-12-21 | 2016-11-23 | 北京信息科技大学 | One does not increase number of buses purpose and avoids crosstalk coded method and device |
| CN104699578A (en) * | 2015-01-09 | 2015-06-10 | 同济大学 | Constant-temperature instruction level self-testing method for testing time delay faults in inner heating manner |
| CN104699578B (en) * | 2015-01-09 | 2017-12-26 | 同济大学 | The constant temperature instruction-level self-test method of heating mode detection delay failure within a kind of |
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