CN101226560B - Algorithm design system and method for implementing DSP functional check - Google Patents
Algorithm design system and method for implementing DSP functional check Download PDFInfo
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Abstract
The invention relates to an algorithm design system to realize DSP functional verification, which comprises a separate algorithm layer entity and a correlation layer entity, wherein the algorithm layer entity is to design a plurality of algorithm entities; the correlation layer entity is to describe the correlation of algorithm entities by use of a graph data structure, a top point in the graph data structure is to map an algorithm entity, that is, through an ancestor-type pointer which is inherited by all algorithms entities an algorithm entity transfer is realized; an edge in the graph data structure is to map a data flow channel between the algorithm entities, that is, virtual interface write and read functions of ancestor type definitions are to realize connection between the algorithm entities and to realize Box function through re-writing the write and read functions. The invention makes technicians only care about detail algorithm realization by itself without consideration of algorithm correlation, thereby greatly lowering software development complexity and speeding up software development.
Description
Technical field
The present invention relates to the design verification technology of digital signal processor (DSP, Digital Signal Processor), relate in particular to by the system and method for Software tool realization to the DSP functional verification.
Background technology
Along with the progress of semiconductor technology and a large amount of employings of industrial civil area, in recent years, the DSP price was significantly reduced, and performance improves constantly, just, enter communication, Industry Control and consumer field, day by day become the important foundation stone of modern information industry with irresistible trend.
Because DSP is different from general flush bonding processor, it is to be used for moving complicated signal processing algorithm.The DSP technology often relates to two branches, one is large scale integrated circuit (IC, the Integrated Circuit) design that hardware is implemented, and another then is the algorithm design of software verification, so as to DSP algorithm function module is simulated, thus the correctness of checking DSP function IC design.
Existing algorithm design C pattern (C model) tool software is at the inner called after Puma of development group, as shown in Figure 1.By this figure as can be seen, this tool software includes two parts content: the one, the algorithm process part, as the algorithm process among Fig. 11, algorithm process 2 ... and algorithm process n is illustrated in the polyalgorithm processing module of this tool software design; Another then is the data flow path between each algorithm processing module, for example (,) among Fig. 1 with the data flow path of cascade system, it expresses the input-output data stream of an algorithm processing module.At this, algorithm process (abbreviation algorithm) part might as well be called Box, the data flow path between each Box is called Pin.
Scheme shown in Figure 1 will act on the algorithms of different of same data stream and handle separation preferably, simplify program development, promote the reusability and the maintainability of software.But when the systematic comparison that constitutes is big, the also corresponding increase of its complexity.Fig. 2 has represented that in the algorithm process model of above-mentioned cascade, the specific implementation flow chart for each algorithm comprises the steps:
201: it is true (True) still vacation (False) that inquiry input allows sign, is execution in step 202 very then, is vacation process ends then;
Check promptly whether output Pin is empty, have only when exporting and just can carry out when Pin is empty, otherwise, can not carry out this processing.This is to read the output data that all algorithms at the corresponding levels produce because need to wait for the next stage algorithm, not so, can cause valid data to be capped.When the afterbody that is in the algorithm chain, output condition allows to carry out all the time.At this moment, last data recipient is a file.
202: the data whether inquiry input-buffer (Input Buffer) is still waiting to handle; If have, just do not carry out the work that data are read in, otherwise can wash out the valid data of Input Buffer; If no, just carry out the work that data are read in;
Whether 203 inquiry input ports (Inport) connect Pin (being the data flow path between the algorithm process Box), it is execution in step 204 then, otherwise execution in step 213 (Pin is more preferential than file f ile, has only just to obtain the input data under the situation that does not connect Pin from file);
204: whether inquiry has data in the Pin, is execution in step 205 then, otherwise execution in step 213;
205: read in new pending data to Input Buffer;
206: judge whether Pin has read sky; Be execution in step 207 then, otherwise execution in step 208;
207: the input of upper level algorithm is set allows to be masked as True (refer step 212);
208: carry out necessary algorithm process;
209: judge whether to output to file; Be execution in step 210 then, otherwise execution in step 211;
210: the result is write in the file;
Each algorithm can output to file, and this does not influence and outputs to next stage, and this is that program debug (debug) provides very big convenience.
211: the result is write among the output Pin (having guaranteed that in step 201 it is empty exporting pin, so can not cover valid data);
212: the input that algorithm at the corresponding levels is set allows to be masked as False, process ends;
This step needs and step 207 cooperates understanding.In order in step 201 is checked, to guarantee to wait until in the step 207 of next stage algorithm at it and to have taken current output data away, can do further output just current algorithm is set again.
213: whether inquiry Inport connects input file (Input File), is execution in step 214 then, otherwise process ends;
214: read in valid data from file and handle (this behavior that is first algorithm usually), process ends.
The core of this flow process such as Fig. 3 institute, current (corresponding levels) algorithm output data is in output Pin, must wait for that next stage algorithm (Box m+1) reads these data fully, could further export other valid data, be that upper level algorithm (Box m-1) is imported writing of data to algorithm at the corresponding levels (Box m), show; This has just relied on the step 212 of Fig. 2 Two-Level Algorithm and step 207 to cooperatively interact and has finished.
This shows that the existing algorithm realization flow makes the algorithm engineering teacher when writing algorithm related the mixing between algorithm and the algorithm, should take algorithm realization itself into account, takes the association between the algorithm again into account.In fact the algorithm engineering teacher only need be concerned about step 208, and for back a kind of processing (step 207 and step 212), is not have direct relation for the internuncial consideration of algorithm and algorithm itself fully.
Therefore need further upgrade to existing algorithm design system, the functional module of partitioning algorithm design software more meticulously, with related the separating between algorithm and the algorithm, make the algorithm engineering teacher when carrying out algorithm design, can concentrate one's energy to consider algorithm realization itself, and need too much not take the connectivity problem of algorithm into account, thereby reduce the complicacy of algorithm development.
Summary of the invention
Technical matters to be solved by this invention provides a kind of algorithm design system and method for the DSP of realization design verification, the functional module of partitioning algorithm design software meticulously, thus reduce the complicacy of algorithm development.
In order to solve the problems of the technologies described above, the invention provides a kind of algorithm design system of realizing the digital signal processor DSP functional verification, comprise the algorithm layer entity and the associated layers entity that are separated from each other, wherein:
The algorithm layer entity is used to design the polyalgorithm entity;
The associated layers entity is used for adopting graph data structure to describe the interconnecting relation to algorithm entity, and a summit in the graph data structure is used to shine upon an algorithm entity, and a limit in the graph data structure is used for a data circulation road between the mapping algorithm entity.
Further, to be the summit realize mapping to this algorithm entity by the entry address of pointing to mapped algorithm entity in described mapping, and mapping to the data circulation road is realized by the interface of definition in the limit; Write the function of importing data or reading the operation implementation algorithm entity of output data by access interface.
Further, the data of current algorithm entity output is controlled at the next stage algorithm entity and carries out after reading valid data in the data output channel of current algorithm entity.
In order to solve the problems of the technologies described above, the invention provides a kind of algorithm design method that realizes the digital signal processor DSP functional verification, may further comprise the steps:
(a) interconnecting relation with algorithm entity separates with algorithm entity, is abstracted into associated layers;
(b) interconnecting relation with associated layers adopts graph data structure to describe, and a summit in the graph data structure is used to shine upon an algorithm entity; A limit in the graph data structure is used for a data circulation road between the mapping algorithm entity.
Further, to be the summit realize mapping to this algorithm entity by the entry address of pointing to mapped algorithm entity for step (b) mapping, and mapping to the data circulation road is realized by the interface of definition in the limit; Import the function that reads the implementation algorithm entity of writing of data or output data by access interface.
Further, the pointer of ancestors' class all being inherited by all algorithm entities of the entry address of step (b) algorithm entity points to; Interface comprises that the virtual interface of ancestors' class definition writes function and read function, write function or read function and realize described algorithm entity by rewriting, write function and carry out and to write the input data by calling, read function and carry out and read output data from algorithm entity by calling to algorithm entity.
Further, write the valid data length that the transmission parameter of function contains input port sequence number, input-buffer pointer and writes; The valid data length that the described transmission parameter of reading function contains output port sequence number, output buffers pointer and reads.
Further, the realization of step (b) graph data structure further comprises step:
(b1) according to the realization of concrete integrated circuit (IC) chip, design of graphics, and figure sorted;
(b2) figure is from first to last traveled through each summit, the algorithm entity that it shines upon is called on the summit that meets service condition.
Further, service condition is meant that the output data circulation road of current algorithm entity is for empty.
Further, judge by the rreturn value of writing function and the rreturn value of reading function whether the output data circulation road is empty, the rreturn value of promptly writing function makes valid data amount minimizing in the output data circulation road, the rreturn value of reading function makes that the increase of valid data amount equals initial value in the output data circulation road, and then the output data circulation road is empty.
Adopt system and method provided by the invention, owing to effectively algorithm itself is separated with the interconnected of algorithm, making the slip-stick artist who writes algorithm only need pay close attention to concrete algorithm realizes, and needn't too much consider its interconnect problem, so the complicacy of software development is reduced greatly, can quicken the exploitation of software, also can improve the reliability of software.
Description of drawings
Fig. 1 is the structural representation of existing algorithm design system Puma;
Fig. 2 is for adopting the process flow diagram of existing algorithm design specific implementation;
Fig. 3 is the explanation to algorithm interconnect problem in the algorithm design process shown in Figure 2;
Fig. 4 is an algorithm design system Puma structural representation provided by the invention;
Fig. 5 is the realization flow figure with Puma figure of the present invention;
Fig. 6 is the process flow diagram of implementation algorithm entity function of the present invention;
Fig. 7 is the application example of Puma of the present invention.
Embodiment
A kind of algorithm design system of realizing the DSP functional verification provided by the invention comprises algorithm layer entity and associated layers entity, wherein:
The algorithm layer entity is used to design polyalgorithm entity B ox;
The associated layers entity is used for carrying out abstract to the interconnecting relation of algorithm entity; Wherein, this interconnecting relation adopts that common data structure---figure describes, and the summit among the figure is used to shine upon an algorithm entity, and the pointer of ancestors' class inheriting by all algorithm entities is realized calling this algorithm entity; Limit among the figure (Edge) is used for a data circulation road Pin between the mapping algorithm entity, and the virtual interface write of this ancestors' class definition, read function are used for the connection of implementation algorithm entity, by rewriteeing the function of this write, read function realization Box.
A kind of algorithm design method that realizes the DSP functional verification provided by the invention may further comprise the steps:
(a) interconnecting relation with algoritic module separates with algoritic module, and is abstracted into associated layers;
(b) adopt graph data structure to describe this associated layers, the summit among the figure (Vertex) is used to shine upon an algorithm entity (Box), and algorithm entity of pointed of ancestors' class inheriting by all algorithm entities is realized calling this algorithm entity; Limit among the figure (Edge) is used for the data circulation road (Pin) between the mapping algorithm entity, and the virtual interface write of this class definition, read function are used for the connection of implementation algorithm entity, by rewriteeing the function of this write, read function implementation algorithm entity.
Describe technique scheme of the present invention in detail below in conjunction with specific embodiments and the drawings.
The present invention is for the function of partitioning algorithm design software module more meticulously, consideration separates itself the connection and algorithm of algorithm, takes out associated layers on the algorithm layer, as shown in Figure 4, and employing common data structure---" figure " describes the interconnecting relation of each algorithm entity.Wherein: the data element in summit (Vertex) representative " figure " is used herein to algorithm entity of mapping; Association in limit (Edge) representative " figure " between two summits is used herein to the data flow path between the mapping algorithm entity.The concrete implication of Vertex and Edge has clearly definition in " data structure " textbook.
Comparison diagram 1 can be clearly seen that existing P uma system is a single layer structure, and being connected between algorithm and the algorithm mixes; And Puma of the present invention system is on existing P uma basis, connection between the algorithm and algorithm are separated itself and takes out associated layers.The benefit of doing like this is: the function of algorithm design software module is divided clear and definite and single more.The slip-stick artist who writes algorithm only need pay close attention to concrete algorithm and realize, and does not need to consider interconnected problem.In like manner, the abstract interconnecting relation that comes out represents that with " figure " this data structure it realizes needn't considering fully the actual meaning of representing of summit (Vertex) and limit (Edge) institute, and the only processing operation relevant with interconnecting relation.
About " figure " is the most complicated a kind of in all data structures, just because of this, is significant with its independent realization.Because " figure " this interconnected intrinsic abstract attribute of describing layer can make it be applied in easily in the description that things concerns widely.Through discussing and test the associated layers that takes out fully, can accelerate the exploitation of similar software greatly, improve the reliability of software.
Same array, chained list and tree are the same, and " figure " also is a kind of data structure that people were used to know.The present invention has realized figure on program.Utilize it, make the work of algorithm design greatly simplify.From algorithm author's angle, it is just passable that the algorithm engineering teacher only need finish the work of the step 208 among Fig. 2, do not need to carry out any internuncial judgement and processing.
The program circuit of Puma realization of the present invention " figure " comprises the steps: as shown in Figure 5
501:, make up in " figure " according to the realization of concrete IC chip;
See also Fig. 6, U among the figure
0～U
10All represent the summit, the line representative edge between summit and the summit.
502: " figure " implemented ordering, guarantee the operational efficiency of " figure ";
503: the preparation that each summit in " figure " is from first to last traveled through;
504: check whether a summit meets service condition, if, execution in step 505, execution in step 506 then if not;
So-called service condition is meant that calling algorithm output data at the corresponding levels arrives before the output Pin, and whether the next stage algorithm has read these data fully, and whether promptly export Pin is empty.
505: the algorithm to this summit mapping calls;
506: point to next summit;
507: judge whether that all summits are all traversed, if process ends is then then returned step 504 if not and carried out.
Below the mapping between " figure " (set on summit and limit) and the specific algorithm is described as follows:
All algorithms are all inherited same ancestors' class CAlgBase in the system of present embodiment, and it has defined two virtual interface write, read function, promptly
class?CAlgBase{
public：
virtual?int?Write(int?index，char*buf，int?len)；
virtual?int?Read(int?index，char*buf，int?len)；
}；
At this, algorithm box can regard a functional module as, and it is rewriteeing write, and read realizes during function that the content that also is about to algorithm Box writes in write or the read function body; And Write, Read function can regard input, the output interface of this functional module respectively as.
Wherein, call Write and promptly write the input data to index input port (Inport) input-buffer (buf) of this algorithm box, its valid data length is len.The rreturn value of Write has been represented the algorithm actual treatment and how much has been imported data.
Call Read promptly from index output port (Outport) reading of data of this algorithm box, data are placed among the output buffers buf that effective length is len.The rreturn value of Read is represented actual how many valid data that returned.
Parameter index during the Write function call represents the input port sequence number among the input Pin of this algorithm box1; The parameter index during the Read function call correspondingly represents the output port sequence number of the output Pin of this algorithm box1, and promptly an algorithm box may have a plurality of input ports or a plurality of output port.
The pointer that all contains class CAlgBase in the summit of each " figure " points to different algorithm entities with it, to realize calling the respective algorithms entity.Concrete algorithm content is at write, in the read function body.Just realized the function of algorithm when calling write or read function, its call flow sees also Fig. 6, may further comprise the steps:
601: whether the output Pin that checks this algorithm is empty; If then execution in step 602, process ends then if not;
602: call the write function, will import data and write algorithm box;
603: call the read function, from the sense data of algorithm box, process ends.
Because the preceding output Pin that will determine this algorithm earlier of every grade of algorithm realization (calling) for empty, just removes to call write then, the read function comes implementation algorithm, has so just guaranteed that the valid data of each grade algorithm output can not be capped.
Present embodiment is mapped to pin with the limit in " figure ", when whenever calling a write/read function, the quantity of valid data among the needs control pin (promptly equal an initial value, such as 0), the success of write is called the valid data that can make among the pin and is reduced, and reduction is exactly the write rreturn value.The valid data that can make among the pin are called in the success of read to be increased, and recruitment is exactly the rreturn value of read.Utilize among the pin this value of valid data amount just can judge easily whether pin is empty (promptly whether equaling initial value).Certainly, if the biography ginseng index when calling write or read function is greater than 1 o'clock, and inputing or outputing of box of expression may be a plurality of.At this moment, judge that whether pin is that a circulation process was implemented in sky needed, this all is that those skilled in the art are known, so repeat no more.
Enforcement by technique scheme of the present invention, as can be seen, the algorithm engineering teacher can be under the algorithm layer in the algorithm design system of the present invention, each algorithm that oneself is write out all hangs in the algorithms library under this layer, he only needs to pay close attention to concrete one by one algorithm and realizes, and does not need to consider problem interconnected between the algorithm.When a DSP design engineer (perhaps algorithm engineering teacher) needed to realize checking to the IC hardware capability by several algorithms in this algorithms library, he only needed operation flow process shown in Figure 5 on Puma of the present invention, just can conveniently obtain to verify the result.Algorithm as shown in Figure 7 connects (only expression is wherein a part of), need DSP design engineer when using puma, to carry out concrete operations, each box wherein (being U0 to U19) is an algorithm, replace algorithm wherein, rerun, can not influence in the whole annexation other algorithm box operation.
This shows that algorithm design system provided by the invention and method itself are separated by connection and algorithm with algorithm, make the algorithm design work simplification, and work efficiency improves.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (10)
1. an algorithm design system of realizing the digital signal processor DSP functional verification comprises the algorithm layer entity and the associated layers entity that are separated from each other, wherein:
Described algorithm layer entity is used to design the polyalgorithm entity;
Described associated layers entity, be used for and adopt graph data structure to describe to the interconnecting relation of described algorithm entity, a summit in the described graph data structure is used to shine upon an algorithm entity, and a limit in the described graph data structure is used to shine upon a data circulation road between the described algorithm entity.
2. according to the described system of claim 1, it is characterized in that, described mapping is that the mapping of the entry address realization of mapped described algorithm entity to this algorithm entity passed through to point in described summit, and the mapping of the interface realization of definition to described data flow path passed through on described limit; Write the function that the operation of importing data or reading output data realizes described algorithm entity by visiting described interface.
3. according to the described system of claim 2, it is characterized in that the output of the data of current algorithm entity is controlled at the next stage algorithm entity and carries out after reading valid data in the data output channel of described current algorithm entity.
4. algorithm design method that realizes the digital signal processor DSP functional verification may further comprise the steps:
(a) interconnecting relation with algorithm entity separates with described algorithm entity, is abstracted into associated layers;
(b) interconnecting relation with described associated layers adopts graph data structure to describe, and a summit in the described graph data structure is used to shine upon an algorithm entity; A limit in the described graph data structure is used to shine upon a data circulation road between the described algorithm entity.
5. in accordance with the method for claim 4, it is characterized in that, the described mapping of step (b) is that the mapping of the entry address realization of mapped algorithm entity to this algorithm entity passed through to point in described summit, and the mapping of the interface realization of definition to described data flow path passed through on described limit; Import the function that realizes described algorithm entity that reads of writing of data or output data by visiting described interface.
6. in accordance with the method for claim 5, it is characterized in that the entry address of the described algorithm entity of step (b) is pointed to by the pointer of ancestors' class that all algorithm entities are all inherited; Described interface comprises that the virtual interface of described ancestors' class definition writes function and read function, describedly write function or the described function of reading is realized described algorithm entity by rewriteeing, carry out and to write the input data by calling the described function of writing, carry out and read output data from described algorithm entity by calling the described function of reading to described algorithm entity.
7. in accordance with the method for claim 6, it is characterized in that the valid data length that the described transmission parameter of writing function contains input port sequence number, input-buffer pointer and writes; The valid data length that the described transmission parameter of reading function contains output port sequence number, output buffers pointer and reads.
8. according to each described method of claim 4 to 7, it is characterized in that the realization of the described graph data structure of step (b) further comprises step:
(b1) according to the realization of concrete integrated circuit (IC) chip, design of graphics, and described figure sorted;
(b2) described figure is from first to last traveled through each described summit, the described algorithm entity that it shines upon is called on the summit that meets service condition.
9. in accordance with the method for claim 8, it is characterized in that described service condition is meant that the output data circulation road of current algorithm entity is for empty.
10. in accordance with the method for claim 9, it is characterized in that, judge by described rreturn value and the described rreturn value of reading function of writing function whether described output data circulation road is empty, be that the described rreturn value of writing function makes valid data amount minimizing in the described output data circulation road, the described rreturn value of reading function makes that the increase of valid data amount equals initial value described in the described output data circulation road, and then described output data circulation road is empty.
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| US5737234A (en) * | 1991-10-30 | 1998-04-07 | Xilinx Inc | Method of optimizing resource allocation starting from a high level block diagram |
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| US5737234A (en) * | 1991-10-30 | 1998-04-07 | Xilinx Inc | Method of optimizing resource allocation starting from a high level block diagram |
| JP2000339283A (en) * | 1999-03-23 | 2000-12-08 | Ysd:Kk | Parallel operation processor |
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