CN1012222B - Dot-line dual-diplaying program-controlled time signal clock - Google Patents

Abstract

The present invention is composed of a pointer quartz clock, a time display clock, a 60 system counter, a program counter, a micro power consumption program memory, a power amplifier and other circuits, wherein the time display clock and the pointer quartz clock synchronously indicate time on the same clock face. Control switches arranged on the clocks are used for quickly compiling, modifying and correcting programs at any time, and 1, 440 time points can be set at most within 24 hours; meanwhile, the time display clock visually displays a programming state, and the programs can be safely protected in any event. The present invention has the advantages of small power consumption and low cost, and the present invention is suitable for schools and families to use and can also be used as a simple time sequential control appliance.

Description

Dot-line dual-diplaying program-controlled time signal clock

The present invention is a kind of timing device of control time sequence able to programme, particularly a kind of control device that is used for crystal clock.

Existing lower-cost clock device is with fixing timed sequence or sets in advance a few cover timed sequences, select for the user by selector switch, and can not directly on clock, work out and revise timed sequence (not referring to be provided with the hardening part mode of a small amount of time point) at any time according to different needs.Mainly be that this memory must be furnished with other equipment or computing machine just can be worked out and update routine because use EPROM as the timed sequence memory.Main cause with EPROM storage program without random memory ram is not solve safety guarantor journey to deposit problem.Being entitled as in " novel programmable sequential controller " article of " CYBERSPACE " 1986.7 months reports, adopted RAM as memory under program, it is higher that it finishes circuit cost of protecting Cheng Gongneng, and it adopts is 2114 chips, power consumption is bigger, is unsuitable on the family expenses time signal clock to use.

The purpose of this invention is to provide a kind ofly can directly on clock, write at any time by the user, the low-power consumption clock device of inspection and update routine, improve its antijamming capability, guarantee defence program safely and reliably.

The present invention adopts following proposal to realize.Crystal oscillator in the pointer crystal clock (1) main pulse reference mark when producing 1HZ behind the frequency multiplier circuit shows clock, thereby guarantee point shows clock and the indication of pointer (line) crystal clock synchronization acquisition time.The structure that point shows is to be connected successively by 5 system counters, two-stage 12 system counters, bistable circuit, again by the corresponding decoder driver control dozens of diode displaying time.During mains failure, do not work in the display part that point shows, to reduce power consumption, its counting circuit part is worked on by the reserve battery power supply, i.e. demonstration is " secretly walking " state, by pointer crystal clock instruction time.Behind the civil power incoming call, point shows that recovery shows, point shows and the automatic synchronous operation of pointer crystal clock.Fast slow-motion control circuit shows by 60 system counters while control program counter and point, when the programmable counter upset changes the ram memory element address, the point demonstration also shows programming state synchronously, the user can stir program switch according to a time of demonstration indication intuitively like this, the required time series program of establishment in random memory ram, and can check the timed sequence that modification has been worked out very easily.In order to guarantee that the program among the RAM is not lost behind the mains failure, power to RAM with reserve battery.Facts have proved, this guarantor's program is also not exclusively reliable, at civil power incoming call with have a power failure moment, sometimes having very strong disturbing pulse seals in the ram memory, write among some unit if disturbing pulse is served as data, can make the former program entanglement that deposits in, the result protects procedure failure, set up for this reason have charging battery, the rc-delay circuit of fast discharge performance control ram memory duty, reach the purpose of safe guarantor's program.

The present invention has following accompanying drawing:

Fig. 1 is a clock face synoptic diagram of the present invention.

Fig. 2 is a complete machine schematic diagram of the present invention.

Fig. 3 is the circuit diagram of a kind of embodiment of each several part circuit of the present invention.

Wherein: Fig. 3-the 1st, frequency multiplier circuit.

Fig. 3-2 is 60 system counter circuits.

Fig. 3-3 is 5 system counter circuits.

Fig. 3-the 4th, programmable counter, memory and delay circuit.

Fig. 3-5 is 12 system counter circuits.

Fig. 3-the 6th, bistable flip-flop circuit.

Fig. 3-the 7th, second sudden strain of a muscle device circuit.

Fig. 3-the 8th, fast slow-motion pierce circuit.

Fig. 4 is the relevant oscillogram of the present invention.

Wherein: Fig. 4-the 1st, crystal clock output waveform.

Fig. 4-the 2nd, frequency multiplier output 1HZ pulse.

Fig. 4-the 3rd, ram memory D ₁The end output waveform.

Fig. 4-4 is 60 system counter R end waveforms.

Fig. 4-the 5th, monostable time delay device Q holds waveform.

Fig. 4-the 6th is with the door output waveform.

Below in conjunction with accompanying drawing, giving the correct time with the control electric bell is that example describes the present invention.

(1) is the pointer crystal clock, form the pulse signal (seeing Fig. 4-2) of 1HZ through frequency multiplier (seeing Fig. 3-1) from the double-end pulse signal of quartz clock stepping motor (seeing Fig. 4-1), the CP end (seeing Fig. 3-2) of the received impulse signal 60 system counters (3) of 1HZ, behind these counter 60 frequency divisions, by one minute pulse signal Pm of R end output, the Pm signal is received the CP end of the IN that a shows end and programmable counter (5) simultaneously, on the one hand guarantee point shows clock and pointer crystal clock synchronous instruction time, guarantee point demonstration clock and programmable counter synchronous operation on the other hand.

Point shows by 5 system counters (15), two-stage 12 system counters (13), (14) and trigger flip-flop (12) formation.1 minute pulse signal Pm lights 4 green LED D after decoding drives through 5 system counters (seeing Fig. 3-3) with in it successively ₁-D ₄, export 5 minutes pulse signals then.4 light emitting diodes realize showing in 1 minute dexterously, are in 0 to 5 minute when interval when the time, and these 4 light emitting diodes are represented 1,2,3,4 minute respectively; Be in 5 to 10 minutes when interval when the time, these 4 light emitting diodes are represented 6,7,8,9 minutes respectively.5 fens clocks drive through decoding behind one-level 12 system counters (seeing Fig. 3-5) frequency division again lights 12 light emitting diode D successively ₅-D ₁₆, export 1 hour pulse signal then, D ₅-D ₁₆Show 5,10 ... whole 5 minutes and 5 multiples such as 60 minute.Design only just can show 60 minutes (showing that step pitch is 1 minute) with 16 light emitting diodes like this, can economize 44 light emitting diodes, has reduced cost.Pulse signal was lighted 12 red light emitting diodes D through one-level 12 system counter frequency divisions, decoding after driving again successively in 1 hour ₁₇-D ₂₈, export pulse in 12 hours then, D ₁₇-D ₂₈Show 1,2 respectively ... 12 integral point clocks.Pulse signal removed to trigger trigger flip-flop (seeing Fig. 3-6) in 12 hours, made it light two yellow light-emitting diode D in turn ₂₉-D ₃₀, show the morning and afternoon respectively.Dotted line is two to show clock face as shown in Figure 1, and 30 light emitting diodes are distributed on the pointer quartz clock face in an orderly manner.The point demonstration also can insert by capacitor C ₃, resistance R ₅With triode BG ₁The second sudden strain of a muscle device of forming (16) (seeing Fig. 3-7), the same time point of beating at pointer (line) crystal clock second hand show that the colored points of crystal clock flashes, and traditional pointer are shown show with novel luminous point organically to combine, and it is more attractive in appearance that clock face seems.During mains failure, after sudden strain of a muscle device second (16) obtains power cut signal, make whole light emitting diodes of instruction time stop luminous, each counter power supply that reserve battery E only shows for point, the point demonstration is " secretly walking " state, civil power when incoming call like this, point just show can be automatically and the pointer crystal clock show synchronously.

Programmable counter (5) is the cycle counter (seeing Fig. 3-4) in 1440 steps, realizes circulation in 24 hours round the clock.Programmable counter output terminal Q ₀-Q ₁₀Respectively with the address input end A of random memory ram ₀-A ₁₀Link to each other Q ₀-Q ₁₀Export the element address sign indicating number (all there be corresponding address sign indicating number each minute) of a series of binary signals, the D of RAM as RAM ₁-D ₈End is an input-output line, and this example is only used D ₁The end outer signal, all the other each ends can expand according to need.The read-write WE end of RAM links to each other with program button AN, and when read-write WE was in low level (being that AN presses), RAM was in " writing " state, D ₁High level on the line or low level signal (by the determining positions of K switch) just can write among the RAM units corresponding, and when read-write WE was in high level, RAM was " reading " state, at data line D ₁On present the content of each unit of memory successively, work as D ₁On when being high level, just can drive relay (11) drive electric bell (or music integrated circuit etc.) through power amplifier (10) and give the correct time.

For the ease of programming, be provided with fast slow-motion circuit (4), it is by fast, slow-motion control knob AN ₁, AN ₂Form (seeing Fig. 3-8) with multivibrator, the CP end of 60 system counters is received in its output, programmable counter and point are shown with the frequency faster 3600 times than normal speed realize " F.F. ", realize " slow-motion " with the frequency faster 60 times than normal speed, compensated the deficiency that the pointer crystal clock can not F.F., write for the user provides fast, the means of inspection and update routine, and provide simultaneously very intuitively and show.After programming finishes, show that with fast, slow-motion control knob calibration point clock and pointer crystal clock are synchronous again.

When civil power cuts off the power supply, the anode of diode D is a low level, negative terminal is a high level, diode D is a cut-off state, cut off bigger power amplification circuit (10) and the relay (11) of power consumption, battery E powers to ram memory by R, and simultaneously chip selection signal CS invalid (be " high level) RAM(6116) enters little power consumption and protects program state.Also to other counting circuit power supply that needs work, because these circuit are all selected cmos circuit for use, power consumption is especially little by R for battery E, thus only with No. 2 batteries of 2 joints, can not lose in the continuous 1 year program that has a power failure of civil power yet, but the still synchronous operation of two clocks.In order to guarantee in civil power incoming call and the interference of the moment that has a power failure Rogue program not, with a kind of " avoidance " method, even memory changes the state exchange time that keeps data mode (or in contrast) over to by normal operating conditions and civil power is sent a telegram here or the time of outage staggers, so just can avoid powerful instantaneous interference pulse.It is by resistance R ₃, capacitor C ₁, relay tip J ₁With triode BG ₂Form put soon, the delay circuit (seeing Fig. 3-4) of trickle charge realizes.During the civil power incoming call, stabilized voltage supply (17) is started working R ₃, C ₁The time-lag action chip selection signal CS that makes ram memory after whole circuit powers are stable, become effectively (low level), RAM changes normal operating conditions over to by keeping data mode.During mains failure, the Vdd termination of stabilized voltage supply (17) has the big capacitor C of filtering, and the electric charge on the C is enough to make the complete machine work several seconds, simultaneously in the moment that has a power failure, is connected on the relay coil J dead electricity of power supply bridge rectifier output terminal, normally closed contact J ₁Rapid closing, triode ends at once, make the CS end of RAM provide high level by battery E, RAM changes little power consumption over to by normal operating conditions and keeps data mode, finish the action of electricity down in advance to RAM, after a moment, the electric charge complete obiteration on the capacitor C, the battery-powered work of complete machine.

The input signal of monostable chronotron (8) is taken to Pm by monostable chronotron (8) and the signal conversion circuit formed with door (9) to insert one before power amplifier, and output terminal Q receives 1 end with (9), directly meets the D of RAM with 2 ends of door (9) ₁End.This circuit has two effects: one, separately be transferred to data line D continuously from ram memory ₁On adjacent high level signal.Its two, the output width is 20 seconds a rectangular pulse signal (this width is adjustable as required), determines that according to this time of ringing a bell is 20 seconds at every turn.For instance, if there is the following daily schedule in RAM: 1st, 2,3 minutes, per minute was played bell one time, did not ring a bell in the 4th minute, played bell again one time on the 5th minute, when carrying out this program, and RAMD ₁Pulse waveform on the end for power amplifier (10), only admits that the rising edge of first square wave is effective shown in Fig. 4-3.Two adjacent square wave times apart of cause are less than 1 microsecond, and amplifier load-pull up time is a Millisecond, so relay all has little time action, i.e. sorption always from first square wave to the second square wave up to the 3rd square wave.For this cause, should ring bell three times in original 3 minutes, the result only rings once, has lost twice, and (seeing Fig. 4-6) just can meet the demands after process monostable chronotron (8) (seeing Fig. 4-5) and AND circuit conversion.

Time signal clock involved in the present invention, power consumption simple in structure is little, and cost is low, particularly programming is very convenient, the user needn't possess computer literacy, does not also need to establish in addition special-purpose programming device or computing machine, only need just program can be deposited in the clock by button or the switch dialled on the casing.Point shows in the demonstration time and when making program indicator, also has decoration function and noctilucence demonstration effect.The present invention also can be used for the timing controlled of household electrical appliance etc., or makes the simple and easy time controller of machine.

Claims (6)

1, a kind of dot-line dual-diplaying program-controlled time signal clock, comprise pointer crystal clock (18), signal source (2), 60 system counters (3), programmable counter (5), memory under program RAM (7), power amplifier (10), power circuit (17), delay circuit (6), it is characterized in that: point shows that (18) are to be electrically connected by the decoder driver of 5 system counters (15), two-stage 12 system counters (13), (14) and bistable trigger (12) and correspondence and light emitting diode successively and forms; Point shows can be with 16 diode displaying 60 minutes, and the demonstration step pitch is 1 minute; Fast slow-motion circuit output end links to each other with the input end of 60 system counters, and the output terminal of 60 system counters is connected with the input end of programmable counter with a demonstration simultaneously, with control programming, and by a demonstration programming state; The power-off signal that takes out from power supply bridge rectifier output terminal is connected to delay circuit (6), and control program ram memory safety is protected program; During the civil power outage, the some demonstration is " secretly walking " state.

2, time signal clock according to claim 1 is characterized in that: memory under program RAM is 6116 chips.

3, time signal clock according to claim 1 is characterized in that: also can insert in point shows and dodge device (16) second, flicker second indication is provided.

4, time signal clock according to claim 1 is characterized in that: each counter all adopts the GMDS integrated circuit.

5, time signal clock according to claim 1, it is characterized in that: delay circuit is by resistance R ₃, and capacitor C ₁The relay tip J that is in parallel ₁Be connected to the triode BG that the choosing of RAM sheet is held with output ₂Form.

6, time signal clock according to claim 1 is characterized in that: time signal carries out outputing to power amplifier (10) after the signal transformation through single stabilization delay circuit (8) with door (9).

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