CN101212215A - Switching system capable of reducing noise in output signal - Google Patents
Switching system capable of reducing noise in output signal Download PDFInfo
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- CN101212215A CN101212215A CNA2006101721173A CN200610172117A CN101212215A CN 101212215 A CN101212215 A CN 101212215A CN A2006101721173 A CNA2006101721173 A CN A2006101721173A CN 200610172117 A CN200610172117 A CN 200610172117A CN 101212215 A CN101212215 A CN 101212215A
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- control signal
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Abstract
The invention relates to a switching system which can reduce noise of an output signal. The switching system comprises a first switch and a second switch, wherein, the first switch turns a first signal on according to a first control signal. The second switch turns a second signal on according to a second control signal. When the voltage of the first and second control signals is limited within a voltage interval, the noise generated during switching of the switches can be reduced thereby.
Description
Technical field
The invention relates to a kind of switched system, particularly about a kind of switched system that reduces noise in output signal.
Background technology
Clock feedthrough (clock feedthrough) is that common noise is disturbed in the general circuit; when signal utilizes transistor (metal oxide semiconductor transistor) when switch is made change action; through the phenomenon of regular meeting's generation spike, this phenomenon may cause the erroneous judgement of circuit or the stability decreases of signal.And in the digital signal of high frequency, because switching frequency is higher, so the short-time pulse wave interference is also just big more for the influence of signal.
In addition, in current type digital analog converter (current mode digital to analog converter), owing to utilize a large amount of diverter switches to carry out the change action of current path, therefore, when a large amount of diverter switches was carried out the switching of signal simultaneously, short-time pulse wave interference and frequency feed-in effect just can cause considerable influence to the output of current type digital analog converter.If when the current type digital analog converter is applied to drive circuit in the liquid crystal indicator, then can influence the output quality of picture.
Summary of the invention
One of them is that a kind of switched system is being provided for a purpose of the present invention, and the voltage range operated according to switched system comes the voltage swing (voltage swing) of the control signal of limit switch, to reduce the noise that switch is produced when switching.
For reaching above-mentioned and other purpose, the present invention proposes a kind of switched system, and this switched system comprises first switch and second switch, first switch wherein, and according to the first control signal conducting, first signal, second switch is according to the second control signal conducting secondary signal.Wherein, the voltage of first control signal and second control signal is limited at one first voltage range, to reduce the noise that switch is produced when switching.
In another embodiment of the present invention, above-mentioned switched system comprises current source, and shunting is providing as first signal and secondary signal, and switched system is biased in second voltage range, and first voltage range defines according to second voltage range.
In another embodiment of the present invention, above-mentioned switched system also comprises driver element, in order to receiving the 3rd signal and the 4th signal, and driver element according to the 3rd signal and the 4th signal to produce first control signal and second control signal respectively.Wherein, driver element can operate in first bias voltage or second bias voltage, and wherein first bias voltage less than second bias voltage.
In another embodiment of the present invention, above-mentioned driver element also comprises first drive circuit and second drive circuit.Wherein, first drive circuit is exported first control signal according to the 3rd signal, and second drive circuit is exported second control signal according to the 4th signal.
In another embodiment of the present invention, above-mentioned first drive circuit comprises the 3rd switch and the 4th switch, wherein the 3rd switch and the 4th switch are biased between first voltage and second voltage, and according to the 3rd signal, to determine the voltage quasi position of the 3rd output switching terminal, i.e. the voltage quasi position of first control signal.Second drive circuit comprises the 5th switch and the 6th switch, wherein the 5th electronic switch and the 6th switch are biased between first voltage and second voltage, and according to the 4th signal, with the accurate position of the output voltage that determines the 5th switch, the i.e. voltage quasi position of second control signal.
The voltage range that the present invention works according to switched system limits the voltage swing of control signal.Reduce the noise that switch is produced thus when switching.When diverter switch was carried out the switching of signal, pulse wave interference and frequency feed-in effect were to the influence of output signal in the time of can reducing.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A is the circuit diagram of switched system according to an embodiment of the invention.
Figure 1B is the circuit diagram of switched system according to an embodiment of the invention.
Fig. 2 A is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 2 B is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 3 A is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 3 B is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 4 A is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 4 B is the circuit diagram of switched system according to another embodiment of the present invention.
Fig. 5 is the circuit diagram according to the driver element of Fig. 4 A embodiment.
The primary clustering symbol description
100: switch system around
110: signal circuit, current source
410: driver element
510～530: level regulator circuit
501,502: drive circuit
SG, SG1, SG2: signal
DS1, DS2: digital signal
CS1: first control signal
CS2: second control signal
OUT1: first output
OUT2: second output
Embodiment
Figure 1A is the circuit diagram of switched system according to an embodiment of the invention.The switched system of present embodiment is applicable to the current conversion in the current type digital analog converter.Switched system 100 comprises signal circuit 110, nmos pass transistor N10, N20, and wherein nmos pass transistor N10, N20 are the N transistor npn npn, and signal circuit 110 major functions are for providing signal SG.Nmos pass transistor N10 is coupled between the first output OUT1 and the signal SG, and its control end (grid) is coupled to the first control signal CS1.Nmos pass transistor N20 is coupled between the signal SG and the second output OUT2, and its control end (grid) is coupled to the second control signal CS2.Wherein, the first control signal CS1 and the second control signal CS2 are anti-phase each other, and nmos pass transistor N10, N20 use mainly as switch in the present embodiment, in order to the outgoing route of switching signal SG.The type of signal SG then comprises current signal and voltage signal.
Switched system 100 can be via the outgoing route of the first control signal CS1 and the second control signal CS2 switching signal SG, when the first control signal CS1 enables, signal SG is exported by the first output OUT1, and when the second control signal CS2 enabled, signal SG was exported by the second output OUT2.And in the process of switching, the voltage swing of the first control signal CS1 and the second control signal CS2 is less than the operated voltage range of switched system 100.
In the present embodiment, switched system is coupled between voltage VDD and the voltage VSS, and then the voltage swing of the first control signal CS1 and the second control signal CS2 is promptly between voltage VDD and voltage VSS.In other words, just dwindle the voltage swing of the first control signal CS1 and the second control signal CS2 to reduce the noise that transistor N10, N20 (switch) are produced when switching.Wherein, the source of noise comprises short-time pulse wave interference and frequency feed-in effect, all can influence the signal to noise ratio of output signal.In another embodiment of the present invention,, represent that then its voltage range is that voltage VDD is to ground connection if switched system 100 operates between voltage VDD and the ground connection.
In the present embodiment, the first control signal CS1 and the second control signal CS2 are defined to one first voltage range, and switched system then is biased in one second voltage range, and wherein first voltage range is less than or equal to second voltage range.
The number of switches of switching signal is not limited to present embodiment, in another embodiment of the present invention, switched system also can only be coupled to single switch or be coupled to a plurality of switches simultaneously, as long as the voltage swing of the control signal that limit switch received, can reduce the noise that switch is produced when switching, for example short-time pulse wave interference and frequency feed-in effect.For control signal, its voltage swing must be limited among the operated voltage range of switched system, avoids too high or too low voltage to produce.Control signal only need maintain the voltage quasi position that is enough to conducting and closes diverter switch and get final product.Therefore, control signal can be adjusted the size of its voltage swing according to the different demands of switched system tolerance, operating frequency and the operating voltage interval of leakage current (for example to).The voltage swing of control signal is more little, and short-time pulse wave interference and frequency feed-in effect are just more little to the influence of switched system, and the noise that switch produced is also just more little.
Figure 1B is the circuit diagram of switched system according to an embodiment of the invention.The main difference of Figure 1B and Figure 1A is signal circuit 110, and the signal SG direction that signal circuit 110 is exported is different with Figure 1A.Nmos pass transistor N10, N20 are equally according to the guiding path of the first control signal CS1 and the second control signal CS2 switching signal SG.And the voltage swing of the first control signal CS1 and the second control signal CS2 is equally less than the operated voltage range (voltage VDD is to voltage VSS) of switched system 101.In another embodiment of the present invention, above-mentioned diverter switch is not exceeded with nmos pass transistor N10, N20, and assembly that also can other type realized, for example the PMOS transistor in the P transistor npn npn.
Next, with circuit description technological means of the present invention, Fig. 2 A is the circuit diagram of switched system according to another embodiment of the present invention.Please refer to Figure 1A, wherein, if signal circuit 110 is the circuit (following with current source 110 expressions) of a current source form, then its circuit framework is shown in Fig. 2 A.Switched system 200 comprises nmos pass transistor N10, N20 and current source 110.Current source 110 shuntings are made signal SG1 and signal SG2 to provide.Nmos pass transistor N10, N20 are respectively coupled between signal SG1, SG2 and the voltage VSS, and adjust the outgoing route of signal SG1, SG2 according to the first control signal CS1 and the second control signal CS2.When the first control signal CS1 enabled, signal SG1 was exported by the first output OUT1, and when the second control signal CS2 enabled, signal SG2 was exported by the second output OUT2.In the process of switching, the operated voltage range of the first control signal CS1 and the second control signal CS2 is limited at and is less than or equal to the operated voltage range of switched system 200.
In other embodiment of the present invention, above-mentioned current source 110 can change its design attitude equally, shown in Fig. 2 B.And switch also can replace by the PMOS transistor, shown in Fig. 3 A, 3B, wherein all the other details of operations of Fig. 2 B, Fig. 3 A, 3B circuit all describe in detail in the explanation of above-mentioned Figure 1A～Fig. 2 A, disclose and easily release in conjunction with the present invention at present technique field those of ordinary skill, do not add tired stating at this.
Fig. 4 A is the circuit diagram of switched system according to another embodiment of the present invention, Fig. 4 A and the main different driver elements 410 that are of Fig. 2 A.In Fig. 4 A example, mainly utilize the driver element 410 of an inside that digital signal DS1, DS2 are converted to control signal CS1, CS2.Driver element 410 can operate between voltage VDD and the voltage VSS.Because switched system 400 can change the outgoing route (the first output OUT1 or the second output OUT2) of signal SG1, SG2 according to digital signal DS1, the DS2 in the external world.Therefore, when voltage range that the voltage swing of digital signal DS1, DS2 is worked more than or equal to switched system 400, switched system 400 can utilize driver element 410 digital signal DS1, DS2 to be converted to the first control signal CS1 and the second control signal CS2 with appropriate voltage amplitude of oscillation.In the present embodiment, the voltage swing of the first control signal CS1 and the second control signal CS2 is less than the voltage swing of digital signal DS1, DS2.
In other words, if the logic high potential of digital signal DS1, DS2 equals voltage VDD, its logic low potential equals voltage VSS, then the operated voltage range of the first control signal CS1 and the second control signal CS2 is between voltage VDD and voltage VSS, to reduce the noise that transistor N10, N20 are produced when switching (conducting with close).Therefore, when signal SG1, SG2 export output OUT1 or output OUT2 to, can reduce the noise effect that short-time pulse wave interference and frequency feed-in effect are produced.In addition, driver element 410 also is applicable to the circuit framework of Fig. 2 B～Fig. 3 B, and present embodiment is an example with Fig. 4 B only, and all the other do not add tired stating.
Fig. 5 is the circuit diagram according to the driver element of Fig. 4 A embodiment.Driver element 500 comprises first level regulator circuit 510, second level regulator circuit 520, the 3rd level regulator circuit 530, first drive circuit 501 and second drive circuit 502.Wherein, first drive circuit 501 is exported the first control signal CS1 according to digital signal DS1; Second drive circuit, 502 radical word signal DS2 export the second control signal CS2.Driver element 500 operates between voltage VDD and the voltage VSS, first level regulator circuit 510, second level regulator circuit 520, the 3rd level regulator circuit 530 are then in order to adjust the operation bias voltage of first drive circuit 501 and second drive circuit 502, to limit the output bias of the first control signal CS1 and the second control signal CS2.
First level regulator circuit 510, second level regulator circuit 520, the 3rd level regulator circuit 530 can be respectively by the PMOS transistor or nmos pass transistor is constituted.520 of first driver element 501 and second driver elements are made of the combination of PMOS transistor AND gate nmos pass transistor respectively.
Next, then be the circuit framework details of example explanation driver element with Fig. 5.PMOS transistor P1～P4 and nmos pass transistor N1～N3, wherein PMOS transistor P1～P4 is the P transistor npn npn, and nmos pass transistor N1～N3 is the N transistor npn npn.PMOS transistor P1 is coupled between voltage VDD and the PMOS transistor P2.The shared node of PMOS transistor P1 and PMOS transistor P2 is coupled to the grid of PMOS transistor P1, to form first level regulator circuit 510.Nmos pass transistor N1 is coupled between the other end and nmos pass transistor N2 of PMOS transistor P2, and the shared node of nmos pass transistor N1 and nmos pass transistor N2 is coupled to the grid of nmos pass transistor N2.PMOS transistor P2 and nmos pass transistor N1 then form first drive circuit 501.
PMOS transistor P3 is coupled between voltage VDD and the PMOS transistor P4 to form second level regulator circuit 520, and the shared node of PMOS transistor P3 and PMOS transistor P4 is coupled to the grid of PMOS transistor P3.Nmos pass transistor N3 is coupled between the other end and nmos pass transistor N2 of PMOS transistor P4, and the shared node of nmos pass transistor N3 and nmos pass transistor N2 is coupled to the grid of nmos pass transistor N2.And the other end of nmos pass transistor N2 is coupled to voltage VSS.PMOS transistor P4 and nmos pass transistor N3 then form second drive circuit 502, and nmos pass transistor 530 then forms the 3rd level regulator circuit 530.
Wherein, the grid of PMOS transistor P2 and nmos pass transistor N1 is coupled to digital signal DS1, and the grid of PMOS transistor P4 and nmos pass transistor N3 is coupled to digital signal DS2.And the shared node of PMOS transistor P2 and nmos pass transistor N1 is exported the first control signal CS1, PMOS transistor P4 and nmos pass transistor N3 shared node export the second control signal CS2.Since in the present embodiment, the logic current potential that digital signal DS1 and DS2 are anti-phase each other, and this is because switched system 400 usually only can be by output OUT1, OUT2 one of them output signal SG1 or SG2.The first control signal CS1, CS2 are respectively the inversion signal of digital signal DS1, DS2.
In the present embodiment, if the logic high potential of digital signal DS1, DS2 equals voltage VDD, its logic low potential equals voltage VSS.Then the logic high potential of the first control signal CS1 deducts the threshold voltage of PMOS transistor P1 less than voltage VDD, and its logic low-voltage equals the threshold voltage that voltage VSS adds nmos pass transistor N2.In addition, the logic high potential of the second control signal CS2 equals the threshold voltage that voltage VDD deducts PMOS transistor P3, and its logic low-voltage equals the threshold voltage that voltage VSS adds nmos pass transistor N2.In other words, the first control signal CS1 and the second control signal CS2 correspond respectively to the logic current potential of digital signal DS1, DS2, but its voltage swing is less than the voltage swing of digital signal DS1, DS2.
The present invention comes control its switch with the control signal of the small voltage amplitude of oscillation, to reduce the noise that switch is produced when switching, reduces the influence to the output signal of switched system of short-time pulse wave interference and frequency feed-in effect.In addition, driver element can be with under switched system operates in identical voltage, and is the control signal with small voltage amplitude of oscillation with digital signal transition, reduces the spike phenomenon of its output signal, uses the design complexities that reduces switched system.
Though as above disclosed preferred embodiment of the present invention; yet it is not to be used for limiting the present invention; any those skilled in the art should change and change it, so protection scope of the present invention should be defined by the claims without departing from the spirit and scope of the present invention.
Claims (13)
1. switched system comprises:
One first switch is according to one first control signal conducting, one first signal; And
One second switch is according to one second control signal conducting, one secondary signal;
Wherein, the voltage of this first control signal and this second control signal is limited at one first voltage range, to reduce the noise that these switches are produced when switching.
2. this switched system as claimed in claim 1 also comprises:
One current source, shunting is to provide as this first signal and this secondary signal.
3. this switched system as claimed in claim 1, wherein this switched system is biased in one second voltage range, and this first voltage range defines according to this second voltage range.
4. this switched system as claimed in claim 3, wherein this first voltage range is equal to or less than this second voltage range.
5. this switched system as claimed in claim 1 also comprises:
One driver element, receive one the 3rd signal and one the 4th signal, and to produce this first control signal and this second control signal respectively, this driver element is biased to and equals this first voltage range this driver element according to the 3rd signal and the 4th signal.
6. this switched system as claimed in claim 5, wherein this driver element also comprises:
One first drive circuit is according to the 3rd signal, to export this first control signal; And
One second drive circuit is according to the 4th signal, to export this second control signal.
7. switched system as claimed in claim 6, wherein this first drive circuit comprises:
One the 3rd switch;
One the 4th switch, wherein the 3rd switch and the 4th switch are biased between one first voltage and one second voltage, and according to the 3rd signal, to determine the voltage quasi position of the 3rd output switching terminal, i.e. the voltage quasi position of this first control signal;
This second drive circuit comprises:
One the 5th switch; And
One the 6th switch, wherein the 5th switch and the 6th switch are biased between this first voltage and this second voltage, and according to the 4th signal, with the accurate position of the output voltage that determines the 5th switch, the i.e. voltage quasi position of second control signal.
8. switched system as claimed in claim 7, wherein this driver element also comprises:
One first level regulator circuit places on the bias voltage path of this first voltage and the 3rd switch, and in order to the accurate position of the input voltage of adjusting the 3rd switch;
One second level regulator circuit places on the bias voltage path of this first voltage and the 5th switch, and in order to the accurate position of the input voltage of adjusting the 5th switch; And
One the 3rd level regulator circuit places on the bias voltage path of this second voltage and the 4th, the 6th switch, and in order to the accurate position of the output voltage of adjusting the 4th, the 6th switch.
9. switched system as claimed in claim 8, wherein this first, this second level regulator circuit is a P transistor npn npn, and the grid and the drain electrode of this P transistor npn npn are coupled to same point, the 3rd level regulator circuit is a N transistor npn npn, and the grid of this N transistor npn npn and drain electrode are coupled to same point.
10. switched system as claimed in claim 1, wherein this first switch and this second switch are all the N transistor npn npn, or this first switch and this second switch are all the P transistor npn npn.
11. switched system as claimed in claim 7, wherein the 3rd and the 5th switch is the P transistor npn npn, and the 4th and the 6th is the N transistor npn npn.
12. switched system as claimed in claim 1, wherein this switched system is applicable to the current conversion in the current type digital analog converter.
13. switched system as claimed in claim 1, wherein this first control signal and this second control signal inversion signal each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101721173A CN101212215A (en) | 2006-12-27 | 2006-12-27 | Switching system capable of reducing noise in output signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101721173A CN101212215A (en) | 2006-12-27 | 2006-12-27 | Switching system capable of reducing noise in output signal |
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| Publication Number | Publication Date |
|---|---|
| CN101212215A true CN101212215A (en) | 2008-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101721173A Pending CN101212215A (en) | 2006-12-27 | 2006-12-27 | Switching system capable of reducing noise in output signal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115033044A (en) * | 2021-03-05 | 2022-09-09 | 龙芯中科技术股份有限公司 | Current source module, voltage stabilizing method, digital-to-analog converter and equipment |
| CN115622549A (en) * | 2022-12-19 | 2023-01-17 | 晟矽微电子(南京)有限公司 | Switching circuit, digital-to-analog converter, chip and electronic equipment |
-
2006
- 2006-12-27 CN CNA2006101721173A patent/CN101212215A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115033044A (en) * | 2021-03-05 | 2022-09-09 | 龙芯中科技术股份有限公司 | Current source module, voltage stabilizing method, digital-to-analog converter and equipment |
| CN115033044B (en) * | 2021-03-05 | 2024-03-15 | 龙芯中科技术股份有限公司 | Current source module, voltage stabilizing method, digital-to-analog converter and equipment |
| CN115622549A (en) * | 2022-12-19 | 2023-01-17 | 晟矽微电子(南京)有限公司 | Switching circuit, digital-to-analog converter, chip and electronic equipment |
| CN115622549B (en) * | 2022-12-19 | 2023-02-28 | 晟矽微电子(南京)有限公司 | Switching circuit, digital-to-analog converter, chip and electronic equipment |
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Open date: 20080702 |