CN101206909A

CN101206909A - Method for generating memory time pulse signal and gating time pulse generating circuit

Info

Publication number: CN101206909A
Application number: CN 200710194874
Authority: CN
Inventors: 张棋
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2007-12-13
Filing date: 2007-12-13
Publication date: 2008-06-25
Anticipated expiration: 2027-12-13
Also published as: CN100578661C

Abstract

The invention relates to a time pulse signal generating method of a memorizer, and a gated time pulse generating circuit. According to a reference time pulse signal and a time pulse intelligent signal, a gated memorizer time pulse signal can be produced; wherein, when the time pulse intelligent signal is intelligent, and the frequency of the gated memorizer time pulse signal keeps consistent with the frequency of the reference time pulse signal; when the time pulse intelligent signal is non-intelligent, and the frequency of the gated memorizer time pulse signal is decreased. When the time pulse signal of a system memorizer is updated, the time pulse signal generating method and the gated time pulse generating circuit of the invention ensure that the energy consumption can be reduced ulteriorly, and still the data access accuracy can be maintained.

Description

Storer time pulse signal forming method and gate clock generating circuit

Technical field

The present invention is a kind of storer time pulse signal forming method and interlock circuit, refers to storer time pulse signal forming method and interlock circuit when system storage carries out the clock signal renewal especially.

Background technology

The motherboard of the general computer system of now being sold on the market, its basic comprising mainly is by CPU (central processing unit) (Central Processing Unit, abbreviation CPU), chipset (Chipset) and some peripheral circuits are formed, its CPU (central processing unit) is the core place of computer system, handles and control the running between each element in the total system in order to the logical operation of carrying out in the system.Chipset then is the running of being responsible for linking between CPU (central processing unit) and other peripherals, the combination of its chipset has many different modes, be with north bridge (North Bridge at present, being called for short NB) chip and south bridge (South Bridge is called for short SB) the chip chipset that forms of arranging in pairs or groups is the more common practice.

And also have an important element on the motherboard of computer system is that system storage (is generally dynamic RAM (Dynamic Random AccessMemory, be called for short DRAM)), in general, system storage normally with chipset in north bridge chips directly be connected as signal.And according to the difference of read-write mode, common type of memory includes at present: synchro system storer (SynchronousDRAM, abbreviation SDRAM), synchronous double data communication system storer (DoubleData Rate SDRAM is called for short DDR SDRAM) or the like.

Seeing also Fig. 1 a, is the configuration schematic diagram of a Memory Controller 10 (configurable on a north bridge chips (not shown)) and a system storage 11; Because any signal in computer system or instruction is when being read or carry out, except that need via above-mentioned CPU (central processing unit) handle with judge, also need to utilize the storage space of system storage 11 inside to be used as the temporary disposal of data.Hereat, for data access (access) process that system storage 11 is carried out, no matter being reading (read), writing (write) or the power supply of storer required work within a certain period set time upgrades (refresh) action etc. of data, all is to be responsible for controls by Memory Controller 10.

Shown in this Fig. 1 a, with regard to present technology, system storage 11 itself does not have clock pulse generator, offers system storage 11 but produce clock pulse (Clock) by Memory Controller 10, makes all access actions to finish synchronously and in an orderly manner according to the indication of clock signal.For instance, under normal operation, Memory Controller 10 can produce a storer clock signal DCLK (DRAM Clock) to system storage 11 with reference to clock signal CLK (not being shown in this figure) according to one, and wherein storer clock signal DCLK is with the same with reference to clock signal CLK phase place unanimity and frequency.Then, system storage 11 utilizes a delay-locked loop (Delay-Locked Loop, be called for short DLL, be not shown in this figure) the storer clock signal DCLK that is received is carried out the adjustment that signal Synchronization is handled, and then produce a data triggering signals DQS (DataStrobe).Data triggering signals DQS can follow data to be back to together on the Memory Controller 10, and the north bridge chips (not shown) just can be come the data of access system storer 11 according to the triggering of data triggering signals DQS.

So-called synchronous adjustment is that the storer clock signal DCLK that will be imported carries out a detecting and a calibration process that postpones input and/or output by delay-locked loop, make that the phase place of data triggering signals DQS is consistent with the phase place of storer clock signal DCLK, just do not have phase differential (in phase).In addition, delay-locked loop also can carry out the compensation (compensate) that clock signal is adjusted constantly in the data access process, can cause the phase effect that the possible signal of data trigger pip DQS is departed from (skew) to avoid system because of the situation of rising of the temperature of inner related elements or change in voltage under operating state.

See also Fig. 1 b, the signal sequence synoptic diagram when carrying out data access for 10 pairs of system storages of Memory Controller 11; As shown in this figure, wherein storer clock signal DCLK must export system storage 11 to from Memory Controller 10 constantly, promptly keep its so-called clock pulse generation rate (toggle rate), to keep the correct corresponding output of follow-up data triggering signals DQS.In Fig. 1 b, when one read signal READ and a write signal WRITE and is high level (High), then expression had the access procedure of data to produce (read or write).Memory Controller 10 also can send a clock pulse enable signal CKE (Clock Enable) and came startup that system storage 11 is carried out data read or writes this moment.Hereat, when the access procedure of data produced, clock pulse enable signal CKE just was in high level (High), and when not having the generation of data access process, clock pulse enable signal CKE can be pulled to low level (Low).

Yet, when system storage 11 produces in the process that does not have data access, or system storage 11 is when entering power supply and upgrade in the process of (refresh), what storer clock signal DCLK still can continue exports system storage 11 to from Memory Controller 10, so will make computer system produce unnecessary power consumption.If but when system storage 11 when not having data access or entering power supply to upgrade, the generation of just turning off storer clock signal DCLK, then when access system storer 11 again, just need readjust the phase place of storer clock signal DCLK and data triggering signals DQS, access system storer 11 again just after so must wait for a period of time so will make the deterioration of efficiency of data access.

Summary of the invention

The invention provides a kind of storer time pulse signal forming method and circuit thereof, make system storage when carrying out the renewal of clock signal, can further reduce power consumption, and still can guarantee the correctness of data access.

The invention provides a kind of storer time pulse signal forming method, comprising: produce a gate storer clock signal with reference to a clock signal and a clock pulse enable signal according to one; Wherein when the clock pulse enable signal is activation, the frequency that makes gate storer clock signal with keep identically with reference to the frequency of clock signal, and when the clock pulse enable signal is disabled, reduce the frequency of gate storer clock signal.

The invention provides a kind of gate clock generating circuit, in order to produce a gate storer clock signal.Gate clock generating circuit of the present invention comprises: a clock generating circuit produces a delay clock pulse enable signal according to one with reference to a clock signal and a clock pulse enable signal; One delay circuit includes a plurality of latch circuits and connects mutually, produces clock pulse cycle selection signal according to anti-phase reference clock signal and delay clock pulse enable signal; And a gating circuit, be connected to clock generating circuit and delay circuit, according to the reference clock signal, postpone the clock pulse enable signal and select signal generation gate storer clock signal with the clock pulse cycle.

The present invention provides a kind of storer time pulse signal forming method in addition, in order to produce a gate storer clock signal.Another storer time pulse signal forming method of the present invention comprises: produce a delay clock pulse enable signal according to one with reference to a clock signal and a clock pulse enable signal; Produce clock pulse cycle selection signal according to anti-phase reference clock signal and delay clock pulse enable signal; And according to the reference clock signal, postpone the clock pulse enable signal and produce this gate storer clock signal with clock pulse cycle selection signal.

Storer time pulse signal forming method of the present invention and gate clock generating circuit make system storage when carrying out the renewal of clock signal, can further reduce power consumption, and still can guarantee the correctness of data access.

Description of drawings

Fig. 1 a is the configuration schematic diagram of Memory Controller 10 and system storage 11.

Fig. 1 b, the signal sequence synoptic diagram when carrying out data access for 10 pairs of system storages of Memory Controller 11.

Fig. 2 a is in embodiments of the present invention the Memory Controller 201 and the configuration schematic diagram of system storage 21.

Fig. 2 b is the sequential synoptic diagram of gate storer clock signal of the present invention.

Fig. 3 is the synoptic diagram of gate clock generating circuit 300 of the present invention.

Fig. 4 a is the synoptic diagram of the clock generating circuit 310 of gate clock generating circuit 300 of the present invention.

Fig. 4 b is the synoptic diagram of the delay circuit 320 of gate clock generating circuit 300 of the present invention.

Fig. 4 c is the synoptic diagram of the gating circuit 330 of gate clock generating circuit 300 of the present invention.

Fig. 5 is the signal timing diagram of corresponding embodiment of the invention gate clock generating circuit 300.

Embodiment

The present invention must can get a more deep understanding by following graphic and explanation.

See also Fig. 2 a, be in embodiments of the present invention the north bridge chips 20 and the configuration schematic diagram of a system storage 21.In the present invention, the running of the major function of north bridge chips 20 and system storage 21 is identical with the explanation of Fig. 1 a.In this embodiment, by changing the function of control signal or steering order, improve the problem of computer system consumption.

North bridge chips 20 among Fig. 2 a can send a storer clock signal DCLK to system storage 21 under normal operation, and the delay-locked loop of system storage 21 (not being shown in this figure) can carry out the adjustment that signal Synchronization is handled according to the storer clock signal DCLK that receives, and then produce a data triggering signals DQS and be back to north bridge chips 20, make north bridge chips 20 to carry out data access to system storage 21 according to data triggering signals DQS.In the present invention, north bridge chips 20 includes a Memory Controller 201, in order to the signal and the instruction of sending data access.

Please consult Fig. 2 b simultaneously, be the signal sequence synoptic diagram of memory data access of the present invention.As shown in the figure, as reading command or write instruction when sending, Memory Controller 201 can send a clock pulse enable signal CKE of high level in order to start the data access to system storage 21.When not having data access to take place, 201 of Memory Controllers make clock pulse enable signal CKE be pulled to low level by high level.

In this example, we represent above-mentioned storer clock signal DCLK with one with reference to clock signal CLK, and so both contents are identical.As mentioned above, though system storage 21 whether by access, the DCLK signal continues to export (the CLK signal shown in Fig. 2 b also continues to produce) on the system storage 21 to from north bridge chips 20, makes the DQS signal to export normally.That is, even system storage 21 not by access or when entering power supply and upgrading (refresh) state, the generation that the CLK signal still will continue clock pulse periodic signal one by one will make computer system produce unnecessary power consumption thus.

In the present invention, in order to reach the loss that reduces power supply, therefore utilize a gate storer clock signal DCLK_G to replace the storer clock signal that original DCLK signal is used as system storage 21.When system storage 21 normally by access the time, DCLK_G signal and the original the same clock pulse periodic signal that can constantly produce of DCLK signal are to system storage 21.But when system storage 21 not by access or when entering power supply and upgrading (refresh) state, the DCLK_G signal can produce the clock pulse periodic signal of slow frequency to system storage 21.The phase place of the phase place of the clock pulse periodic signal that produced of DCLK_G signal of this moment during with operate as normal is identical, but the frequency of frequency when more normally working is slow.Because phase place is consistent,, and can not make system storage 21 produce misoperation so this moment, delay locked loop still can produce the DQS signal normally.

This Fig. 2 b is depicted as the gate storer clock signal DCLK_G synoptic diagram of the embodiment of the invention.

Shown in Fig. 2 b, suppose between time T 1～T5, system storage 21 is by access, and clock pulse enable signal CKE is the state (the CKE signal is a high level) of activation, and this moment, the DCLK_G signal produced phase place and all consistent continuous clock pulse periodic signal CG1～CG5 of frequency according to reference clock signal CLK.And system storage 21 just can produce data triggering signals DQS (not being shown among the figure) according to the DCLK_G signal, make that system storage 21 can be correct by access.

Suppose between time T 6～T10 system storage 21 for not by access or the state for upgrading, clock pulse enable signal CKE changes into the state for disabled (that is change into low level by high level) when time point T6.This moment, DCLK_G produced the clock pulse periodic signal with slower frequency.In an embodiment of the present invention, the DCLK_G signal frequency of supposing this moment is 1/5 of an operate as normal lower frequency, that is between T6～T10, have five clock pulse periodic signal C6～C10 to produce with reference to clock signal CLK, but the DCLK_G signal has only a clock pulse periodic signal CG6 to produce.It is synchronous that we make the clock pulse periodic signal C7 of clock pulse periodic signal CG6 that this moment, the DCLK_G signal produced and CLK signal in the present embodiment, that is the clock pulse periodic signal CG6 of DCLK_G can be just along rising to high level when time point T7, negative edge drops to low level when time point T7 ', so with so that phase place is kept unanimity.

Then, shown in Fig. 2 b, system storage 21 returns to by the state of access after time point T11, and clock pulse enable signal CKE is enabled to high level at time point T11, and the DCLK_G signal produces phase place and all consistent continuous clock pulse periodic signal of frequency according to reference clock signal CLK.

The foregoing description is worked as system storage 21 not by between the time T 6～T10 of access, the 2nd the clock pulse periodic signal (that is C7) of the CLK signal of section in the time is synchronous therewith to suppose the DCLK_G signal, but in fact in the present invention, the clock pulse periodic signal CG6 of DCLK_G signal generation can be synchronous with this section any one clock pulse periodic signal that the CLK signal produces in the time.That is CG6 also can be synchronous with any of C6, C7, C8, C9 or C10, as long as the frequency that satisfies the DCLK_G signal than the frequency of CLK signal slowly.

Fig. 3 is that the present invention's one gate clock generating circuit 300 is in order to produce the gate storer clock signal DCLK_G shown in Fig. 2 b.

Gate clock generating circuit 300 of the present invention comprises: a clock generating circuit 310, can receive with reference to clock signal CLK and clock pulse enable signal CKE, and postpone clock pulse enable signal CKE_L in order to produce one; One delay circuit 320 includes a plurality of latch circuits, in order to according to postponing clock pulse enable signal CKE_L and anti-phase reference clock signal CLK, produces clock pulse cycle selection signal CLK_SEL; And a gating circuit 330, in order to select according to the clock pulse cycle signal CLK_SEL, with reference to clock signal CLK with postpone clock pulse enable signal CKE_L and produce a gate storer clock signal DCLK_G.

Fig. 4 a is depicted as the enforcement synoptic diagram of the clock generating circuit 310 of gate clock generating circuit 300 of the present invention.Clock generating circuit 310 includes a phase inverter 401 and a D flip-flop 402.Wherein D flip-flop 402 receives anti-phase clock pulse enable signal CKE and exports one according to the triggering of reference clock signal CLK (suppose in the present invention D flip-flop 402 be just along the trigger that triggers) and postpones clock pulse enable signal CKE_L.

Fig. 4 b is depicted as the enforcement synoptic diagram of the delay circuit 320 of gate clock generating circuit 300 of the present invention.In the present embodiment, suppose system storage 21 not by the state of access under when being the disabled state (that is CKE signal), the frequency of DCLK_G signal is reduced to 1/5 under the operate as normal, and (that is this moment is whenever the CLK signal produces 5 clock pulse periodic signals, the DCLK_G signal only produces 1 clock pulse periodic signal), and the 2nd clock pulse periodic signal phase-locking of the clock pulse periodic signal that this moment, the DCLK_G signal was produced and CLK signal this moment.Therefore shown in Fig. 4 b, the delay circuit 320 of present embodiment includes 5 latch circuits 321～325, and the output LO2 of the 2nd latch circuit 322 is become clock pulse cycle selection signal CLK_SEL.

Shown in Fig. 4 b, each latch circuit 321～325 all includes a multiplexer 411～415 and a D flip-flop 421～425, supposes that wherein D flip-flop 421～425 is all just along the trigger that triggers.D flip-flop 421～425 is exported the 0 or 1 output LO1～LO5 that is used as latch circuit 321～325 in regular turn according to the triggering of anti-phase reference clock signal CLK.As mentioned above, because the clock pulse periodic signal that the DCLK_G signal produces must be synchronous with the 2nd the clock pulse periodic signal that reference clock signal CLK produces, therefore the output LO2 of the 2nd D flip-flop 422 becomes clock pulse cycle selection signal CLK_SEL in the present embodiment.In like manner, the clock pulse periodic signal that makes the generation of DCLK_G signal is if desired selected signal CLK_SEL with synchronous with reference to the 3rd the clock pulse periodic signal of clock signal CLK as long as the output LO3 of the 3rd D flip-flop 423 becomes the clock pulse cycle.

Fig. 4 c is depicted as the enforcement synoptic diagram of the gating circuit 330 of gate clock generating circuit 300 of the present invention.In the present embodiment, gating circuit 330 include one first with

door

440,1 second and

door

450,1 first Sheffer stroke gate 460, one second Sheffer stroke gate 470, one the 3rd Sheffer stroke gate 480 and a phase inverter 490.

Shown in Fig. 4 c, first with door 440 the clock pulse cycle is selected signal CLK_SEI and with reference to clock signal CLK through output one first signal CLK_S1 after the logical operation.Second maintains high level (being logical value " 1 ") with a door input end of 450, and another input end receives with reference to clock signal CLK, via second with door 450 logical operations after output one secondary signal CLK_S2.The delay clock pulse enable signal CKE_L that first Sheffer stroke gate 460 is produced the first signal CLK_S1 and clock generating circuit 310 is through output one the 3rd signal CLK_S3 after the logical operation.Second Sheffer stroke gate 470 with secondary signal CLK_S2 and anti-phase delay clock pulse enable signal CKE_L (utilizing phase inverter 490 anti-phase this delay clock pulse enable signal CKE_L) through output one the 4th signal CLK_S4 after the logical operation.At last, the 3rd Sheffer stroke gate 480 becomes gate storer clock signal DCLK_G with the 3rd signal CLK_S3 and the 4th signal CLK_S4 through output after the logical operation.

Figure 5 shows that signal timing diagram according to Fig. 4 a～Fig. 4 c.As shown in Figure 5, the output LO1～LO5 of 5 latch circuits 321～325 is in regular turn:

[LO1，LO2，LO3，LO4，LO5]＝[1，0，0，0，0]；

[LO1，LO2，LO3，LO4，LO5]＝[0，1，0，0，0]；

[LO1，LO2，LO3，LO4，LO5]＝[0，0，1，0，0]；

[LO1，LO2，LO3，LO4，LO5]＝[0，0，0，1，0]；

[LO1，LO2，LO3，LO4，LO5]＝[0，0，0，0，1]；

Because it is output LO2 with reference to the 2nd latch circuit 322 that clock pulse cycle of present embodiment is selected signal CLK_SEL, the oscillogram that therefore can obtain CLK_SEL as shown in Figure 5.

With reference to figure 5, the enforcement of Fig. 4 a～Fig. 4 c signal can obtain required gate storer clock signal DCLK_G according to the present invention.

In addition, do not consider the late effect of logic gate in the present embodiment.If the delay cell of considering adding different time delays that late effect is then can be in gate clock generating circuit 300 suitable is in order to proofread and correct the late effect that produces because of logic gate.

In the above-described embodiments, gate clock generating circuit 300 utilizes the latch circuit 321～325 of 5 series connection to constitute this delay circuit 320, makes that the frequency of DCLK_G signal becomes 1/5th of normal working frequency when system storage during not by access; Be with, the number that can adjust series circuit is with the generation rate of control clock pulse periodic signal, in order to reduce the power consumption of computer system effectively.

In addition, according to present technology, in the neutral gear stage of data access, clock pulse enable signal CKE transfers to the low level time and must not be less than 3 clock pulse periodic signals, is must at least 3 with, the latch circuit of being connected under the notion of present embodiment.And the gate clock generating circuit 300 that present embodiment proposed only is a kind of device of implementing that reaches the inventive method, and corresponding signal sequence synoptic diagram describes with the simplest state.Yet clock pulse enable signal CKE is in the time of low level state may be longer, so also can utilizing the latch circuit of other numbers to connect, we constitute this kind gate clock generating circuit, or utilize other minimizings that can reach clock pulse periodic signal generation rate or slack-off element also can, in order to reach the effect of the inventive method.

The present invention can solve in the background technology between north bridge chips and the system storage in order to keep the renewal of storer clock signal, and in the stop phase of data access process still can cause the power consumption situation of computer system.In addition, embodiments of the invention describe when not having the data access process to take place, yet, general clock pulse enable signal is in low level except the no datat access procedure takes place, when system storage upgrades (refresh) process at the power supply that carries out itself, also be a kind of state that can reduce its clock pulse generation rate, so, when system storage is carrying out power supply own when upgrading, also can utilize method of the present invention reach province can effect.

Hereat, we have successfully solved the mentioned problem of background technology, and finish the fundamental purpose of the present invention's development.

The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.

Being simply described as follows of symbol in the accompanying drawing:

Memory Controller: 10,201

North bridge chips: 20

System storage: 11,21

Gate clock generating circuit: 300

Clock generating circuit: 310

Delay circuit: 320

Gating circuit: 330

Latch circuit: 321～325

D flip-flop: 402,421～425

Multiplexer: 411～415

With door: 440,450

Sheffer stroke gate: 460～480

Phase inverter: 401,490.

Claims

1. a storer time pulse signal forming method is characterized in that, this storer time pulse signal forming method comprises:

Produce a gate storer clock signal according to one with reference to a clock signal and a clock pulse enable signal;

Wherein when this clock pulse enable signal is activation, it is identical that the frequency that makes this gate storer clock signal and this frequency with reference to clock signal are kept, and when this clock pulse enable signal is disabled, reduce the frequency of this gate storer clock signal.

2. storer time pulse signal forming method according to claim 1 is characterized in that, when this clock pulse enable signal is disabled, makes the phase place of this gate storer clock signal keep identical with this phase place with reference to clock signal.

3. storer time pulse signal forming method according to claim 1 is characterized in that, this gate storer clock signal is in order to control a system storage.

4. storer time pulse signal forming method according to claim 3, it is characterized in that, when this clock pulse enable signal is activation, this system storage is normal access status, and when this clock pulse enable signal was disabled, then this system storage was not for by access status or power supply update mode.

5. a gate clock generating circuit is characterized in that, in order to produce a gate storer clock signal, this gate clock generating circuit comprises:

One clock generating circuit is in order to produce a delay clock pulse enable signal according to one with reference to a clock signal and a clock pulse enable signal;

One delay circuit is connected to this clock generating circuit, includes a plurality of latch circuits and connects mutually, in order to select signal according to anti-phase this with reference to clock signal and this delay clock pulse enable signal clock pulse cycle that produces; And

One gating circuit is connected to this clock generating circuit and this delay circuit, in order to select signal to produce this gate storer clock signal according to this with reference to clock signal, this delay clock pulse enable signal and this clock pulse cycle.

6. gate clock generating circuit according to claim 5 is characterized in that, when this clock pulse enable signal was activation, this gate storer clock signal was identical and phase place is identical with reference to the clock signal frequency with this.

7. gate clock generating circuit according to claim 5, it is characterized in that, when this clock pulse enable signal was disabled, this gate storer clock signal was identical with this phase place with reference to clock signal, and the frequency of this gate storer clock signal is slow than this frequency with reference to clock signal.

8. gate clock generating circuit according to claim 5, it is characterized in that, when this clock pulse enable signal is disabled, during in this gate storer clock signal the clock pulse periodic signal can with this phase-locking with reference to any the clock pulse periodic signal in the clock signal.

9. gate clock generating circuit according to claim 5 is characterized in that, this clock generating circuit comprises:

One phase inverter, input end receive this clock pulse enable signal; And

One D flip-flop;

Wherein this D flip-flop receives this anti-phase clock pulse enable signal via this phase inverter, and according to this with reference to the triggering of clock signal in order to export this delay clock pulse enable signal.

10. gate clock generating circuit according to claim 5 is characterized in that, the number of described latch circuit series connection and the frequency dependence of this gate storer clock signal.

11. gate clock generating circuit according to claim 5 is characterized in that, each this latch circuit comprises:

One multiplexer; And

One D flip-flop is connected to this multiplexer, in order to export 0 or 1 output signal in regular turn with reference to clock signal according to anti-phase this;

Wherein, select one of them of output signal of described latch circuit to become this clock pulse cycle and select signal.

12. gate clock generating circuit according to claim 5 is characterized in that, this gating circuit comprises:

One first with door, with this in clock pulse cycle select signal with this with reference to clock signal through exporting one first signal after the logical operation;

One second with door, export a secondary signal after should passing through logical operation with reference to clock signal and a logical value " 1 ";

One first Sheffer stroke gate, be connected to this first with door, will this first signal postpone the clock pulse enable signal through exporting one the 3rd signal after the logical operation with this;

One second Sheffer stroke gate, be connected to this second with door, this secondary signal and anti-phase this are postponed clock pulse enable signal through exporting one the 4th signal after logical operation; And

One the 3rd Sheffer stroke gate is connected to this first Sheffer stroke gate and this second Sheffer stroke gate, and the 3rd signal and the 4th signal are become this gate storer clock signal through output after the logical operation.

13. gate clock generating circuit according to claim 12 is characterized in that this gating circuit more comprises a phase inverter, should postpone the clock pulse enable signal in order to anti-phase.

14. a storer time pulse signal forming method is characterized in that, in order to produce a gate storer clock signal, this storer time pulse signal forming method comprises:

Produce a delay clock pulse enable signal according to one with reference to a clock signal and a clock pulse enable signal;

Select signal according to anti-phase this with reference to clock signal and this delay clock pulse enable signal clock pulse cycle that produces; And

Select signal to produce this gate storer clock signal according to this with reference to clock signal, this delay clock pulse enable signal and this clock pulse cycle.

15. storer time pulse signal forming method according to claim 14 is characterized in that, more comprises: when this clock pulse enable signal is activation, make the frequency of this gate storer clock signal identical with this frequency with reference to clock signal.

16. storer time pulse signal forming method according to claim 14, it is characterized in that, more comprise: when this clock pulse enable signal is disabled, reduce the frequency of this gate storer clock signal, and make the phase place of this gate storer clock signal keep identical with this phase place with reference to clock signal.

17. storer time pulse signal forming method according to claim 16 is characterized in that, the clock pulse periodic signal in this gate storer clock signal can with this phase-locking with reference to any the clock pulse periodic signal in the clock signal.

18. storer time pulse signal forming method according to claim 17, it is characterized in that, more comprise: produce a plurality of output signals according to anti-phase this with reference to clock signal and this delay clock pulse enable signal, and select one of them output signal to become this clock pulse cycle and select signal.