CN101206356B - Liquid crystal display panel - Google Patents
Liquid crystal display panel Download PDFInfo
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- CN101206356B CN101206356B CN2006101578902A CN200610157890A CN101206356B CN 101206356 B CN101206356 B CN 101206356B CN 2006101578902 A CN2006101578902 A CN 2006101578902A CN 200610157890 A CN200610157890 A CN 200610157890A CN 101206356 B CN101206356 B CN 101206356B
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Abstract
The present invention relates to a LCD panel, comprising a first basal plate, a second basal plate opposite to the first basal plate, a liquid crystal layer positioned between two basal plates, and a conductive object arranged in the liquid crystal layer. The first basal plate comprises a first substrate and a common electrode layer. The common electrode layer is positioned on the side of the first substrate close to the liquid crystal layer. The second basal plate comprises a second substrate, a plurality of common electrodes and a plurality of pixel electrodes. The common electrodes are alternately arranged on the side of the second substrate close to the liquid crystal layer. The pixel electrodes are positioned on the sides of the second substrate and the common electrodes close to the liquid crystal layer. The common electrodes are electrically connected with the common electrode layer directly via the conductive object.
Description
Technical field
The present invention relates to a kind of display panels.
Background technology
Because advantages such as display panels has gently, approaches, power consumption is little are widely used in modernized information equipments such as TV, notebook computer, mobile phone, personal digital assistant.At present, the application on the display panels TV market is more and more important.
Seeing also Fig. 1, is a kind of structural representation of display panels of prior art.This display panels 10 comprises one first substrate 110, one and this first substrate 110 second substrate 100, a frame glue 120, the liquid crystal layer 140 of a plurality of conductive gold spacer 130 and between these two substrates 110,100 that are oppositely arranged.
This frame glue 120 is sandwiched between these two substrates 110,100, and forms a receiving space with these two substrates 110,100.This receiving space is accommodated this liquid crystal layer 140.This conductive gold spacer 130 mixes in frame glue 120.
The inboard of this first substrate 110 is provided with a common electrode layer 111.This second substrate 100 comprises a substrate 150, a plurality of thin film transistor (TFT) 160, a plurality of public electrode 170, an insulation course 180, semi-conductor layer 181 and a plurality of pixel electrode 190.
This thin film transistor (TFT) 160 comprises a gate 161, one source pole 162 and a drain 163.This gate 161 and this public electrode 170 are disposed on the inner surface of this substrate 150.This insulation course 180 and this semiconductor layer 181 are covered in the surface of this gate 161 and this public electrode 170 in regular turn.This source electrode 162 and drain 163 are covered on this semiconductor layer 181, and have a groove 182 therebetween.This pixel electrode 190 is covered in the partly surface of drain 163, part substrate 150 and this insulation course 180.
This public electrode 170, this pixel electrode 190 and the insulation course 180 that is sandwiched in therebetween constitute a plurality of memory capacitance (not indicating).This common electrode layer 111, this pixel electrode 190 and the liquid crystal molecule that is sandwiched in therebetween constitute a plurality of liquid crystal capacitances (not indicating).Usually, this common electrode layer 111 is provided a stable voltage, and this pixel electrode 190 is provided a plurality of gray scale voltages, and the voltage between this common electrode layer 111 and this pixel electrode 190 is kept by this liquid crystal capacitance.
Because this liquid crystal capacitance is very little, so the time of its sustaining voltage is very short, therefore need be in the two ends of this liquid crystal capacitance this memory capacitance in parallel, with the time of lengthening sustaining voltage.Thereby this public electrode 170 need be electrically connected to this common electrode layer 111.Common electrode layer 111 and this public electrode 170 of this display panels 10 is to be connected to this conductive gold spacer 130 by external lead wire (figure does not show), is in contact with one another between these conductive gold spacers 130, thereby realizes being electrically connected.
Yet this conductive gold spacer 130 is mingled in the problem that is easy to generate density unevenness in this frame glue 120, causes occurring the disconnecting problem between a plurality of conductive gold spacers easily, thereby makes the spread of voltage of this public electrode 170, influences the display quality of this display panels 10.In addition, this conductive gold spacer 130 need think that the particle powder shape is mingled in this frame glue 120 usually, and this powder descends slowly and lightly easily in this display panels 10, causes the short circuit of circuit, thereby reduces the yield of this display panels 10.
Summary of the invention
In order to solve the lower problem of prior art display panels display quality, be necessary the display panels that provides a kind of display quality higher.
A kind of display panels, it comprises that one first substrate, second substrate, a liquid crystal layer and this two substrates between relative with this first substrate are arranged on the conductive gold spacer in this liquid crystal layer.This first substrate comprises one first substrate and a common electrode layer.This common electrode layer is positioned at close liquid crystal layer one side of this first substrate.This second substrate comprises one second substrate, a plurality of public electrode and a plurality of pixel electrode.This public electrode is disposed on close liquid crystal layer one side of this second substrate.This pixel electrode is positioned at close liquid crystal layer one side of this second substrate and this public electrode.This public electrode directly is electrically connected with this common electrode layer by this conductive gold spacer.
A kind of display panels, it comprises that one first substrate, second substrate, a liquid crystal layer and this two substrates between relative with this first substrate are arranged in the conductive gold spacer of this liquid crystal layer.This first substrate comprises one first substrate and a common electrode layer.This common electrode layer is positioned at close liquid crystal layer one side of this first substrate.This second substrate comprises one second substrate, a plurality of public electrode, a plurality of pixel electrode and a plurality of transparency electrode.This public electrode is disposed on close liquid crystal layer one side of this second substrate.This pixel electrode is positioned at close liquid crystal layer one side of this second substrate and this public electrode.This transparency electrode is adjacent with this pixel electrode, and it also is positioned at close liquid crystal layer one side of this public electrode, and and this pixel electrode between have an opening.This public electrode is electrically connected with this common electrode layer by this electrode and this conductive gold spacer.
Compared to prior art, this conductive gold spacer is arranged in this liquid crystal layer, this public electrode directly is electrically connected with this common electrode layer by this conductive gold spacer or is electrically connected with this common electrode layer by this pixel electrode and this conductive gold spacer, there is not in the prior art between the conductive gold spacer problem of disconnecting easily, therefore the voltage stability of this public electrode is preferable, thereby the display quality of this display panels is higher.
Description of drawings
Fig. 1 is a kind of structural representation of display panels of prior art.
Fig. 2 is the floor map of display panels first embodiment of the present invention.
Fig. 3 is the amplification profile synoptic diagram of Fig. 2 along III-III direction.
Fig. 4 is the structural representation of display panels second embodiment of the present invention.
Embodiment
See also Fig. 2 and Fig. 3, Fig. 2 is the floor map of display panels first embodiment of the present invention, and Fig. 3 is the amplification profile synoptic diagram of Fig. 2 along III-III direction.This display panels 20 comprises one first substrate 210, one and liquid crystal layer 230 and a plurality of conductive gold spacer 207 that be arranged in this liquid crystal layer 230 of second substrate 200, between these two substrates 210,200 that be oppositely arranged of this first substrate 210.
This first substrate 210 comprises one first substrate 211, one first alignment film 213 and a common electrode layer 212.This common electrode layer 212 and this first alignment film 213 are arranged on close liquid crystal layer 230 1 sides of this first substrate 211 in regular turn.
This second substrate 200 comprise that the multi-strip scanning line 201 that is parallel to each other, many are parallel to each other and with these sweep trace 201 vertically insulated crossing data lines 202, a plurality of thin film transistor (TFT) 240, a plurality of public electrode 204, a plurality of pixel electrode 205 and a plurality of through hole 206 that is positioned at this sweep trace 201 and this data line 202 intersections.
This sweep trace 201 and this data line 202 define a plurality of pixel regions 203.This public electrode 204 runs through this pixel region 203 and is parallel to each other with this data line 202.One through hole 206 is set in each pixel region 203, and correspondence is provided with a conductive gold spacer 207 on each through hole 206.
The gate 241 of this thin film transistor (TFT) 240 is connected to this sweep trace 201, and source electrode 242 is connected to this data line 202, and drain 243 is connected to this pixel electrode 205.
This second substrate 200 further comprises one second substrate 250, one second alignment film 260, an insulation course 270 and semi-conductor layer 280.This public electrode 204 is positioned in this second substrate 250 and same layer with the gate 241 of this thin film transistor (TFT) 240.This insulation course 270 is covered on this gate 241 and this public electrode 204.This semiconductor layer 280 is covered on the insulation course 270 of these thin film transistor (TFT) 240 correspondences.This source electrode 242 and drain 243 are positioned on this semiconductor layer 280, and have a groove (not indicating) therebetween.This through hole 206 is arranged on the insulation course 270 of these public electrode 204 correspondences, and be positioned at this insulation course 270 away from drain 243 1 sides.This pixel electrode 205 is covered on drain 243 partly, the part insulation course 270 and second substrate 250 between the two relative with this public electrode 204.This second alignment film 260 is covered in the surface of this source electrode 242, part halfbody body layer 280, this drain 243, this pixel electrode 205 and part public electrode 204.
This public electrode 204, this pixel electrode 205 and the insulation course 270 that is sandwiched in therebetween constitute a plurality of memory capacitance (not indicating).This common electrode layer 212, this pixel electrode 205 and the liquid crystal molecule that is sandwiched in therebetween constitute a plurality of liquid crystal capacitances (not indicating).
This display panels 20 can utilize the location of inkjet technology (Ink-jet PrintingTechnology) to spill conductive gold spacer 207 that the cloth technology should liquid state and spill and be distributed on this through hole 206.This liquid state be converted into solid-state after, this conductive gold spacer 207 contacts with this second alignment film 260 with this first alignment film 213.By the friction between this conductive gold spacer 207 and this two alignment films 213,260, two alignment films 213,260 at these conductive gold spacer 207 places can be removed, thereby this conductive gold spacer 207 is directly contacted with this public electrode 204 with this common electrode layer 212, then this common electrode layer 212 is electrically connected with this public electrode 204, and promptly this memory capacitance is in parallel with this liquid crystal capacitance.
When these display panels 20 normal demonstrations, this common electrode layer 212 is provided identical burning voltage with this public electrode 204, this pixel electrode 205 is provided a plurality of gray scale voltages, then produce an electric field perpendicular to these two substrates 210,220 between this pixel electrode 205 and this common electrode layer 212, this electric field is kept by this liquid crystal capacitance and this memory capacitance of parallel connection.
Compared to prior art, this conductive gold spacer 207 is arranged in this liquid crystal layer, this public electrode 204 directly is electrically connected with this common electrode layer 212 via this conductive gold spacer 207, there is not in the prior art between the conductive gold spacer problem of disconnecting easily, therefore the voltage stability of this public electrode 204 is preferable, thereby the display quality of this display panels 20 is higher.
In addition, this conductive gold spacer 207 can liquid state spills and is distributed on this through hole 206, do not exist the powder of conductive gold spacer in the prior art to descend slowly and lightly easily in the problem of display panels, so the yield of this display panels 20 is higher.
Seeing also Fig. 4, is the structural representation of display panels second embodiment of the present invention.The display panels 20 of this display panels 30 and first embodiment is roughly the same, its key distinction part is: the surface of the surface of the part public electrode 304 in this through hole 306 and the part insulation course 370 of these through hole 306 both sides has a transparency electrode 309, this transparency electrode 309 is to make simultaneously with this pixel electrode 305, and it has an opening 308 between the two, this conductive gold spacer 307 directly contacts with the transparency electrode 309 of this common electrode layer 312 with these public electrode 304 surfaces, and this common electrode layer 312 is electrically connected with this public electrode 304.This second alignment film 360 is positioned at the surface of this source electrode 342, part halfbody body layer 380, this drain 343, this pixel electrode 305 and this transparency electrode 309.
The display panels of the display panels of third embodiment of the invention and first embodiment is roughly the same, and its key distinction part is: this conductive gold spacer only is arranged on the through hole of odd column pixel region.
The display panels of the display panels of four embodiment of the invention and the 3rd embodiment is roughly the same, and its key distinction part is: this conductive gold spacer only is arranged on the through hole of even column pixel region.
It is described that display panels of the present invention is not limited to above embodiment, as: each pixel region 203 of the display panels 20 of first embodiment can be provided with a plurality of conductive gold spacers 207; The public electrode 204 of first embodiment also can be parallel with this sweep trace 201; The conductive gold spacer 207 of first embodiment also can have the conducting objects of conductive characteristic for other; The conductive gold spacer of third and fourth embodiment also can Else Rule arrangement mode be arranged in these pixel regions.
Claims (10)
1. display panels, it comprises one first substrate, one second substrate and the liquid crystal layer this two substrates between relative with this first substrate, this first substrate comprises one first substrate and a common electrode layer, this common electrode layer is positioned at close liquid crystal layer one side of this first substrate, this second substrate comprises one second substrate, a plurality of public electrodes and a plurality of pixel electrode, this public electrode is disposed on close liquid crystal layer one side of this second substrate, this pixel electrode is positioned at close liquid crystal layer one side of this second substrate and this public electrode, it is characterized in that: this display panels comprises that further one is arranged on the conductive gold spacer in this liquid crystal layer, and this public electrode directly is electrically connected with this common electrode layer by this conductive gold spacer.
2. display panels as claimed in claim 1, it is characterized in that: this second substrate further comprises an insulation course, this insulation course is positioned at the surface of close liquid crystal layer one side of this public electrode, and has at least one through hole on this insulation course, and this conductive gold spacer is arranged on this through hole.
3. display panels as claimed in claim 2, it is characterized in that: this public electrode, this pixel electrode and the insulation course that is sandwiched in therebetween constitute a plurality of memory capacitance, common electrode layer, this pixel electrode and the liquid crystal molecule that is sandwiched in therebetween constitute a plurality of liquid crystal capacitances, and this liquid crystal capacitance is in parallel with this memory capacitance.
4. display panels as claimed in claim 3 is characterized in that: when this display panels normally shows, produce an electric field perpendicular to these two substrates between this common electrode layer and this pixel electrode.
5. display panels as claimed in claim 2 is characterized in that: this display panels is to adopt the location of inkjet technology to spill the cloth technology this conductive gold spacer is spilt to be distributed on this through hole.
6. display panels as claimed in claim 5 is characterized in that: the state that this conductive gold spacer spills when being distributed on this through hole is liquid state.
7. display panels as claimed in claim 1, it is characterized in that: this display panels further comprises one first alignment film and one second alignment film, this first alignment film is arranged on close liquid crystal layer one side of this common electrode layer, this second alignment film is arranged on close liquid crystal layer one side of second substrate with this pixel electrode, this conductive gold spacer by the friction will be corresponding with it two alignment films remove.
8. display panels, it comprises one first substrate, one second substrate and the liquid crystal layer this two substrates between relative with this first substrate, this first substrate comprises one first substrate and a common electrode layer, this common electrode layer is positioned at close liquid crystal layer one side of this first substrate, this second substrate comprises one second substrate, a plurality of public electrodes and a plurality of pixel electrode, this public electrode is disposed on close liquid crystal layer one side of this second substrate, this pixel electrode is positioned at close liquid crystal layer one side of this second substrate and this public electrode, it is characterized in that: this display panels comprises that further a plurality of electrodes and adjacent with this pixel electrode are arranged in the conductive gold spacer of this liquid crystal layer, this electrode is positioned at close liquid crystal layer one side of this public electrode, and and having an opening between this pixel electrode, this public electrode is electrically connected with this common electrode layer by this electrode and this conductive gold spacer.
9. display panels as claimed in claim 8, it is characterized in that: this second substrate further comprises many parallel scanning beams, many with the vertically insulated crossing data line of this sweep trace and a plurality of thin film transistor (TFT) that is positioned at this sweep trace and this data line intersection, this sweep trace and this data line define a plurality of pixel regions.
10. display panels as claimed in claim 9, it is characterized in that: this thin film transistor (TFT) comprises a gate, an one source pole and a drain, this display panels further comprises a semi-conductor layer and an insulation course, this gate be arranged on this second substrate close liquid crystal layer one side and with this public electrode with the layer, this insulation course is arranged on this gate and this public electrode, this semiconductor layer is positioned at insulation course one side of this thin film transistor (TFT) correspondence, this source electrode and drain are positioned on this semiconductor layer, and have a groove therebetween, have at least one through hole on the public electrode of this insulation course correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101578902A CN101206356B (en) | 2006-12-22 | 2006-12-22 | Liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101578902A CN101206356B (en) | 2006-12-22 | 2006-12-22 | Liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101206356A CN101206356A (en) | 2008-06-25 |
| CN101206356B true CN101206356B (en) | 2010-12-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101578902A Expired - Fee Related CN101206356B (en) | 2006-12-22 | 2006-12-22 | Liquid crystal display panel |
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| Country | Link |
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| CN (1) | CN101206356B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5974415B2 (en) | 2011-10-05 | 2016-08-23 | 株式会社ジャパンディスプレイ | Liquid crystal display |
| CN103235437B (en) * | 2013-04-27 | 2015-12-02 | 南京中电熊猫液晶显示科技有限公司 | A kind of Liquid crystal disply device and its preparation method |
| CN104062816A (en) * | 2014-06-09 | 2014-09-24 | 深圳市华星光电技术有限公司 | Liquid crystal panel and display device |
| CN110471223B (en) * | 2019-08-15 | 2022-03-11 | 厦门天马微电子有限公司 | Display panel and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0731373A1 (en) * | 1995-03-10 | 1996-09-11 | International Business Machines Corporation | Liquid crystal display |
| CN1255648A (en) * | 1998-11-27 | 2000-06-07 | 那纳须株式会社 | Liquid crystal display and its mfg. method |
| CN1534341A (en) * | 2003-03-28 | 2004-10-06 | ���ǵ�����ʽ���� | Liquid crystal display device |
-
2006
- 2006-12-22 CN CN2006101578902A patent/CN101206356B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0731373A1 (en) * | 1995-03-10 | 1996-09-11 | International Business Machines Corporation | Liquid crystal display |
| CN1255648A (en) * | 1998-11-27 | 2000-06-07 | 那纳须株式会社 | Liquid crystal display and its mfg. method |
| CN1534341A (en) * | 2003-03-28 | 2004-10-06 | ���ǵ�����ʽ���� | Liquid crystal display device |
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| CN101206356A (en) | 2008-06-25 |
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Granted publication date: 20101229 Termination date: 20161222 |
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