CN101204029B - Spread-spectrum clock of message time sequence in communication system and method thereof - Google Patents
Spread-spectrum clock of message time sequence in communication system and method thereof Download PDFInfo
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- H04B15/00—Suppression or limitation of noise or interference
- H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
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Abstract
Methods and apparatus are provided for modulating a data rate of a clock signal. A method of transmitting a binary signal is provided comprising the steps of generating (105) random bit periods for each of a first plurality of bits in the binary signal, complementing each bit period of the first plurality of bits in the binary signal with a different bit period in a second plurality of bits in the binary signal to produce complemented pairs, and transmitting (115) the binary signal having a data rate varying with the bit periods of the binary signal. Each of the complemented pairs has a total period substantially equal to a pre-determined period. A timing apparatus for modulating a data rate of a binary signal comprises a binary sequence generator (30) configured to randomly generate a binary sequence indicating a value for modulating a bit rate of each bit in the binary signal while maintaining a signal period of the binary signal, a digital-to-analog converter (DAC) (32) having an input coupled to the binary sequence generator and having an output, and a voltage controlled oscillator (VCO) (34) having an input coupled to the output of the DAC. The DAC is configured to produce a voltage in response to the value of the binary sequence. The VCO is configured to generate a modulated binary signal having a period varying linearly with the voltage.
Description
Technical field
The present invention relates generally to the message time sequence in communication system, and the constant message time method and the sequence circuit that relate more specifically to be used for maintaining communication system.
Background technology
Serial communication system is realized easily usually and generally is used for multiple application thus.An example of serial communication system be such as via two wire bus with one or more from the device series coupled main control units (MCU).MCU to provide from device power supply and via two wire bus with communicate from device.In an example, MCU and mutual two phase places continuously from device.During first phase place, MCU provides power supply to all from device.During second phase place, MCU with from the device one of communicate.Typically, MCU uses the signal based on voltage to communicate, and uses the signal based on electric current to respond from device.
An application-specific of serial communication system is the airbag deployment system in the automobile.In airbag deployment system, master cylinders control unit and a plurality of accelerometer sensor of arranging be connected in series (for example, via two wire bus) around vehicle.Each transducer is low-power device normally, and typically, bus is powered by the master cylinders control unit.No matter the relatively low power that provides along two wire bus, be to keep enough signal to noise ratios aspect be concerned about with regard to the communication between master cylinders control unit and transducer one.
Except from the electromagnetic radiation that resides in other equipment in the vehicle, may reduce signal to noise ratio such as interference, and design needs to consider thus is that the total amount by the energy of two wire bus radiation is minimized from the electromagnetic radiation of two wire bus.Serial communication system comprise clock circuit with keep serial data synchronously, and this clock circuit may generate interference.This clock circuit comprises the driver that typically produces trapezoidal pulse.These trapezoidal pulses generally produce pulse form spectrum component (for example, the bit rate of serial data) at the harmonic wave place of fundamental frequency, and these spectrum components can reduce signal to noise ratio than large amplitude.
Except the shielding two wire bus, used low radiation Signalling method and data albefaction to reduce total amount by the energy of two wire bus radiation.Low radiation Signalling method comprises current-mode signaling rather than voltage mode signaling, utilizes the loop of twisted wire to eliminate and difference signaling.The deal with data content is represented in the data albefaction so that 0 and 1 appearance randomization, and shows similar to white noise.These two kinds of methods may all need other complicated circuit to realize.
Therefore, expectation is used for the method for the data transfer rate of randomization communication system, and this method reduces the interference for communication system.In addition, expectation is used for regulating the circuit of the data transfer rate of communication system, and this circuit reduces the interference for communication system.In addition, in conjunction with the accompanying drawings and this background note of the present invention, other desired characters of the present invention and characteristic are described in detail below of the present invention and claims will be conspicuous.
Description of drawings
Describe the present invention below in conjunction with the following drawings, wherein, same reference numbers is represented similar elements, and
Fig. 1 is based on the schematic diagram of the communication system of spread spectrum bus;
Fig. 2 is the schematic diagram of sequence circuit shown in Figure 1;
Fig. 3 is the schematic diagram of the exemplary embodiment of binary sequence; And
Fig. 4 is the flow chart that is used to transmit the method for binary message.
Embodiment
The following only actually of describing in detail of the present invention is exemplary and be not intended to limit the present invention or application of the present invention and use.In addition, be not intended to be subjected to the restriction of the theory that proposes in aforementioned background of the present invention or the following detailed description.
With reference to the accompanying drawings, Fig. 1 is based on the schematic diagram of the communication system 10 of spread spectrum bus.Communication system 10 based on spread spectrum bus (for example comprises main control unit (MCU) 12, the master cylinders control unit), have the driver 14 of first input of being coupled to MCU 12, the sequence circuit 16 of second input that is coupled to driver 14 and output one or more of being coupled to driver 14 via communication bus 22 (for example, twisted wire pair) from installing 18,20.Be provided at MCU 12 to from installing the communication between 18,20 based on the communication system 10 of spread spectrum bus via communication bus 22, this communication bus 22 is highly suitable for realizing in multiple automotive control system and other control system.Thereby though other devices can with from install 18,20 the coupling communicate with MCU 12, from install 18,20 each can be coupled with transducer 24,26 (impact microphone that for example, is used for vehicle) respectively.MCU 12 via communication bus 22 with communicate by letter and provide power supply from installing 18,20 to it.During stage of communication, transmit binary message at MCU 12 and between installing 18,20.Produce binary message in the signal that sequence circuit 16 modulation binary sequences transmit with output place at driver 14.From this signal, extract binary message from installing 18,20, and send the content of this binary message to transducer 24,26.Though with reference to having described sequence circuit 16 based on the communication system 10 of spread spectrum bus, sequence circuit 16 can be realized with the plurality of communication systems of using pulse-width modulation to communicate by letter.
Fig. 2 is the schematic diagram of the exemplary embodiment of sequence circuit 16 shown in Figure 1.Sequence circuit 16 comprises: binary sequence generator 30 has the input that is configured to the receive clock signal; Digital to analog converter (DAC) 32, the input that has output and have the output of being coupled to binary sequence generator 30; And voltage controlled oscillator (VCO) 34, has the input of the output of being coupled to DAC 32, second output of being coupled to first output of binary sequence generator 30 and being configured to be coupled with multiple serial communication apparatus, such as being coupled, as shown in Figure 1 via communication bus 22 and from installing 18,20.Sequence circuit 16 produces signal in second output place of VCO 34, carries binary message.In the exemplary embodiment, sequence circuit 16 merges with central communication control unit (MCU 12 for example shown in Figure 1), and this central communication control unit is to other devices (for example shown in Figure 1 from installing 18,20) power supply and communicate with it.
Fig. 3 is the schematic diagram that is used to utilize the exemplary embodiment of the binary sequence 40 that sequence circuit shown in Figure 1 16 modulates.Binary sequence 40 comprise bit sequence (for example B1, B2 ..., B12), and each bit have the time cycle (for example T1, T2 ..., T12).Though binary sequence 40 is described to ten two (12) individual bits and ten two (12) individual time corresponding cycles, binary sequence 40 also can have any even number bit and even number time corresponding cycle.Binary sequence 40 comprises and is used for and the data of communicating by letter from device.For example, binary sequence 40 can comprise the order from MCU shown in Figure 1 12, thereby by shown in Figure 1 extracting from installing 18,20.
With reference to figure 2 and 3, binary sequence generator 30 (for example pseudo-random binary sequence generator) generates the time cycle of each bit that is used for binary sequence 40 randomly, to produce the binary sequence after modulating.In the exemplary embodiment, binary sequence 40 has cycle total time or signal period, and it is pre-determined by communication cycle phase place (for example, at MCU shown in Figure 1 12 and from installing between 18,20).This cycle total time is maintained in the binary sequence after the modulation, is used to utilize the parts of communication system 10 (Fig. 1) to recover metastable clock frequency.For the facility of explaining, binary sequence 40 is divided into the first half (for example, low bytes) and the second half (for example, high bytes).Binary sequence generator 30 generates the time cycle of the first half each bit that is used for binary sequence 40 randomly, and each of these time cycles is all less than cycle total time of binary sequence 40.In the exemplary embodiment, binary sequence generator 30 generates the independent binary sequence of the first half each bit that is used for binary sequence 40 randomly, and this independent binary sequence has predetermined value associated therewith.Though in the first half content, described the generation at random of time cycle, binary sequence generator 30 also can generate the time cycle that is used at each bit of more than first bit of binary sequence 40 randomly, and no matter the position among this each bit more than first in binary sequence 40.In this case, binary sequence 40 is grouped into more than first bit and more than second bit, and this more than second bit has and more than first bit number that bit is identical, also takies the diverse location in binary sequence 40 simultaneously.
After foundation is used for time cycle of bit of the first half or more than first bit of binary sequence 40, then, binary sequence generator 30 generates the time cycle that is used at each bit of the second half of binary sequence 40 so that binary sequence 40 the first half in each time cycle compensate by the time cycle that is used at the second half different bits of binary sequence 40.For example, binary sequence generator 30 generate randomly time cycle of the first half of being used for binary sequence 40 (T1, T2 ..., T6), then, selection be used for binary sequence 40 time cycle of the second half (T7, T8 ..., T12), make time cycle of T1+T7=T2+T8=T3+T9=T4+T10=T5+T11=T6+T12=predetermined constant.Though time cycle of the first half of binary sequence 40 is described to sequentially to compensate time cycle of the second half of binary sequence 40, but the multiple sequence that also can use the second half the time cycle that is used to compensate binary sequence 40 (for example, sequence more at random), keep simultaneously the time cycle that is compensated relation (for example, be used for binary sequence 40 the first half bit time cycle with binary sequence 40 the second half in the summation of time cycle of compensation bit keep predetermined constant).
Can select among the embodiment, binary sequence generator 30 generates the bit rate of the first half each bit that is used for binary sequence 40 randomly, generate the bit rate of the second half each bit be used for binary sequence 40 then, make binary sequence 40 the first half in each bit rate by binary sequence 40 the second half in bit rate compensate.When compensation binary sequence 40 the first half in each bit the time, binary sequence generator 30 will be (for example, the first half the bit that is used for binary sequence 40 is together with the second half the compensation bit that is used for binary sequence 40) summation of bit rate remains predetermined constant (for example, the inverse of predetermined constant time cycle).
The value of each binary sequence that DAC 32 will be generated by binary sequence generator 30 is converted to voltage.In the exemplary embodiment, DAC 32 has the translation function that is used for the value of each binary sequence is converted to predetermined voltage.VCO 34 is clock signal via first output, and exports modulation signal via second output.Modulation signal has the cycle of linear change along with the voltage that receives from DAC 32.Locate modulation signal is combined with signal of communication at driver 14 (Fig. 1), to produce the signal of communication after modulating, such as pulse-width modulation (PWM) signal.For example, VCO 34 generates the square wave clock signal, and this square wave clock signal is based on the PWM from the voltage of DAC 32.For PWM bus code standard, the logical one signal that VCO 34 outputs have 2/3rds (2/3) duty cycle pulse, and export logic zero signal with 1/3rd (1/3) duty cycle pulse.
Fig. 4 is the flow chart that is used to transmit the method for binary message (for example PWM message).This method is in 100 beginnings.With reference to figure 2 and 4, in step 105, binary sequence generator 30 generates the random bit rate of the first half each bit that is used for PWM message.Selectively, binary sequence generator 30 generates the random time cycle of the first half each bit that is used for PWM message.PWM message has cycle total time, and the 30 generation random time cycles of binary sequence generator, and each of the feasible time cycle that is generated is all less than cycle total time.In the exemplary embodiment, binary sequence generator 30 generates the binary sequence of the first half each bit that is used for PWM message randomly.Each binary sequence that generates is at random represented value.
Then, in step 110, binary sequence generator 30 selects to be used for the bit rate or the time cycle of each bit of the second half of PWM message.PWM message the second half in each bit rate or the time cycle compensation PWM message the first half in different bit rates or time cycle.In one exemplary embodiment, binary sequence generator 30 with PWM message the second half in the order of bit sequence, select to be used for the compensation bit rate or the time cycle of each bit of the second half of PWM message.In a further exemplary embodiment, binary sequence generator 30 be chosen in PWM message the second half in the compensation bit rate, make every pair the summation of time cycle of the bit rate of compensation or compensation be substantially equal to predetermined constant.
VCO 34 transmits the signal with PWM message in step 115.This signal has the data transfer rate that changes along with the bit rate of PWM message or time cycle.In one exemplary embodiment, the value of binary sequence that DAC 32 will be used for each bit of PWM message is converted to voltage, and VCO 34 transmits and has along with from the voltage of DAC 32 and the signal in the cycle of linear change.
By generating the bit rate that is used at the successive bits of binary message randomly, the frequency spectrum of binary message is launched on bigger bandwidth, and having reduced interference usually near the wireless device of operating the communication bus, sequence circuit 16 (Fig. 2) provides the low-power that is ideally suited for based on the communication system of pulse-width modulation to communicate by letter with low radiation data thus.In addition, the binary message that is produced by sequence circuit 16 (Fig. 2) has metastable time reference (timereference), so that the detection of the message time of binary message is provided for the steady sequential clock signal of signal sampling.
In the exemplary embodiment, be provided for transmitting the method for binary signal.This method may further comprise the steps: generate the random bit cycle that is used for each bit in more than first bit of binary signal; Different bit periods in more than second bit of utilization in binary message compensate each bit period of more than first bit in binary signal, and are right to produce compensation; And transmission has the binary signal of the data transfer rate that changes along with the bit period of binary signal.Each compensation is to having the total cycle that is substantially equal to predetermined period.More than first bit in binary signal be have order binary signal the first half, and compensation process comprises: based on the first half order of binary signal, utilize the first half bit period of binary signal to compensate the second half bit period of this binary signal.This binary signal has the signal period, and the bit period that is used for each bit in more than first bit of binary signal is less than the signal period.Generate step and comprise that generation randomly is used for the binary sequence of each bit in more than first bit of binary signal, this binary sequence is represented value.The method that is used to transmit binary signal may further include the step that the value of binary sequence is converted to voltage, and transfer step can comprise and transmits the binary signal with the cycle that changes along with this voltage linear.
In a further exemplary embodiment, be provided for transmitting the method for message signale.This method may further comprise the steps: the random bit rate that generates the first half each bit be used for message signale; Selection is used for the bit rate of each bit of the second half of message signale; And transmit the signal have this message signale and have the data transfer rate that changes along with the bit rate of message signale.Message signale the second half in each bit rate compensation message signale the first half in different bit rates.This message signale comprises pulse-width modulation (PWM) message.Generate step and comprise and generate binary sequence randomly, and this binary sequence is represented value.This method may further include step: binary sequence is converted to voltage, and produces and to have along with this voltage and the signal in the cycle of linear change.The first half of message signale has order, and selects step to comprise: based on the first half order of message signale, utilize the first half bit rate of message signale, select the second half bit rate of message signale.PWM message has the message time cycle, and generates step and comprise the time cycle that generates the first half each bit that is used for PWM message randomly, and the time cycle of each bit of the first half that is used for PWM message is less than the message time cycle.PWM message the second half in each bit have the time cycle, and bit rate selects step to comprise: with PWM message the first half in each bit and this PWM message the second half in different bit pairings, to produce a plurality of paired bits, the summation of the time cycle of each paired bit is a constant.
In another exemplary embodiment, be provided for modulating the sequence equipment of the data transfer rate of binary signal with signal period.This sequence equipment comprises: binary sequence generator, be configured to generate randomly the binary sequence of expression value, and be used for being modulated at the bit rate of each bit of binary signal, keep the signal period simultaneously; Digital to analog converter (DAC) has the input of being coupled to binary sequence generator and has output; And voltage controlled oscillator (VCO), have the input of the output of being coupled to DAC.This DAC is configured to produce voltage in response to the value of binary sequence.VCO is configured to produce the binary signal after the modulation with cycle of linear change along with voltage.Binary sequence generator comprises the pseudo-random binary sequence generator that is configured to generate randomly binary sequence.This pseudo-random binary sequence generator is configured to generate randomly the binary sequence of each bit of more than first bit that is used for binary signal, each expression random bit rate of this binary sequence.This pseudo-random binary sequence generator is further configured the bit rate for each bit of more than second bit selecting to be used for binary signal, the different bit rates of each bit rate compensation in more than first bit in more than second bit.Binary sequence generator comprises pseudo-random binary sequence generator, and it is configured to generate randomly the bit sequence that is used at each bit of more than first bit of binary signal, each expression random time cycle of bit sequence.Pseudo-random binary sequence generator is further configured to selecting to be used for the bit period at each bit of more than second bit of binary signal, a plurality of right to produce, each bit period of more than first bit compensates the different bit periods of more than second bit, to produce pre-determined total period.Each bit period in more than first bit is less than pre-determined total period.More than first bit be have order binary signal the first half, and more than second bit is the second half of this binary signal, and pseudo-random binary sequence generator is further configured to sequentially select to be used for the bit period of each bit of the second half based on this order.
Though in detailed description before, presented at least one exemplary embodiment, should be understood that to have a lot of variants.It will also be appreciated that exemplary embodiment or a plurality of exemplary embodiment only are examples, be not intended to limit the scope of the invention by any way, applicability or configuration.But preceding detailed description will be provided for the route map easily (road map) of realization example embodiment or a plurality of exemplary embodiments to those skilled in the art.Should be understood that under the situation of the scope of the present invention that can in not departing from, set forth, can carry out multiple change in the function of key element with in arranging as claims and legal equivalents thereof.
Claims (20)
1. method that is used to transmit binary signal, described method comprises step:
Generation (105) is used for the random bit cycle at each bit of more than first bit of described binary signal;
Different bit periods in more than second bit of utilization in described binary signal compensate each bit period of described more than first bit in described binary signal, right to produce compensation, each described compensation is to having the total cycle that is substantially equal to predetermined period; And transmission (115) has the described binary signal of the data transfer rate that changes along with the bit period of described binary signal.
2. the method that is used to transmit binary signal according to claim 1, wherein, described more than first bit be have order described binary signal the first half, wherein, described more than second bit is the second half of described binary signal, and wherein, described compensation process comprises: based on described the first half described order of described binary signal, utilize described the first half described bit period of described binary signal to compensate described the second half described bit period of described binary signal.
3. the method that is used to transmit binary signal according to claim 1, wherein, described binary signal has the signal period, and the described bit period of each bit that wherein is used for described more than first bit is less than the described signal period.
4. the method that is used to transmit binary signal according to claim 1, wherein, described generation step comprises the binary sequence that generates each bit that is used for described more than first bit randomly, described binary sequence is represented value.
5. the method that is used to transmit binary signal according to claim 4, comprise that further the value with described binary sequence is converted to the step of voltage, and wherein, described transfer step comprises that transmission has the described binary signal in the cycle that changes along with described voltage linear.
6. the method that is used to transmit binary signal according to claim 1, wherein, described transfer step comprise with described binary signal from the master cylinders control unit be sent at least one from the device.
7. the method that is used to transmit binary signal according to claim 1, wherein, described transfer step comprises along vehicle communication bus and transmits described binary signal.
8. method that is used to transmit message signale, described method comprises step:
Generate the random bit rate that (105) are used for each bit of the first half of described message signale;
Select (110) to be used for the bit rate of each bit of the second half of described message signale, described each bit rate compensation of described the second half of described message signale described message signale described the first half in different bit rates; And
Transmit the signal that (115) have described message signale, described signal has the data transfer rate that changes along with the described bit rate of described message signale.
9. method according to claim 8, wherein, described message signale comprises pulse-width modulation (PWM) message.
10. method according to claim 8, wherein, described generation step comprises randomly the binary sequence that generates described the first half each bit that is used for described message signale, described binary sequence is represented value.
11. method according to claim 10 further comprises step:
Described binary sequence is converted to voltage; And
Generation has the described signal in the cycle that changes along with described voltage linear.
12. method according to claim 8, wherein, described the first half of described message signale has order, and wherein, described selection step comprises: based on described the first half described order of described message signale, utilize described the first half described bit rate of described message signale, select described the second half described bit rate of described message signale.
13. method according to claim 9, wherein, described PWM message has the message time cycle, wherein, described generation step comprises randomly the time cycle that generates described the first half each bit that is used for described PWM message, the time cycle of each bit of described the first half that is used for described PWM message is less than the described message time cycle, wherein, described PWM message described the second half in each bit have the time cycle, and wherein, described bit rate select step comprise with described PWM message described the first half in each bit and described PWM message described the second half in different bits match, producing a plurality of paired bits, the described time cycle of every pair of described paired bit and remain unchanged.
14. a sequence equipment that is used to modulate the data transfer rate of the binary signal with signal period, described sequence equipment comprises:
Binary sequence generator (30) is configured to generate randomly the binary sequence of expression value, is used for modulating the bit rate of each bit of described binary signal, keeps the described signal period simultaneously;
Digital to analog converter (DAC) (32) has the input of being coupled to described binary sequence generator and has output, and described DAC produces voltage in response to the described value of described binary sequence; And
Voltage controlled oscillator (VCO) (34) has the input of the described output of being coupled to described DAC, and described VCO is configured to produce the binary signal after the modulation with the cycle that changes along with described voltage linear.
15. equipment according to claim 14, wherein, described binary sequence generator comprises the pseudo-random binary sequence generator that is configured to generate randomly described binary sequence.
16. equipment according to claim 15, wherein, described pseudo-random binary sequence generator is configured to generate randomly the binary sequence of each bit of more than first bit that is used for described binary signal, each expression random bit rate of described binary sequence.
17. equipment according to claim 16, wherein, described pseudo-random binary sequence generator further is configured to select to be used for the bit rate of each bit of more than second bit of described binary signal, the different bit rates of each compensation in described more than first bit of the described bit rate in described more than second bit.
18. equipment according to claim 14, wherein, described binary sequence generator comprises pseudo-random binary sequence generator, it is configured to generate randomly the binary sequence of each bit of more than first bit that is used for described binary signal, each expression random time cycle of described binary sequence.
19. equipment according to claim 18, wherein, it is a plurality of right to produce that described pseudo-random binary sequence generator further is configured to select to be used for the bit period of each bit of more than second bit of described binary signal, each bit period of described more than first bit compensates the different bit periods of described more than second bit, to produce predetermined total cycle.
20. equipment according to claim 19, wherein, described more than first bit be have order described binary signal the first half, and described more than second bit is the second half of described binary signal, and wherein, described pseudo-random binary sequence generator further is configured to sequentially to select to be used for based on described order the described bit period of each bit of described the second half.
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| PCT/US2005/021088 WO2007001254A1 (en) | 2005-06-15 | 2005-06-15 | Spread spectrum clock and method for message timing in a communication system |
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| CN101204029B true CN101204029B (en) | 2011-03-09 |
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| US9973835B2 (en) | 2013-01-28 | 2018-05-15 | Infineon Technologies Ag | Signal generator, a decoder, a method for generating a transmit signal and a method for determining speed data |
| CN107015937B (en) * | 2017-03-27 | 2019-07-16 | 西安微电子技术研究所 | A kind of low-voltage high speed Perceptual Load Drive Circuit |
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| US4644299A (en) * | 1986-02-14 | 1987-02-17 | Hughes Aircraft Company | Multimode noise generator using digital FM |
| US4697157A (en) * | 1986-10-17 | 1987-09-29 | Hughes Aircraft Company | Inherently flat spectral density pseudorandom noise generator |
| CN1086735A (en) * | 1993-03-18 | 1994-05-18 | 徐福华 | A kind of electric pulse traditional Chinese medical science integral treatment instrument |
| CN1213571A (en) * | 1997-10-05 | 1999-04-14 | 徐福华 | Chinese medicinal electromagnetic integral treatment instrument |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4834086B2 (en) | 2011-12-07 |
| CN101204029A (en) | 2008-06-18 |
| JP2008544640A (en) | 2008-12-04 |
| WO2007001254A1 (en) | 2007-01-04 |
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