CN101202628B - Method for realizing of Hach coprocessor - Google Patents
Method for realizing of Hach coprocessor Download PDFInfo
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- CN101202628B CN101202628B CN2006101649700A CN200610164970A CN101202628B CN 101202628 B CN101202628 B CN 101202628B CN 2006101649700 A CN2006101649700 A CN 2006101649700A CN 200610164970 A CN200610164970 A CN 200610164970A CN 101202628 B CN101202628 B CN 101202628B
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Abstract
The invention provides a realizing method for a grouping hash coprocessor, which belongs to the field of information security password and can realize data encrypting calculation and participate in signature verification. The grouping hash coprocessor realized by using the method supports a grouping password system and HASH calculation, supports high and low speed data interfaces and a pipeline structure, can realize the functions of single grouping, single hash, first grouping then hash and simultaneous grouping and hash, etc., and has better practicability. The hardware parts used for realizing the functions include a grouping calculation unit, a hash calculation unit, a low speed data interface reading and writing control unit, a high speed data interface treatment unit (consisting of an input FIFO1 and an output FIFO2), a coprocessor core control unit and a double-opening RAM, an interior FIFO3, a command register, a block number register, a parameter register, a grouping input buffer register Inda and a grouping output buffer register Outda, etc.
Description
Technical field
The utility model relates to information security password field, and specifically, the hardware that relates to grouping and HASH crypto-operation coprocessor is realized.
Background technology
Along with popularizing of computer network, a large amount of electronic data becomes possibility by Network Transmission to all over the world.But in the transmission course of the significant datas such as destiny with great economic worth or relation country, army, reveal any point and mistake all may cause immeasurable loss.Cryptographic technique then is the guarantee and the core technology of information security.
Though the public key algorithm encryption can solve many private key algorithm and encrypt indeterminable problem, can face more and more huger data volume, from practical standpoint, often fast a lot of times of the speed of private key password encryption than PKI, the private key cryptographic algorithm still is the main flow that mass data is encrypted.Therefore in a cryptographic system, can use block cipher and public key algorithm simultaneously.Grouping algorithm is realized the encryption to transmission data itself, and public key algorithm is realized the encryption to key in the grouping algorithm.
Block cipher is a branch of symmetric cryptographic algorithm, and so-called symmetric cryptography is meant enciphering and deciphering algorithm form symmetry, and encryption key is identical with decruption key.Another branch of symmetric cryptography is a stream cipher, and by bit encryption, during deciphering, key stream needs synchronous with ciphertext.And block cipher is that plaintext (or ciphertext) is encrypted, transmits, deciphered by certain bit length grouping.Improved the required key stream of stream cipher synchronous problem in real time to a great extent.The different mode of operation (for example ECB, CBC etc.) of block cipher one-tenth also capable of being combined satisfies the demand of cipher protocol.The decrypting process of block cipher is the inverse process of encrypting.The fail safe of system is the confidentiality of key.The most frequently used algorithm is DES (3DES) and AES.
Certainly, in complete cryptographic system, not only there is the encryption and decryption problem of data, also comprises the checking of data correctness.For guaranteeing that data are not distorted in transmission course, it is essential that digital signature has become.For very long information signature method more complicated, solution to this problem is utilized the HASH function exactly, produces the eap-message digest of a regular length, at last this eap-message digest is signed.
Three character that the HASH function satisfies: 1) compressibility, the input of random length all is compressed into the output of regular length; 2) easy computational, given input, it is easy calculating output; 3) irreversibility is just calculated upward irreversible.The most frequently used algorithm is MD series and SHA series.
Summary of the invention
Hach coprocessor of the present invention designs for realizing data encrypting and deciphering computing and signature verification, it supports block cipher system and HASH computing, support high low speed data-interface and pipeline organization, can realize function combinations such as single grouping, single Hash, elder generation's grouping back Hash and while Hach, have very strong practicality.
The hardware component of realizing this function comprises: grouping arithmetic element, Hash operation unit, low speed data interface read-write control unit, high speed interface processing unit (being made up of input FIFO1 and output FIFO2), coprocessor key control unit and dual port RAM, inner FIFO3, command register, piece number register, parameter register, grouping input buffer register Inda and a grouping output buffer Outda etc.
This coprocessor is supported high speed interface and low speed data interface simultaneously, and the high-speed data mouth is supported the input of 32 bit data, and the low speed data mouth is supported the input of 8,16,32 bit data.
Wherein dual port RAM, command register, piece number register and parameter register all carry out unified addressing respectively to low speed data mouth ppu and innernal CPU, so that by address wire control it is conducted interviews.
Order, piece number and parameter are only by the input of low speed data interface, and required plaintext or the ciphertext of encryption and decryption both can also can be imported by the high-speed data mouth by the input of low speed data mouth.
Encryption and decryption data is followed the principle of where going back and forth from which, if promptly expressly advance from the low speed data mouth, then ciphertext also goes out from the low speed data mouth, advances from the high-speed data mouth, then goes out from the high-speed data mouth.
When encryption and decryption data was imported by the low speed data mouth, the outside will be sent out piece number, parameter and encryption and decryption data earlier, and then says the word; When encryption and decryption data was imported by high speed interface, the low speed data interface was still followed the sequencing of piece number → parameter → order, but carried encryption and decryption data not have sequencing with the high-speed data mouth, and both can independently carry out.
This coprocessor is supported to divide into groups simultaneously and fill and outside the filling inside of Hash.
The piece number that the piece number register is deposited is to be got divided by 32 by the plaintext that participates in encryption and decryption or the bit number of ciphertext, doing grouping separately, Hach is done and earlier under the situation of grouping back Hash simultaneously, piece numerical table during outside the filling shows the later length of grouping filling, and the piece numerical table during inner the filling shows the true length of grouped data; When doing Hash separately, the piece numerical table during outside the filling shows the later length of Hash filling, and the piece numerical table during inner the filling shows the true length of Hash data.
Order is to give the coprocessor key control unit after being resolved by innernal CPU, carries out the control of corresponding computing, can support the user defined command agreement by revising software like this.
When same group of data being divided into groups simultaneously,,, introduce an inner FIFO3 and come data are carried out buffer memory to prevent loss of data in the porch of hash units for solving grouping and the unmatched problem of Hash operation speed with Hash operation.
When dividing into groups computing, be raising speed, the coprocessor key control unit is introduced pipeline organization, promptly sends out data → send out and enables → give one group of data → detections done → read data → enable, and utilizes to be ready to next operation time and to organize pending data.
When data are imported by the low speed data interface, data are moved from RAM in the coprocessor key control unit by innernal CPU, in like manner operation result is also moved among the RAM by innernal CPU, the convenient so spontaneous situation of carrying out computing of innernal CPU of supporting, only need write-in block number → parameter → order successively, send pending data to the coprocessor key control unit again and get final product.
In this coprocessor, owing to support the computing of multitude of different ways and speed, need shake hands in a large number, introduce handshake register, as to write fashionable flag be 1, flag is 0 when reading.Outside from low speed data interface write command register, flag is 1, it is 1 that innernal CPU detects flag, the indication outside has write new order, then take out and resolve, flag becomes 0 simultaneously, and external detection becomes 0 to flag, represent that then command analysis finishes, next new order can be continued to send in the outside.
This coprocessor is supported following all kinds of instructions: the selection of data inlet, mode of operation selection, algorithm selection, encryption and decryption selection, encryption and decryption model selection, key length selection and Hash length are selected.
The workflow of this coprocessor may further comprise the steps:
(1) outsidely sends out piece number, parameter, pending data and order.Wherein pending data can go into also to go into from high speed interface from the low speed data interface, and inlet selection information is included in the order.
(2) innernal CPU resolve command, and analysis result sent into key control unit.
(3) the key control unit judgment data is advanced from the low speed data interface, then forwards (4) to, and data are advanced from high speed interface, then forwards (16) to, and to be that innernal CPU is spontaneous send data, then forwards (4) to.
(4) as singly doing grouping, forward (5) to, singly do Hash, forward (7) to, Hach is done simultaneously, forwards (10) to, and grouping back Hash forwards (13) to earlier.
(5) receive data that innernal CPU sends here in Inda, send enable signal, change (6) to grouped element.
(6) wait for when grouping done signal is effective, the output result, reading for innernal CPU (is the situations of being gone into by the low speed data interface as data, the result also will be sent to dual port RAM by innernal CPU, read for the outside), count judgment data according to piece simultaneously and whether all handle, as do not have, then change (5), finish as handling then.
(7) receive the data that innernal CPU is sent here, send among the inside FIFO3 of Hash porch, and send enable signal to hash units.Change (8).
(8) hash units is received enable signal, according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data, change (9).
When (9) the done signal of coprocessor wait Hash was effective, the output result read (as data are the situations of being gone into by the low speed data interface, and the result also will be sent to dual port RAM by innernal CPU, reads for the outside) for innernal CPU.
(10) receive the data that innernal CPU is sent here,, data are delivered among Inda and the inner FIFO3 simultaneously, and sent enable signal to grouped element and hash units when FIFO3 is non-when full.Change (11).
When (11) detection grouping done signal is effective, the output result, reading for innernal CPU (is the situations of being gone into by the low speed data interface as data, the result also will be sent to dual port RAM by innernal CPU, reads for the outside), count judgment data according to piece simultaneously and whether all handle, as do not have, then change (10),, then change (12) as handling.
When (12) detection Hash done signal was effective, the output result read (as data are the situations of being gone into by the low speed data interface, and the result also will be sent to dual port RAM by innernal CPU, reads for the outside) for innernal CPU.
(13) receive data that innernal CPU sends here in Inda, send enable signal, also send enable signal simultaneously to hash units to grouped element.Change (14).
(14) wait for when grouping done signal is effective, group result is moved among the inside FIFO3 of Hash porch, handle for hash units, it (is the situations of being gone into by the low speed data interface as data that the while result is read away by innernal CPU, the result also will be sent to dual port RAM by innernal CPU, reads for the outside).Count judgment data according to piece and whether all handle, then change in this way (15), otherwise change (13).
(15) wait for that when Hash done signal was effective, the output result read (as data are the situations of being gone into by the low speed data interface, and the result also will be sent to dual port RAM by innernal CPU, reads for the outside) for innernal CPU.
(16) as singly doing grouping, forward (17) to, singly do Hash, forward (21) to, Hach is done simultaneously, forwards (24) to, and grouping back Hash forwards (29) to earlier.
(17) from high speed interface input FIFO1, receive data in Inda, change (18).
(18) send enable signal to grouped element.Change (19).
(19) receive next group data from high speed interface input FIFO1 in Inda, the computing of dividing into groups simultaneously realizes water operation, changes (20).
(20) wait for when grouping done signal is effective, output results among the output FIFO2, read, count judgment data according to piece simultaneously and whether all handle, as do not have, then change (18), finish as handling then for the high speed interface outside.
(21) from high speed interface input FIFO1, receive data, send among the inside FIFO3 of Hash porch, and send enable signal to hash units.Change (22).
(22) hash units is received enable signal, according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data, change (23).
When (23) the done signal of coprocessor wait Hash is effective, output results among the output FIFO2, read for the high speed interface outside.
(24) from high speed interface input FIFO1, receive data,, data are delivered among Inda and the inner FIFO3 simultaneously, change (25) when FIFO3 is non-when full.
(25) send enable signal to grouped element and hash units, change (26).
(26) from high speed interface input FIFO1, receive next group data,, data are delivered among Inda and the inner FIFO3 simultaneously, divide into groups simultaneously and Hash operation, realize water operation, change (27) when FIFO3 is non-when full.
Whether when (27) detection grouping done signal is effective, output results to output FIFO2, read for the high speed interface outside, count judgment data according to piece simultaneously and all handle, as do not have, then commentaries on classics (25) as handling, is then changeed (28).
When (28) detection Hash done signal is effective, output results to output FIFO2, read for the high speed interface outside.
(29) receive data to Inda from high speed interface input FIFO1, change (30).
(30) send enable signal to grouped element, also send enable signal simultaneously to hash units.Turn to (31).
(31) receive next group data to Inda from high speed interface input FIFO1, the computing of dividing into groups simultaneously realizes water operation, turns to (32)
(32) wait for when grouping done signal is effective, group result is outputed to FIFO2, read for the high speed interface outside, the result also is shifted among the inside FIFO3 of Hash porch simultaneously, handles for hash units.
Count judgment data according to piece then and whether all handle, then change in this way (33), otherwise change (30).
(33) wait for when Hash done signal is effective, output results to output FIFO2, read for the high speed interface outside.As seen from the above description, the present invention has the following advantages:
(1) supports high speed and low-speed interface simultaneously, satisfy the needs under user's different condition;
(2) support multiple block cipher;
(3) support multiple hash algorithm;
(4) be speed up processing, adopt pipeline organization;
(5) support the inside of grouping and Hash to fill and outside the filling simultaneously, use more flexible;
(6) support the user to come the custom command agreement by revising software;
(7) support to carry out simultaneously block cipher and Hash operation;
When (8) being supported in the outside and obtaining encrypted result, also obtain corresponding Hash operation result.
Description of drawings
(1) coprocessor hardware component structural representation
(2) data are by the process chart of high speed interface input
(3) data are by the process chart of low speed data interface input
Embodiment
The structure of being set forth in the concrete enforcement fundamental sum of the present invention specification of the present invention is consistent with principle.Below in conjunction with accompanying drawing, specify the present invention.
The invention discloses a kind of implementation of Hach coprocessor, its hardware component comprises: grouping arithmetic element, Hash operation unit, low speed data interface read-write control unit, high speed interface processing unit (being made up of input FIFO1 and output FIFO2), coprocessor key control unit and dual port RAM, inner FIFO3, command register, piece number register, parameter register, grouping input buffer register Inda and a grouping output buffer Outda etc.
See also the solid line boxes part of accompanying drawing 1, the hardware component structural representation that it utilizes said structure to realize for the present invention.According to this schematic diagram, this hardware component is made of above-mentioned several sections.
The wherein low speed data interface read-write control unit read-write that comes control data according to the bit wide (8bits, 16bits, 32bits) and the address of low speed data interface.
Dual port RAM carries out the buffer unit of transfer of data as low speed data interface and inner cpu processor, respectively low speed data interface ppu and inner cpu processor are carried out unified addressing with command register, piece number register, parameter register, so that inside and outside to its visit.
Input FIFO1 and output FIFO2 form high speed interface, buffer unit as high speed interface transmission data, Inda and Outda carry out the buffer unit of transfer of data as coprocessor key control unit and grouping arithmetic element, and inner FIFO3 carries out the buffer unit of transfer of data as coprocessor key control unit and Hash operation unit.
The coprocessor key control unit is the maincenter of whole coprocessor, and he is responsible for control and finishes all kinds of computings, as: Hash, Hach are done etc. simultaneously after single grouping, single Hash, the grouping earlier.
Following conjunction with figs. is further set forth the specific embodiment of the present invention.
This coprocessor externally divides low speed data interface and high speed interface, support the situation of the spontaneous computing of inner cpu simultaneously, because data are fashionable by the low speed data interface, all do transfer and enter core processing unit through inner cpu, so the situation of the spontaneous computing of inner cpu is included in the middle of the situation that data are gone into by the low speed data interface, so we introduce data and are gone into the low speed data interface to go into two kinds of situations by high speed interface at this.
(1) situation of being gone into by high speed interface for data referring to accompanying drawing 2, may further comprise the steps:
(1) send out piece number, parameter and order successively by the low speed data interface, pending data are entered by the high speed FIFO mouth simultaneously.
(2) innernal CPU resolve command, and analysis result sent into key control unit.
(3) key control unit is judged as is singly done grouping, forwards (4) to, singly does Hash, forwards (8) to, and Hach is done simultaneously, forwards (11) to, and grouping back Hash forwards (16) to earlier.
(4) from high speed interface input FIFO1, receive data in Inda.
(5) send enable signal to grouped element.
(6) receive next group data from high speed interface input FIFO1 in Inda, the computing of dividing into groups simultaneously realizes water operation.
(7) wait for when grouping done signal is effective, output results among the output FIFO2, read, count judgment data according to piece simultaneously and whether all handle, as do not have, then change (5),, then finish as handling for the high speed interface outside.
(8) from high speed interface input FIFO1, receive data, send among the inside FIFO3 of Hash porch, and send enable signal to hash units.
(9) hash units is received enable signal, according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data.
When (10) the done signal of coprocessor wait Hash is effective, output results among the output FIFO2, read for the high speed interface outside.
(11) from high speed interface input FIFO1, receive data,, data are delivered among Inda and the inner FIFO3 simultaneously when FIFO3 is non-when full.
(12) send enable signal to grouped element and hash units.
(13) from high speed interface input FIFO1, receive next group data,, data are delivered among Inda and the inner FIFO3 simultaneously, divide into groups simultaneously and Hash operation, realize water operation when FIFO3 is non-when full.
Whether when (14) detection grouping done signal is effective, output results to output FIFO2, read for the high speed interface outside, count judgment data according to piece simultaneously and all handle, as do not have, then commentaries on classics (12) as handling, is then changeed (15).
When (15) detection Hash done signal is effective, output results to output FIFO2, read for the high speed interface outside.
(16) receive data to Inda from high speed interface input FIFO1.
(17) send enable signal to grouped element, also send enable signal simultaneously to hash units.
(18) receive next group data to Inda from high speed interface input FIFO1, the computing of dividing into groups simultaneously realizes water operation.
(19) wait for when grouping done signal is effective, group result is outputed to FIFO2, read for the high speed interface outside, the result also is shifted among the inside FIFO3 of Hash porch simultaneously, handles for hash units.
Count judgment data according to piece then and whether all handle, then change in this way (20), otherwise change (17).
(20) wait for when Hash done signal is effective, output results to output FIFO2, read for the high speed interface outside.
(2) situation of being gone into by the low speed data interface for data referring to accompanying drawing 3, may further comprise the steps:
(1) outside distribute piece number, parameter, pending data by the low speed data interface after, say the word again.
(2) innernal CPU resolve command, and analysis result sent into key control unit.
(3) key control unit is judged as is singly done grouping, forwards (4) to, singly does Hash, forwards (6) to, and Hach is done simultaneously, forwards (9) to, and grouping back Hash forwards (12) to earlier.
(4) receive data that innernal CPU sends here in Inda, send enable signal to grouped element.
(5) wait for that the output result was sent to dual port RAM by innernal CPU, reads for the outside when grouping done signal was effective, count judgment data according to piece simultaneously and whether all handle, as do not have, then change (4),, then finish as handling.
(6) receive the data that innernal CPU is sent here, send among the inside FIFO3 of Hash porch, and send enable signal to hash units.
(7) hash units is received enable signal, according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data.
When (8) the done signal of coprocessor wait Hash was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside.
(9) receive the data that innernal CPU is sent here,, data are delivered among Inda and the inner FIFO3 simultaneously, and sent enable signal to grouped element and hash units when FIFO3 is non-when full.。
Whether when (10) detection grouping done signal was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside, count judgment data according to piece simultaneously and all handle, as do not have, and then changeed (9), as handling, and then commentaries on classics (11).
When (11) detection Hash done signal was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside.
(12) receive data that innernal CPU sends here in Inda, send enable signal, also send enable signal simultaneously to hash units to grouped element.
Wait for when grouping done signal is effective (13), group result moved among the inside FIFO3 of Hash porch that handle for hash units, the result is sent to dual port RAM by innernal CPU simultaneously, reads for the outside.Count judgment data according to piece and whether all handle, then change in this way (14), otherwise change (12).
(14) wait for that when Hash done signal was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside.
Claims (9)
1. Hach coprocessor for realizing that data encrypting and deciphering computing and signature verification design, it is characterized in that supporting block cipher system and HASH computing, support high low speed data-interface and pipeline organization, can realize single grouping, single Hash, elder generation's grouping back Hash and while Hach function combinations; Hardware component comprises: grouping arithmetic element, Hash operation unit, low speed data interface read-write control unit, high speed interface processing unit FIFO1 and FIFO2, coprocessor key control unit and dual port RAM, inner FIFO3, command register, piece number register, parameter register, grouping input buffer register Inda and a grouping output buffer Outda; Wherein:
Described grouping arithmetic element and Hash operation unit are realized divide into groups computing and Hash operation respectively;
The read-write that described low speed data interface read-write control unit comes control data according to the bit wide and the address of low speed data interface;
Described dual port RAM carries out unified addressing with command register, piece number register, parameter register to low speed data interface ppu and innernal CPU as the buffer unit of low speed data interface;
Described high speed interface processing unit FIFO1 and FIFO2 form high speed interface, as the buffer unit of high speed interface processing unit transmission data;
Described grouping input buffer register Inda and grouping output buffer Outda carry out the buffer unit of transfer of data as coprocessor key control unit and grouping arithmetic element, and inner FIFO3 carries out the buffer unit of transfer of data as coprocessor key control unit and Hash operation unit;
All kinds of computings are finished in described coprocessor key control unit control.
2. Hach coprocessor as claimed in claim 1, it is characterized in that: support high speed interface and low speed data interface simultaneously, high speed interface is supported the input of 32 bit data, the low speed data interface is supported the input of 8,16,32 bit data, wherein order, piece number and parameter are imported by the low speed data interface only, and required plaintext or the ciphertext of encryption and decryption both can also can have been imported by high speed interface by the input of low speed data interface; When encryption and decryption data was imported by the low speed data interface, the outside will be sent out piece number, parameter and encryption and decryption data earlier, and then says the word; When encryption and decryption data was imported by high speed interface, the low speed data interface was still followed the sequencing of piece number → parameter → order, but carried encryption and decryption data not have sequencing with high speed interface, and both can independently carry out; Encryption and decryption data is followed the principle of where going back and forth from which, if promptly expressly advance from the low speed data interface, then ciphertext also goes out from the low speed data interface, advances from high speed interface, then goes out from high speed interface.
3. Hach coprocessor as claimed in claim 1 is characterized in that: this coprocessor is supported to divide into groups simultaneously and fill and outside the filling inside of Hash.
4. Hach coprocessor as claimed in claim 1 is characterized in that order is to give the coprocessor key control unit after being resolved by innernal CPU, carries out the control of corresponding computing, can support the user defined command agreement by revising software like this.
5. Hach coprocessor as claimed in claim 1, it is characterized in that when same group of data being divided into groups simultaneously with Hash operation, for solving grouping and the unmatched problem of Hash operation speed, porch in the Hash operation unit is introduced an inner FIFO3 and is come data are carried out buffer memory to prevent loss of data.
6. Hach coprocessor as claimed in claim 1, it is characterized in that when dividing into groups computing, be raising speed, the coprocessor key control unit is introduced pipeline organization, promptly send out data → send out and enable → give one group of data → detections done → read data → enable, utilize to be ready to next operation time and to organize pending data.
7. Hach coprocessor as claimed in claim 1, it is characterized in that when data are imported by the low speed data interface, data are moved from dual port RAM in the coprocessor key control unit by innernal CPU, in like manner operation result is also moved in the dual port RAM by innernal CPU, only need write-in block number → parameter → order successively, send pending data to the coprocessor key control unit again and get final product.
8. Hach coprocessor as claimed in claim 1, it is characterized in that the following all kinds of instructions of this coprocessor support: the selection of data inlet, mode of operation selection, algorithm selection, encryption and decryption selection, encryption and decryption model selection, key length selection and Hash length are selected.
9. Hach association processing method for realizing that data encrypting and deciphering computing and signature verification design, be used for Hach coprocessor as claimed in claim 1, it is characterized in that supporting the multiple calculation function combination of block cipher computing and Hash operation, step is as follows:
(1) outsidely sends out piece number, parameter, pending data and order, order is resolved and analysis result is sent into the coprocessor key control unit;
(2) if pending data are advanced from the low speed data interface, change (3),, then forward (8) to if pending data are advanced from high speed interface;
(3) the coprocessor key control unit is judged as is singly done grouping, forwards (4) to, singly does Hash, forwards (5) to, and Hach is done simultaneously, forwards (6) to, and grouping back Hash forwards (7) to earlier;
(4) receive data that innernal CPU sends here in Inda, send enable signal to the grouping arithmetic element; Wait for that the output result was sent to dual port RAM by innernal CPU, reads for the outside, all handles up to data when grouping arithmetic element done signal was effective;
(5) receive the data that innernal CPU is sent here, send among the inside FIFO3 of porch, Hash operation unit, and send enable signal to the Hash operation unit; Enable signal is received in the Hash operation unit, according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data; The coprocessor key control unit waits for when the done signal of Hash operation unit is effective that the output result is sent to dual port RAM by innernal CPU, reads for the outside;
(6) receive the data that innernal CPU is sent here,, data are delivered among Inda and the inner FIFO3 simultaneously, and sent enable signal to grouping arithmetic element and Hash operation unit when FIFO3 is non-when full; When detection grouping arithmetic element done signal was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside, all handles up to data; Detect Hash operation unit done signal simultaneously when effective, the output result is sent to dual port RAM by innernal CPU, reads for the outside;
(7) receive data that innernal CPU sends here in Inda, send enable signal, also send enable signal simultaneously to the Hash operation unit to the grouping arithmetic element; Wait for that the result was sent to dual port RAM by innernal CPU, reads for the outside, all handles up to data when grouping arithmetic element done signal was effective; Then the result is moved among the inside FIFO3 of porch, Hash operation unit, handle, wait for that when Hash operation unit done signal was effective, the output result was sent to dual port RAM by innernal CPU, reads for the outside for the Hash operation unit;
(8) the coprocessor key control unit is judged as is singly done grouping, forwards (9) to, singly does Hash, forwards (10) to, and Hach is done simultaneously, forwards (11) to, and grouping back Hash forwards (12) to earlier;
(9) from FIFO1, receive data in Inda; Send enable signal to the grouping arithmetic element; Wait for when grouping arithmetic element done signal is effective, output results among the output FIFO2, read, all handle up to data for the high speed interface outside;
(10) from FIFO1, receive data, send among the inside FIFO3 of Hash porch, and send enable signal to the Hash operation unit; The Hash operation unit according to piece numerical control system internally among the FIFO3 peek carry out computing, all handle up to data; The coprocessor key control unit is waited for when the done signal of Hash operation unit is effective, outputs results among the output FIFO2, reads for the high speed interface outside;
(11) from FIFO1, receive data,, data are delivered among Inda and the inner FIFO3 simultaneously when inner FIFO3 is non-when full; Send enable signal to grouping arithmetic element and Hash operation unit; When detection grouping arithmetic element done signal is effective, output results to output FIFO2, read, all handle up to data for the high speed interface outside; Detect Hash operation unit done signal simultaneously when effective, output results to output FIFO2, read for the high speed interface outside;
(12) receive data to Inda from FIFO1; Send enable signal to the grouping arithmetic element, also send enable signal simultaneously to the Hash operation unit; Wait for when grouping arithmetic element done signal is effective, the result is outputed to FIFO2, read for the high speed interface outside, the result also is shifted among the inside FIFO3 of porch, Hash operation unit then, handle for the Hash operation unit, all handle, wait for when Hash operation unit done signal is effective up to data, output results to output FIFO2, read for the high speed interface outside.
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| CN2006101649700A CN101202628B (en) | 2006-12-11 | 2006-12-11 | Method for realizing of Hach coprocessor |
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| CN2006101649700A CN101202628B (en) | 2006-12-11 | 2006-12-11 | Method for realizing of Hach coprocessor |
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| CN101202628A CN101202628A (en) | 2008-06-18 |
| CN101202628B true CN101202628B (en) | 2010-10-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102262608A (en) * | 2011-07-28 | 2011-11-30 | 中国人民解放军国防科学技术大学 | Method and device for controlling read-write operation of processor core-based coprocessor |
| CN103874060B (en) * | 2012-12-13 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | The method for encryption/decryption and device of data |
| CN109687954B (en) * | 2018-12-25 | 2022-05-13 | 贵州华芯通半导体技术有限公司 | Method and apparatus for algorithm acceleration |
| CN112214795B (en) * | 2020-10-13 | 2022-08-16 | 天津津航计算技术研究所 | Encryption module suitable for various data bandwidths |
| CN114584315B (en) * | 2022-02-24 | 2024-04-02 | 武汉天喻信息产业股份有限公司 | Block chain all-in-one machine, working method and construction method |
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