CN101202306A - Thin film transistor substrate and its producing method - Google Patents
Thin film transistor substrate and its producing method Download PDFInfo
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- CN101202306A CN101202306A CNA2006101575567A CN200610157556A CN101202306A CN 101202306 A CN101202306 A CN 101202306A CN A2006101575567 A CNA2006101575567 A CN A2006101575567A CN 200610157556 A CN200610157556 A CN 200610157556A CN 101202306 A CN101202306 A CN 101202306A
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Abstract
The invention discloses a thin film transistor substrate, comprising a glass basement, a gate which is arranged on the glass basement, a gate insulating layer which covers the glass basement which is provided with the gate; corresponding to the gate, an amorphous silicon layer, an ohmic contact layer, a source electrode and a drain electrode are sequentially arranged on the gate insulating layer in a laminating way. The source electrode and the drain electrode are arranged on the ohmic contact layer and contact the ohmic contact layer to guide and connect electric signal; wherein, the ohmic contact layer comprises a high doping polysilicon layer. The thin film transistor substrate of the invention has low loss to the electric signal. The invention also includes a manufacturing method of the thin film transistor substrate.
Description
Technical field
The invention relates to a kind of thin film transistor base plate and manufacture method thereof.
Background technology
At present, LCD replaces conventional cathode ray tube (the Cathode Ray Tube that is used for computer gradually, CRT) display, and, because characteristics such as the liquid crystal display utensil is light, thin, little, make its be fit to very much be applied in desktop PC, laptop computer, personal digital assistant (Personal Digital Assistant, PDA), in portable phone, TV and multiple office automation and the audio-visual equipment.Liquid crystal panel is its main element, its generally comprise a thin film transistor base plate, a colored filter substrate and be sandwiched in this thin film transistor base plate and this colored filter substrate between liquid crystal layer.
Seeing also Fig. 1, is a kind of generalized section of prior art thin film transistor base plate.This thin film transistor base plate 100 comprises a substrate of glass 101, one is positioned at the grid 102 on the substrate of glass 101, one is positioned at the gate insulator 103 on this grid 102 and this substrate of glass 101, stacked amorphous silicon layer 104 and the highly doped amorphous silicon layer 105 that is arranged on this gate insulator 103, be positioned at an one source pole 106 and a drain electrode 107 on this highly doped amorphous silicon layer 105 and this gate insulator 103, one is positioned at this gate insulator 103, passivation layer 108 and in this source electrode 106 and this drain electrode 107 is positioned at the pixel electrode 109 on this passivation layer 108, and this pixel electrode 109 conducts with this drain electrode 107.
When the grid 102 of this thin film transistor base plate 100 loads the signal of telecommunication, be carried in the signal of telecommunication of this source electrode 106, by these highly doped amorphous silicon layer 105 inputs, by this amorphous silicon layer 104 as passage, transfer to this drain electrode 107 through this highly doped amorphous silicon layer 105 again, further import this pixel electrode 109.
The highly doped amorphous silicon layer 105 of this thin film transistor base plate 100 contacts with this drain electrode 107 with this source electrode 106, again by this amorphous silicon layer 104 as passage, the signal of telecommunication of source electrode 106 is transferred to this drain electrode 107.But, because this highly doped amorphous silicon layer 105 and nonmetal, and the material of this source electrode 106 and this drain electrode 107 is a metal material, thereby, the contact resistance that exists between this source electrode 106 and this drain electrode 107 and this highly doped amorphous silicon layer 105 will loss be transmitted in the signal of telecommunication between this source electrode 106 and this drain electrode 107, makes that the loss of 100 pairs of signals of telecommunication of this thin film transistor base plate is big.
Summary of the invention
In order to solve above-mentioned this thin film transistor base plate problem big, provide the low thin film transistor base plate of a kind of signal of telecommunication loss real for essential to signal of telecommunication loss.
In order to solve above-mentioned this thin film transistor base plate problem big, provide the low manufacturing method of film transistor base plate of a kind of signal of telecommunication loss real for essential to signal of telecommunication loss.
A kind of thin film transistor base plate, it comprises a substrate of glass, one is arranged on the grid of this substrate of glass, one covers the gate insulator of the substrate of glass with this grid, to should grid, and a stacked in regular turn amorphous silicon layer and an ohmic contact layer that is arranged on this gate insulator, an one source pole and a drain electrode, this source electrode and drain electrode are arranged on this ohmic contact layer, and contact with transmission of electric signals with this ohmic contact layer, and this ohmic contact layer comprises a highly doped polysilicon layer.
A kind of manufacturing method of film transistor base plate, it comprises: a substrate of glass is provided; In one mask manufacture process, form a grid in this substrate of glass; In one mask manufacture process, form a gate insulator, an amorphous silicon layer and an ohmic contact layer in regular turn on this substrate of glass, this ohmic contact layer comprises a highly doped polysilicon layer; In one mask manufacture process, form an one source pole and a drain electrode, this source electrode and this drain electrode are arranged on this highly doped polysilicon layer, and contact with transmission of electric signals with this ohmic contact layer should grid.
Compared to prior art, thin film transistor base plate of the present invention, it has a highly doped polysilicon layer and directly contacts to connect the signal of telecommunication as ohmic contact layer and this source electrode and this drain electrode, again by this amorphous silicon layer as the channel layer of transmission signals to transmit this signal of telecommunication.Because the migration rate of the charge carrier of this highly doped polysilicon layer is bigger, the charge carrier of this highly doped polysilicon layer easily passes the potential barrier between this source electrode and this drain electrode and this highly doped polysilicon, then have good Ohmic contact between this source electrode and this drain electrode and this highly doped polysilicon layer, thereby make this thin-film transistor base low the loss of the signal of telecommunication.
Compared to prior art, manufacturing method of film transistor base plate of the present invention, in one mask manufacture process, form a highly doped polysilicon layer and directly contact to connect the signal of telecommunication with this source electrode and this drain electrode, again by the amorphous silicon layer that contacts with this highly doped polysilicon layer as channel layer with transmission of electric signals.Because the migration rate of the charge carrier of this highly doped polysilicon layer is bigger, the charge carrier of this highly doped polysilicon layer easily passes the potential barrier between this source electrode and this drain electrode and this highly doped polysilicon, then have good Ohmic contact between this source electrode and this drain electrode and this highly doped polysilicon layer, thereby make this thin film transistor base plate low the loss of the signal of telecommunication.
Description of drawings
Fig. 1 is a kind of generalized section of prior art thin film transistor base plate.
Fig. 2 is the generalized section of thin film transistor base plate first execution mode of the present invention.
Fig. 3 is the manufacturing flow chart of thin film transistor base plate shown in Figure 2.
Fig. 4 is the schematic diagram that forms the gate metal layer of thin film transistor base plate shown in Figure 2.
Fig. 5 is the schematic diagram that forms the grid of thin film transistor base plate shown in Figure 2.
Fig. 6 is the schematic diagram that forms gate insulator, amorphous silicon membrane and the highly doped amorphous silicon layer film of thin film transistor base plate shown in Figure 2.
Fig. 7 is the schematic diagram that forms the highly doped polysilicon film of thin film transistor base plate shown in Figure 2.
Fig. 8 forms the amorphous silicon layer of thin film transistor base plate shown in Figure 2 and the schematic diagram of highly doped polysilicon layer.
Fig. 9 is the schematic diagram that forms the source/drain metal layer of thin film transistor base plate shown in Figure 2.
Figure 10 forms the source/drain of thin film transistor base plate shown in Figure 2 and the schematic diagram of groove.
Figure 11 is the schematic diagram that forms the passivation layer of thin film transistor base plate shown in Figure 2.
Figure 12 is the schematic diagram that forms the passivation layer pattern of thin film transistor base plate shown in Figure 2.
Figure 13 is the schematic diagram that forms the conductor layer of thin film transistor base plate shown in Figure 2.
Figure 14 is the schematic diagram that forms the pixel electrode of thin film transistor base plate shown in Figure 2.
Figure 15 is the structural representation of thin film transistor base plate second execution mode of the present invention.
Figure 16 is the schematic diagram that forms gate insulator, amorphous silicon membrane, highly doped amorphous silicon layer film and the metallic film of thin film transistor base plate shown in Figure 15.
Figure 17 forms the highly doped polysilicon film of thin film transistor base plate shown in Figure 15 and the schematic diagram of metal silicide film.
Figure 18 is the schematic diagram that forms amorphous silicon layer, highly doped polysilicon layer and the metal silicide layer of thin film transistor base plate shown in Figure 15.
Embodiment
Seeing also Fig. 2, is the generalized section of thin film transistor base plate first execution mode of the present invention.This thin film transistor base plate 200 comprises a substrate of glass 210, one is positioned at the grid 220 on the substrate of glass 210, one is positioned at the gate insulator 230 on this grid 220 and this substrate of glass 210, be layered in amorphous silicon (a-Si) layer 240 and highly doped polysilicon (poly-Si) layer 250 on this gate insulator 230 in regular turn, one is positioned at the source electrode 270 and drain electrode 280 on this highly doped polysilicon layer 250 and this gate insulator 230, one is positioned at this gate insulator 230, passivation layer 208 and in this source electrode 270 and this drain electrode 280 is positioned at the pixel electrode 290 on this passivation layer 208.This amorphous silicon layer 240 is as the channel layer of the transmission of electric signals of this thin film transistor base plate 200; This highly doped polysilicon layer 250 contacts with this drain electrode 280 to connect the signal of telecommunication as an ohmic contact layer and this source electrode 270, and it can be divided into two contact zones that disconnect each other (not indicating), and this two contact zone is electrically connected with this source electrode 270 and this drain electrode 280 respectively.This pixel electrode 290 can drain with this and 280 conduct.
When the grid 220 of this thin film transistor base plate 200 loads the signal of telecommunication, be carried in the signal of telecommunication of this source electrode 270, by 250 pairs on this highly doped polysilicon layer should source electrode 270 the contact zone input, transmit as channel layer by this amorphous silicon layer 240, transfer to this drain electrode 280 through should drain 280 contact zone of 250 pairs on this highly doped polysilicon layer again, further import this pixel electrode 290.
Compared to prior art, the source electrode 270 of thin film transistor base plate 200 of the present invention contact with two contact zones of this highly doped polysilicon layer 250 respectively with drain electrode 280 and imports the signal of telecommunication, again the amorphous silicon layer 240 by this two contact zone of connection as the channel layer of this thin film transistor base plate 200 with transmission of electric signals; Because the carrier mobility of this highly doped polysilicon layer 250 is big, then the charge carrier of this highly doped polysilicon layer 250 easily passes the potential barrier between this source electrode 270 and this drain electrode 280 and this highly doped polysilicon layer 250, makes to have good Ohmic contact between this source electrode 270 and this drain electrode 280 and this highly doped polysilicon layer 250.Thereby, when opening the signal of telecommunication as grid 220 loadings of this thin film transistor base plate 200 of channel layer with amorphous silicon layer 240, the signal of telecommunication that is carried in this source electrode 270 transfers to this drain electrode 280 by this source electrode 270, because this source electrode 270 and this drain electrode 280 have good Ohmic contact with this highly doped polysilicon layer 250, the loss of 200 pairs of signals of telecommunication of this thin film transistor base plate will be reduced.In addition, because the carrier mobility of this highly doped polysilicon layer 250 is bigger,, can make the loss of 200 pairs of signals of telecommunication of this thin film transistor base plate low so the resistance of this highly doped polysilicon layer 250 is less.
Please consulting Fig. 3 again, is the manufacturing flow chart of thin film transistor base plate 200 shown in Figure 2.This manufacture method is used five road mask manufacture processes, and it may further comprise the steps:
One, the first road mask
Step S1: form gate metal layer;
See also Fig. 4, a substrate of glass 210 is provided, on this substrate of glass 210, form a gate metal layer 201 and one first photoresist layer (figure does not show) in regular turn.
Step S2: form grid;
Please consult Fig. 5 again, with the pattern of first mask this first photoresist layer is carried out exposure imaging, thereby form a predetermined pattern; This gate metal layer 201 is carried out etching, and then form a grid 220, remove first photoresist layer.
Two, the second road mask
Step S3: form gate insulator, amorphous silicon membrane and highly doped amorphous silicon layer film;
Please consult Fig. 6 again, on substrate of glass 210, deposit a gate insulator 230, an amorphous silicon membrane 202 and a highly doped amorphous silicon layer film 203 in regular turn with this grid 220.The material of this gate insulator 230 is generally silicon nitride, and its thickness is 300nm, and the thickness 1500nm of this amorphous silicon membrane 202, the thickness of this highly doped amorphous silicon layer film 203 are 500nm.
Step S4: form the highly doped polysilicon film;
Please consult Fig. 7 again, this highly doped amorphous silicon layer film 203 is implemented excimer laser crystallisation (Excimer Laser Re-crystallization) again, promptly use this this highly doped amorphous silicon layer film 203 of excimer laser scanning, make this highly doped amorphous silicon layer film 203 recrystallize into highly doped polysilicon film 204.The pulse frequency of this excimer laser is 300Hz, and pulse duration is less than 25ns, and energy density is less than 250mJ/cm2.
Step S5: form amorphous silicon layer and highly doped polysilicon layer;
Please consult Fig. 8 again, deposition one second photoresist layer (figure does not show) carries out exposure imaging with the pattern of second mask to this second photoresist layer, thereby forms a predetermined pattern on this highly doped polysilicon film 204; This amorphous silicon membrane 202 and this highly doped polysilicon film 204 are carried out etching, and then form the amorphous silicon layer 240 and the highly doped polysilicon layer 250 of patterning, remove second photoresist layer.
Three, the 3rd road mask
Step S6: formation source/drain metal layer;
Please consult Fig. 9 again, on this gate insulator 230 and this highly doped polysilicon layer 250, form one source/drain metal layer 205 and one the 3rd photoresist layer (figure does not show).
Step S7: form source/drain and groove;
Pattern with the 3rd mask carries out exposure imaging to the 3rd photoresist layer, thereby forms a predetermined pattern; Please consult Figure 10 again, this source/drain metal layer 205 is carried out etching, and then form an one source pole 270 and a drain electrode 280.Continue to implement passage etching dorsad, this highly doped polysilicon layer 250 of etching, and cross a part that is etched to this amorphous silicon layer 240, form a groove 206, this groove 206 makes this highly doped polysilicon layer 250 be divided into two contact zones that disconnect each other (not indicating), and make this amorphous silicon layer 240 become the channel layer of the transmission of electric signals of this thin film transistor base plate 200, remove the 3rd photoresist layer.
Four, the 4th road mask
Step S8: form passivation layer;
Please consult Figure 11 again, deposition one passivation layer 208 and one the 4th photoresist layer on the substrate of glass 210 of this gate insulator 230, this source electrode 270 and this drain electrode 280 (figure does not show).
Step S9: form passivation layer pattern;
Please consult Figure 12 again, with the pattern of the 4th mask the 4th photoresist layer is carried out exposure imaging, thereby form a predetermined pattern; This passivation layer is carried out etching, and then define the passivation layer 208 of a patterning, remove the 4th photoresist layer.
Five, the 5th road mask
Step S10: form a conductor layer;
Please consult Figure 13 again, on the passivation layer 208 of this patterning, form a conductor layer 209 and one the 5th photoresist layer (figure does not show).
Step S11: form pixel electrode;
Please consult Figure 14 again, with the pattern of the 5th mask the 5th photoresist layer is carried out exposure imaging, thereby form a predetermined pattern; This conductor layer 209 is carried out etching, and then define a conductor layer pattern, promptly pixel electrode 290, remove the 5th photoresist layer.
Compared to prior art, because this highly doped polysilicon layer 250 has big charge carrier diffusivity, make that the resistance of this highly doped polysilicon layer 250 itself is less, also make between this highly doped polysilicon layer 250 and this source electrode 270 and this drain electrode 280 and have good Ohmic contact, but the signal of telecommunication of this source electrode 270 of less loss and the transmission between 280 that should drain, thereby thin film transistor base plate 200 manufacturing process of the present invention do not increase the mask manufacture process, in the second road mask manufacture process, this highly doped amorphous silicon layer film 203 is implemented excimer laser, make this highly doped amorphous silicon layer film 203 again crystallization form this highly doped polysilicon film 204, further form two contact zones of this highly doped polysilicon layer 250, this two contact zone and this source electrode 270 and this drain electrode 280 have good Ohmic contact to connect the signal of telecommunication, again by the channel layer of this amorphous silicon layer 240, to transmit this signal of telecommunication as this thin film transistor base plate 200; Thereby reduce with of the loss of this amorphous silicon layer 240 as 200 pairs of signals of telecommunication of thin film transistor base plate of channel layer.
Please consulting Figure 15 again, is the structural representation of thin film transistor base plate second execution mode of the present invention.This thin film transistor base plate 300 than the thin film transistor base plate of first execution mode different be in: comprise this metal silicide layer 360 and this highly doped polysilicon layer 350 with the ohmic contact layer that this source electrode 370 contacts with this drain electrode 380, a metal silicide layer 360 promptly further be set between this highly doped polysilicon layer 350 and this source electrode 370 and this drain electrode 380.The material of this metal silicide layer 360 generally is one of titanizing silicon alloy (TiSi), cobalt silicon alloy (CoSi2) and nickel silicon alloy (NiSi).
Second execution mode of thin film transistor base plate of the present invention is than its first execution mode, this metal silicide layer 360 is electrically connected to connect the signal of telecommunication of this source electrode 370 and this drain electrode 380 with this source electrode 370 and this drain electrode 380, because this metal silicide layer 360 is bigger than the charge carrier diffusivity of this highly doped polysilicon layer 350, when contacting with this drain electrode 380 with this source electrode 370, have better ohmic contact, thereby further reduce with the loss of amorphous silicon layer as 300 pairs of signals of telecommunication of thin film transistor base plate of channel layer.
Compared to the manufacture process of this thin film transistor base plate first execution mode, make this thin film transistor base plate 300 different be in:
In the second road mask manufacture process that forms this highly doped polysilicon layer 350:
At first, form gate insulator, amorphous silicon membrane, highly doped amorphous silicon layer film and metallic film;
Please consult Figure 16 again, on substrate of glass 310, deposit a gate insulator 330, an amorphous silicon membrane 302, one highly doped amorphous silicon layer film 303 and a metallic film 361 in regular turn with this grid 320.The material of this gate insulator 330 is generally silicon nitride, its thickness is 300nm, the thickness 1500nm of this amorphous silicon membrane 302, the thickness of this highly doped amorphous silicon layer film 303 is 500nm, the thickness of this metallic film 361 is 1～5nm, and its material generally is one of titanium (Ti), cobalt (Co) and nickel (Ni).
Then, form highly doped polysilicon film and metal silicide film;
Please consult Figure 17 again, this highly doped amorphous silicon layer film 303 is implemented excimer laser crystallisation again, promptly use this excimer laser to scan this metallic film 361, make this highly doped amorphous silicon layer film 303 recrystallize into a highly doped polysilicon film 304; Owing to will produce a large amount of heat energy when crystallization forms this highly doped polysilicon film 304 again, make this metallic film 361 and a part of highly doped polysilicon film 304 of its below form this metal silicide film 362, the thickness of this metal silicide film 362 is bigger than this metallic film 361.The pulse frequency of this excimer laser is 300Hz, and pulse duration is less than 25ns, and energy density is less than 250mJ/cm2.
At last, form amorphous silicon layer, highly doped polysilicon layer and metal silicide layer;
Please consult Figure 18 again, deposition one photoresist layer (figure does not show) carries out exposure imaging with the pattern of a mask to this photoresist layer, thereby forms a predetermined pattern on this metal silicide film 362; This amorphous silicon membrane 302, this highly doped polysilicon film 304 and this metal silicide film 362 are carried out etching, and then form amorphous silicon layer 340, highly doped polysilicon layer 350 and the metal silicide layer 360 of patterning, remove second photoresist layer.
Manufacture process compared to thin film transistor base plate first execution mode of the present invention, the manufacture process of this thin film transistor base plate second execution mode, only need further to deposit a metallic film 361 on this highly doped amorphous silicon layer film 303, produce the bigger metal silicide film 362 of this highly doped polysilicon film 304 and charge carrier migration rate, thereby can further reduce with the loss of amorphous silicon layer as 300 pairs of signals of telecommunication of thin film transistor base plate of channel layer.In addition, this metal silicide film 362 forms synchronously with forming this highly doped polysilicon film 304, only utilizes the heat of implementing to produce when the excimer laser crystallization method forms this highly doped polysilicon film 304 to make this metal silicide film 362.Thereby the manufacture process of this thin film transistor base plate second execution mode need not increase the making flow process can realize better effect.
Claims (10)
1. thin film transistor base plate, it comprise gate insulator that a substrate of glass, is arranged on the grid of this substrate of glass, and covers the substrate of glass with this grid, to should grid, a stacked amorphous silicon layer and an ohmic contact layer, one source pole and a drain electrode that is arranged on this gate insulator in regular turn; This source electrode and drain electrode are arranged on this ohmic contact layer, and contact to connect the signal of telecommunication with this ohmic contact layer, it is characterized in that: this ohmic contact layer comprises a highly doped polysilicon layer.
2. thin film transistor base plate as claimed in claim 1, it is characterized in that: the number of plies of this ohmic contact layer is two-layer, be respectively a highly doped polysilicon layer and a metal silicide layer, this metal silicide layer is arranged between this highly doped polysilicon layer and this source electrode and the drain electrode, with transmission of electric signals.
3. thin film transistor base plate as claimed in claim 2 is characterized in that: the material of this metal silicide layer is one of titanizing silicon alloy, cobalt silicon alloy and nickel silicon alloy.
4. manufacturing method of film transistor base plate, it may further comprise the steps: a substrate of glass is provided; In one mask manufacture process, form a grid in this substrate of glass; In one mask manufacture process, form a gate insulator, an amorphous silicon layer and an ohmic contact layer in regular turn on this substrate of glass; In one mask manufacture process, form an one source pole and a drain electrode, this source electrode and this drain electrode are arranged on this ohmic contact layer to should grid, and this ohmic contact layer contacts to connect the signal of telecommunication with this drain electrode with this source electrode, it is characterized in that: this ohmic contact layer comprises a highly doped polysilicon layer.
5. manufacturing method of film transistor base plate as claimed in claim 4, it is characterized in that: make the mask manufacture process of this ohmic contact layer, comprise that further depositing a gate insulator, an amorphous silicon membrane and a highly doped amorphous silicon layer film in regular turn has the substrate of glass of this grid.
6. manufacturing method of film transistor base plate as claimed in claim 5 is characterized in that: use this highly doped amorphous silicon layer film of excimer laser scanning, make this highly doped amorphous silicon layer film recrystallize into the highly doped polysilicon film.
7. manufacturing method of film transistor base plate as claimed in claim 4, it is characterized in that: the number of plies of this ohmic contact layer is two layers, be respectively a highly doped polysilicon layer and a metal silicide layer, make the mask manufacture process of this ohmic contact layer, comprise that further depositing a gate insulator, an amorphous silicon membrane, a highly doped amorphous silicon layer film and a metallic film in regular turn has the substrate of glass of this grid.
8. manufacturing method of film transistor base plate as claimed in claim 7 is characterized in that: use excimer laser to scan this metallic film, when this highly doped amorphous silicon layer film recrystallizes into the highly doped polysilicon film, form this metal silicide film.
9. as claim 5 or 7 described manufacturing method of film transistor base plate, it is characterized in that: the thickness 1500nm of this amorphous silicon membrane, the thickness of this highly doped amorphous silicon layer film are 500nm.
10. as claim 6 or 8 described manufacturing method of film transistor base plate, it is characterized in that: the pulse frequency of this excimer laser is 300Hz, and pulse duration is less than 25ns, and energy density is less than 250mJ/cm2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200610157556A CN101202306B (en) | 2006-12-15 | 2006-12-15 | Thin film transistor substrate producing method |
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| CN200610157556A CN101202306B (en) | 2006-12-15 | 2006-12-15 | Thin film transistor substrate producing method |
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| CN101202306A true CN101202306A (en) | 2008-06-18 |
| CN101202306B CN101202306B (en) | 2010-05-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012122790A1 (en) * | 2011-03-17 | 2012-09-20 | 复旦大学 | Metal-semiconductor compound thin-film and dram memory cell and manufacturing method therefor |
| CN107093633A (en) * | 2017-04-21 | 2017-08-25 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte, display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913113A (en) * | 1997-02-24 | 1999-06-15 | Lg Electronics Inc. | Method for fabricating a thin film transistor of a liquid crystal display device |
| CN1324665C (en) * | 2004-03-29 | 2007-07-04 | 广辉电子股份有限公司 | Method for making self-alignment type thin-film transistor |
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2006
- 2006-12-15 CN CN200610157556A patent/CN101202306B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012122790A1 (en) * | 2011-03-17 | 2012-09-20 | 复旦大学 | Metal-semiconductor compound thin-film and dram memory cell and manufacturing method therefor |
| CN107093633A (en) * | 2017-04-21 | 2017-08-25 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte, display device |
| CN107093633B (en) * | 2017-04-21 | 2020-04-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
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| CN101202306B (en) | 2010-05-26 |
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