CN101197392A - Semiconductor device and manufacturing method thereof, and contact etching stop layer - Google Patents
Semiconductor device and manufacturing method thereof, and contact etching stop layer Download PDFInfo
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- CN101197392A CN101197392A CNA2006101191482A CN200610119148A CN101197392A CN 101197392 A CN101197392 A CN 101197392A CN A2006101191482 A CNA2006101191482 A CN A2006101191482A CN 200610119148 A CN200610119148 A CN 200610119148A CN 101197392 A CN101197392 A CN 101197392A
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Abstract
The invention discloses a semiconductor device and a method for manufacturing the same and a contact etching stop layer, wherein the device comprises a substrate, at least one grid electrode and a source/drain region formed on the substrate, and the contact etching stop layer consisting of a multi-layer structure; the contact etching stop layer comprises a first contact etching stop layer formed on the substrate, the grid electrode and the source/drain region, an isolation layer formed on the first contact etching stop layer and a second contact etching stop layer formed on the isolation layer. The semiconductor device can effectively reduce the damage on the device caused by plasma during manufacturing the device and further increases the stress in the channel of the device; meanwhile, the invention increases the mobility of carrier more effectively, thereby improving the electrical property of the device. The manufacturing method, which is simple and feasible and convenient for operation, does not need to adopt additional processing steps and has little influence on production cycle.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor device and manufacture method and contact etching stop layer.
Background technology
Along with the manufacturing of integrated circuit to very lagre scale integrated circuit (VLSIC) (ULSI) development, its inner current densities is increasing, device size is more and more littler, service speed is more and more faster, improves that the drive current of device becomes more and more important in the circuit.A plurality of parameters such as the drive current of circuit and the grid length of device, grid capacitance and mobility of charge carrier rate are closely related, shorten grid length, increase grid capacitance or improve the drive current that the mobility of charge carrier rate can be improved device effectively.Wherein, under the situation that does not change grid structure, often utilize stress engineering to apply certain stress,, improve the drive current of device to improve the mobility of charge carrier rate in the raceway groove to the raceway groove of device.Enter 65nm technology node, because the method for traditional raising device drive current has been subjected to many restrictions, the drive current that improves device by stress engineering has become the actual industrial standard of semiconductor industry.
So-called stress engineering is meant, in the device forming process, can introduce the material layer of stress in the device surface growth, can reach the purpose of improving device property.Now confirm, can improve the mobility in hole, can be used for improving the performance of PMOS device along the compression (compressive strain) of channel direction; And can improve the mobility of electronics along the tensile stress (tensile strain) of channel direction, can be used for improving the performance of nmos device.For the carrier mobility in the raceway groove is had tangible improvement, the material layer of this introducing stress should be formed at the surface near raceway groove, usually can utilize on device and to form contact etching stop layer (CESL, Contact Etch Stop Layer) and realize with stress.
Fig. 1 is existing device architecture schematic diagram with contact etching stop layer of introducing stress, as shown in Figure 1, on silicon substrate 101, formed a device architecture, this device has a polysilicon gate 104, this grid below is pad silicon oxide layer 103 (Pad Oxide), formed gate lateral wall layer 105 on gate lateral wall, it can form the good protection to polysilicon gate; In addition, in the grid both sides of each device, be mask with grid structure and side wall layer, between grid, formed source/ drain doping region 107 and 108 in the mode of injecting with ion on the substrate.After this layer device forms, in order to realize the isolation between itself and last layer device, need grow contact etching stop layer 110 and interlayer dielectric layer (not shown) thereon.At this moment, in order to strengthen the carrier mobility of this device, improve device electrical performance, the contact etching stop layer 110 that is connected with device can be grown to the stressor layers with certain stress, the process conditions when stress kind that this layer had and big I deposit by regulating it realize.Usually,, can deposit the contact etching stop layer that one deck has compression, to improve the mobility in hole for the PMOS device; For nmos device, then can deposit the contact etching stop layer that one deck has tensile stress, to improve the mobility of electronics, finally reach the purpose of improving device electrical performance.Wherein, within the specific limits, the stress intensity that this contact etching stop layer can be introduced can increase along with the increase of its layer thickness.
But, the problem that has two aspects in the making of above-mentioned existing CESL with stress, the one,, this layer is used to introduce the CESL of stress normally by plasma enhanced chemical vapor deposition (PECVD, Plasma enhanced chemical vapor deposition) method forms, in its deposition forming process, can produce a large amount of plasmas, and since this CESL layer very near device, the plasma cognition that produces in its forming process causes damage to device, when serious, to cause device reliability relatively poor, and make grid leakage current obviously increase; The 2nd,, after this layer CESL thickness acquires a certain degree (after being generally 100nm), the stress intensity that this layer introduced can be not again have obvious variation with the increase of its thickness, but is tending towards saturated.As seen, existing individual layer CESL manufacture method can cause plasma damage to device, and its stress that can introduce is limited, and therefore, existing individual layer CESL with stress also is limited to the improvement of device electrical performance.
Application number is that 200310121332.7 Chinese patent application discloses a kind of structure of introducing stress, and this structure is to utilize the side wall layer of grid (spacer) that raceway groove is introduced stress, but this stress structure exists the limited problem of above-mentioned introducing stress intensity equally.Wherein, because the thickness of gate lateral wall layer directly relates to size of devices, its thickness can not at will be changed, it is infeasible to utilize bed thickness to adjust stress intensity itself, in addition, what the method for its this side wall layer of growing adopted is high density plasma chemical vapor deposition (HDP, High density plasma chemical vapor deposition) method, exists plasma device to be caused the problem of damage equally.
Summary of the invention
The invention provides a kind of semiconductor device and manufacture method thereof, the contact etching stop layer of using in this device, can reduce or avoid the damage of plasma, and improve the limited problem of stress that existing contact etching stop layer is introduced in device channel device.
A kind of semiconductor device provided by the invention comprises: substrate, at least one grid and the source/drain region that form on described substrate; Wherein, also comprise: first contact etching stop layer that on described substrate and described grid, source/drain region, forms; The separator that on described first contact etching stop layer, forms; Second contact etching stop layer that on described separator, forms.
Wherein, described separator is unadulterated silicon layer, and the thickness of described separator is 30 to 100
Between.
Wherein, when described source/drain region was the N type, described first contact etching stop layer and second contact etching stop layer were silicon nitride layer or the silicon oxynitride layer with tensile stress; When described source/drain region was the P type, described first contact etching stop layer and second contact etching stop layer had the silicon nitride layer or the silicon oxynitride layer of compression.
Wherein, the thickness of described first contact etching stop layer and second contact etching stop layer is respectively between 10 to 50nm.
The present invention has the manufacture method of a kind of device of identical or relevant art feature, comprises step:
One substrate is provided, and on described substrate, comprises a grid and source/drain region at least;
On described substrate, form first contact etching stop layer;
On described first etching stop layer, form a separator;
On described separator, form second contact etching stop layer.
Wherein, described separator is unadulterated silicon layer, and the thickness of described separator is 30 to 100
Between.
Wherein, when described source/drain region was the N type, first contact etching stop layer and second contact etching stop layer of formation had tensile stress, and when described source/drain region was the P type, first contact etching stop layer and second contact etching stop layer of formation had compression.
Wherein, described first contact etching stop layer and second contact etching stop layer are silicon nitride layer or silicon oxynitride layer, and described first contact etching stop layer and second contact etching stop layer are to be formed by PECVD or HDP method, and the thickness of formation is between 10 to 50nm.
The present invention has a kind of contact etching stop layer of identical or relevant art feature, comprises first contact etching stop layer, separator that forms on described first contact etching stop layer and second contact etching stop layer that forms on described separator.
Wherein, described separator is unadulterated silicon layer, and the thickness of described separator is 30 to 100
Between.
Wherein, when being applied to nmos device, described first contact etching stop layer and second contact etching stop layer are silicon nitride layer or the silicon oxynitride layer with tensile stress, when being applied to the PMOS device, described first contact etching stop layer and second contact etching stop layer have the silicon nitride layer or the silicon oxynitride layer of compression, and the thickness of described first contact etching stop layer and second contact etching stop layer is respectively between 10 to 50nm.
Compared with prior art, the present invention has the following advantages:
Semiconductor device of the present invention, in the middle of applied contact etching stop layer, increased one deck separator, contact stop layer etching before, this separator has certain conductivity, and the high-energy photon that can absorb plasma generation can effectively reduce the injury of production process ionic medium body to device.Avoided the problem that descends because of device performance that plasma causes the damage of device.
Semiconductor device of the present invention, in the middle of the contact etching stop layer of using, added a separator, this contact etching stop layer is divided for first contact etching stop layer and second contact etching stop layer, increased the number of plies of introducing the structure of stress, the introducing stress of having avoided layer thickness to arrive to a certain degree back appearance is tending towards saturated problem, can further increase the stress that to introduce, more effectively improve the mobility of charge carrier rate, improve the electrical property of device.
Device making method of the present invention has simple possible, easy to operate advantage, and the deposition program during only to the formation contact etching stop layer is adjusted, and need not to increase extra processing step, and is little to the production cycle influence.
Contact etching stop layer of the present invention, the middle separator that adds not only can reduce the plasma damage to device that this contact etching stop layer causes in forming process, and can also be more effectively introduce stress to device because of increasing of its number of plies, improve its degree of improvement to device performance.
Description of drawings
Fig. 1 is existing device architecture schematic diagram with contact etching stop layer of introducing stress;
Fig. 2 is the device architecture schematic diagram with contact etching stop layer of introducing stress of the present invention;
Fig. 3 is for adding the statistics schematic diagram of separator front and back device grid leakage current;
Fig. 4 is the schematic diagram of the corresponding relation of the number of plies, gross thickness and the introducing stress intensity of explanation contact etching stop layer;
Fig. 5 is the flow chart of manufacturing method of semiconductor device of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely applied in many application; and can utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
In the conventional semiconductor device, after forming device, need growth can introduce the contact etching stop layer (CESL) and the interlayer dielectric layer of stress, this two-layer plasma mode (PECVD or HDP) deposition of normally utilizing forms, the a large amount of plasmas that produce in its growth course easily cause plasma damage to device, cause device performance to descend, increase as leakage current.In addition, though stress can increase with the increase of CESL layer thickness, after its thickness acquired a certain degree, it is saturated that its stress of introducing also can be tending towards.Therefore, inevitably can be in the existing individual layer contact etching stop layer manufacturing process because of the plasma damage device that produces, and its stress that can introduce device is limited.
The semiconductor device that the present invention proposes has adopted the contact etching stop layer with sandwich construction, has alleviated the problems referred to above.Fig. 2 is the device architecture schematic diagram with contact etching stop layer of introducing stress of the present invention, as shown in Figure 2, semiconductor device of the present invention, comprise substrate 101, at least one grid 104 and source/drain region (107 and 108) on this substrate, have been formed, and at substrate and grid, first contact etching stop layer (110) with stress that forms on source/drain region, then, the present invention has also formed a separator 201 on this first contact etching stop layer, conductivity that this separator has and high-energy photon absorbability not only can be avoided the damage to device of the plasma that produces in whole contact etching stop layer growth course, can also effectively prevent the damage to device of the plasma introduced in the growth course of interlayer dielectric layer.After contact etching stop layer forms, also need to carry out the growth of interlayer dielectric layer, in order to obtain growth result preferably, this interlayer dielectric layer normally adopts the method deposition of HDP to form, also can produce a large amount of plasmas in its growth course, if there is not separator, these plasmas also will cause damage to device.After forming this separator 201, improve the stress that to introduce for further, and formed second contact etching stop layer 202 thereon with stress.
Fig. 3 is for adding the statistics schematic diagram of separator front and back device grid leakage current, and wherein used separator is unadulterated silicon layer.As shown in Figure 3, what the abscissa among the figure was represented is the logarithm of grid leakage current, and its value is more for a short time to show that grid leakage current is more little; What the ordinate among the figure was represented is statistics probability, the i.e. probability that a certain leakage current occurs in the device detection.Among the figure 301 is the statistics of grid leakage current of the device that do not add silicon layer, 302 statisticses for the device grid leakage current behind the adding silicon layer, as can be seen, when not adding silicon layer, the electric leakage of the grid situation of device is more serious, there is the grid leakage current of more device bigger, and also dispersion of the distribution of grid leakage current, show that the uniformity of device performance is relatively poor; And after adding silicon layer, the electric leakage of the grid situation of device is clearly better, and the grid leakage current of most devices is all very little, and uniformity is also fine.As seen, add the electric leakage of the grid performance that silicon layer can effectively improve device.Reason is, plasma is mainly caused by two aspects to the damage that device brings: on the one hand being because the charging damage that the charged particles that produces in the plasma process causes, is the damage to device of the high-energy photon that produces in the plasma process on the other hand.For the former, because the silicon layer that adds can be used as an interim conductive layer, make the electric charge of plasma generation flow thereon, the distribution meeting uniformity of electric charge on substrate reduced the damage of electric charge to device as a result.For the latter, because the band gap width of silicon materials is 1.1eV, and the wave-length coverage of the high-energy photon of plasma generation at 250nm between the 750nm, the energy that is high-energy photon is between 4.96 to 1.65eV, this just means that high-energy photon can be absorbed through silicon materials the time, thereby has avoided the damage of high-energy photon to device.As seen, the damage that the existence of this separator--silicon layer can avoid plasma process that device is caused effectively, thereby after adding this silicon layer, the electric leakage of the grid situation of device can be significantly improved.
Fig. 4 is the schematic diagram of the corresponding relation of the number of plies, gross thickness and the introducing stress intensity of explanation contact etching stop layer, and the stress material that is adopted among this figure is a silicon nitride material.As shown in Figure 4,401 is the graph of a relation at the stress of the number of plies, gross thickness and the introducing of XX direction, and 402 is the graph of a relation at the stress of the number of plies, gross thickness and the introducing of YY direction.Wherein, abscissa representative be layer thickness, the ordinate representative be stress intensity, and all provided one deck respectively on each direction, three layers and five layers, the curve of three kinds of numbers of plies.No matter can see, still be the YY direction at XX, Zong the stress of generation all is similar to the variation relation of bed thickness: during the same number of plies, stress increases with the increase of gross thickness, but can be tending towards saturated; During the difference number of plies, under the identical situation of gross thickness, the number of plies that increases growth can obviously improve the stress that can introduce.This is to cause because the generation of stress mainly is interface by each layer, after a layer growth is intact, the stress of this laminar surface is released, variation has taken place in its lattice constant, at this moment, when this had discharged on the layer of stress the new layer of material of regrowth, the two can be inequality in lattice constant at the interface, can produce new stress for resisting not matching of this two interlayers lattice constant.Because the summation of the stress that the stress that finally shows is multilayer material to be produced, so the stress that growth nitride multilayer silicon materials can produce is far longer than the stress that the individual layer silicon nitride material can produce.
The first embodiment of the present invention is exactly a kind of enhancement mode nmos device of the multilayer contact etching stop layer with tensile stress of having grown.For the enhancement mode nmos device, its substrate is the P type, and source/leakage doped region is the N type, and during because of its work, the channel current flows of formation is and the electronics of source/leakage doped region homotype that this device is called N channel device or nmos device between the source below the grid, drain electrode.For improving the mobility of the electronics in such device channel, need growth thereon to have the CESL of tensile stress, in the present embodiment, this CESL forms by three layers, first contact etching stop layer that is connected with device, be positioned at middle separator, and be positioned at second contact etching stop layer on the separator.In the present embodiment, first, second contact etching stop layer is a silicon nitride layer, and separator has been selected unadulterated silicon layer for use.
In the present embodiment, the thickness of first contact etching stop layer and second contact etching stop layer can be separately positioned between 10 to 50nm, as 20nm, 30nm or 40nm etc.Can be seen that by Fig. 4 stress, thickness in this thickness range are higher than being, be more excellent span.In addition, the thickness of the silicon layer in the present embodiment does not need too thick, and to avoid increasing the difficulty of back selective removal contact etching stop layer, its optimal value can be arranged on 30 to 100
Between, as be 50
Or 80
Deng.
First, second contact etching stop layer of the used stress introduced is a silicon nitride layer in the present embodiment, in other embodiments of the invention, it can also be formed by silicon oxynitride with certain stress or silica material respectively, as long as its sedimentary condition is regulated, make it have the needed stress of device and get final product.
Used separator is unadulterated silicon layer in the present embodiment; in other embodiments of the invention; this separator can also adopt other materials; as long as this material both can be used as an interim conductive channel, the high-energy photon that can absorb plasma generation again should fall into protection scope of the present invention.
Device in the present embodiment is a nmos device, require used contact etching stop layer material to have tensile stress, in other embodiments of the invention, also contact etching stop layer can be applied in the PMOS device, just the material of the contact etching stop layer of correspondence will be become the material with compression this moment.Utilize the adjustment of process conditions to realize that the change of stress is the known method of those of ordinary skill in the art, do not repeat them here.
The manufacture method of semiconductor device of the present invention, with existing device manufacture method basically identical, just the depositing operation when forming contact etching stop layer is adjusted, implement simple and convenient, little to the influence of production cycle.
The second embodiment of the present invention describes the manufacture method of semiconductor device of the present invention in detail, Fig. 5 is the flow chart of manufacturing method of semiconductor device of the present invention, as shown in Figure 5, before making contact etching stop layer, the method of element manufacturing is identical with process and conventional art, when element manufacturing (S501) after formed grid, source/drain region, the making that enters contact etching stop layer at substrate surface.
On this substrate, form first contact etching stop layer (S502) earlier, this layer is the silicon oxynitride layer that utilizes PECVD method deposition to form in the present embodiment, for nmos device, sedimentary condition to this layer is adjusted, make it that device channel is formed tensile stress, to improve the mobility of electronics in the raceway groove.The optimal value of this layer thickness can be arranged between 10 to 50nm.
After forming first contact etching stop layer, then form a separator (S503) thereon, in the present embodiment, this separator is to utilize the PECVD method, the polysilicon layer that (in situ) on the throne in same chamber forms.Its technology is very simple on realizing, only needs after having deposited first contact etching stop layer reacting gas, the process conditions that feed chamber to be adjusted, and can realize the deposition on the throne of this polysilicon layer.In the present embodiment, the thickness of this polysilicon layer can be arranged on 30 to 100
Between, as be 40
Or 60
Deng.
After forming separator, on this layer, form one second contact etching stop layer (S504) again, in the present embodiment, this layer has adopted silicon nitride material, and it also can utilize PECVD method deposition to form in same chamber, and is same, for nmos device, it is adjusted into thin layer with tensile stress.In the present embodiment, the thickness optimal value of this layer can be arranged between 10 to 50nm.
Then, can carry out the growth (S505) of interlayer dielectric layer, the growth of this layer normally utilizes PECVD or HDP method, but can avoid the separator of plasma damage because of having increased one deck among the present invention, and the plasma that produces when the growth interlayer dielectric layer is damage device again.The element manufacturing step and the prior art of being carried out after this step are basic identical, by those of ordinary skill in the art is known, do not repeat them here.
In the present embodiment, the three-decker of contact etching stop layer all is to utilize the PECVD method to form, only need the deposition program is adjusted, importing different reacting gass can realize in same reaction chamber, operate very simple, production cycle is not had to influence substantially, do not increase the complexity of technology yet.In other embodiments of the invention, for reaching better effect, also can adopt additive method to form this three-decker, as use the HDP method.In addition, this three-decker also can form with different modes respectively, adopts the HDP method to form as first contact etching stop layer, and separator adopts the PECVD method to form, and second contact etching stop layer adopts the HDP method to form again.
In the present embodiment, at the nmos device above-mentioned contact etching stop layer of having grown with sandwich construction of tensile stress, in other embodiments of the invention, the contact etching stop layer of the sandwich construction of also can in the PMOS device, growing with compression.
In the present embodiment, what first contact etching stop layer adopted is silicon oxynitride layer, what second contact etching stop layer adopted is silicon nitride layer, in other embodiments of the invention, this is two-layer can also to adopt other materials, adopt silicon oxide layer as first contact etching stop layer, second contact etching stop layer adopts silicon nitride layer etc.
Be used to introduce bigger stress in the semiconductor device of the present invention, can avoid simultaneously the contact etching stop layer of plasma damage device again, three-decker is arranged, comprise one first contact etching stop layer, a separator that on this first contact etching stop layer, forms and one second contact etching stop layer that on described separator, forms.Wherein, first contact etching stop layer and second contact etching stop layer can be formed by silicon nitride layer or silicon oxynitride layer respectively, and between 10 to 50nm, the thickness of separator is 30 to 100 respectively for the thickness of first contact etching stop layer and second contact etching stop layer
Between.
When this contact etching stop layer is applied to nmos device, be made into to having the sandwich construction of tensile stress, when this contact etching stop layer is applied to the PMOS device, be made into to having the sandwich construction of compression
First contact etching stop layer and second contact etching stop layer in the foregoing description are the single-layer medium layer, in other embodiments of the invention, first and/or second contact etching stop layer also can be made up of the multilayer dielectricity layer, can be as first contact etching stop layer by 1 to 5 layer dielectric layer with certain stress, form as silicon oxynitride layer, second contact etching stop layer also can be made up of or the like as silicon nitride layer 1 to 5 layer the dielectric layer with certain stress.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (20)
1. semiconductor device comprises:
Substrate;
At least one grid and the source/drain region that on described substrate, form;
It is characterized in that, also comprise:
First contact etching stop layer that on described substrate and described grid, source/drain region, forms;
The separator that on described first contact etching stop layer, forms;
Second contact etching stop layer that on described separator, forms.
2. semiconductor device as claimed in claim 1 is characterized in that: described separator is unadulterated silicon layer.
3. semiconductor device as claimed in claim 1 is characterized in that: the thickness of described separator is 30 to 100
Between.
4. semiconductor device as claimed in claim 1 is characterized in that: when described source/drain region was the N type, described first contact etching stop layer and second contact etching stop layer were silicon nitride layer or the silicon oxynitride layer with tensile stress.
5. semiconductor device as claimed in claim 1 is characterized in that: when described source/drain region was the P type, described first contact etching stop layer and second contact etching stop layer had the silicon nitride layer or the silicon oxynitride layer of compression.
6. semiconductor device as claimed in claim 1 is characterized in that: the thickness of described first contact etching stop layer and second contact etching stop layer is respectively between 10 to 50nm.
7. the manufacture method of a device as claimed in claim 1 comprises step:
One substrate is provided, and on described substrate, comprises a grid and source/drain region at least;
On described substrate, form first contact etching stop layer;
On described first etching stop layer, form a separator;
On described separator, form second contact etching stop layer.
8. manufacture method as claimed in claim 7 is characterized in that: described separator is unadulterated silicon layer.
9. manufacture method as claimed in claim 7 is characterized in that: the thickness of described separator is 30 to 100
Between.
10. manufacture method as claimed in claim 7 is characterized in that: when described source/drain region was the N type, first contact etching stop layer and second contact etching stop layer of formation had tensile stress.
11. manufacture method as claimed in claim 7 is characterized in that: when described source/drain region was the P type, first contact etching stop layer and second contact etching stop layer of formation had compression.
12. manufacture method as claimed in claim 7 is characterized in that: described first contact etching stop layer and second contact etching stop layer are silicon nitride layer or silicon oxynitride layer.
13. manufacture method as claimed in claim 7 is characterized in that: described first contact etching stop layer and second contact etching stop layer are to be formed by PECVD or HDP method.
14. manufacture method as claimed in claim 7 is characterized in that: the thickness of described first and second contact etching stop layers of formation is between 10 to 50nm.
15. a contact etching stop layer is characterized in that: comprise first contact etching stop layer, separator that on described first contact etching stop layer, forms and second contact etching stop layer that on described separator, forms.
16. contact etching stop layer as claimed in claim 15 is characterized in that: described separator is unadulterated silicon layer.
17. contact etching stop layer as claimed in claim 15 is characterized in that: the thickness of described separator is 30 to 100
Between.
18. contact etching stop layer as claimed in claim 15 is characterized in that: when being applied to nmos device, described first contact etching stop layer and second contact etching stop layer are silicon nitride layer or the silicon oxynitride layer with tensile stress.
19. contact etching stop layer as claimed in claim 15 is characterized in that: when being applied to the PMOS device, described first contact etching stop layer and second contact etching stop layer have the silicon nitride layer or the silicon oxynitride layer of compression.
20. contact etching stop layer as claimed in claim 15 is characterized in that: the thickness of described first contact etching stop layer and second contact etching stop layer is respectively between 10 to 50nm.
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| CN102024705B (en) * | 2009-09-22 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and method for producing same |
| CN102983174A (en) * | 2012-12-18 | 2013-03-20 | 电子科技大学 | Strained PMOSFET with trough-type structures and fabrication method of strain PMOSFET |
| CN102983174B (en) * | 2012-12-18 | 2016-11-30 | 电子科技大学 | Strain PMOSFET with trench structure and preparation method thereof |
| CN110246759A (en) * | 2019-06-03 | 2019-09-17 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of flush memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024705B (en) * | 2009-09-22 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and method for producing same |
| CN102983174A (en) * | 2012-12-18 | 2013-03-20 | 电子科技大学 | Strained PMOSFET with trough-type structures and fabrication method of strain PMOSFET |
| CN102983174B (en) * | 2012-12-18 | 2016-11-30 | 电子科技大学 | Strain PMOSFET with trench structure and preparation method thereof |
| CN110246759A (en) * | 2019-06-03 | 2019-09-17 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of flush memory device |
| CN110246759B (en) * | 2019-06-03 | 2021-11-02 | 武汉新芯集成电路制造有限公司 | Preparation method of flash memory device |
| CN114497325A (en) * | 2022-01-14 | 2022-05-13 | 武汉大学 | Quantum dot embedded full-color Micro-LED display chip and preparation method thereof |
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| Publication number | Publication date |
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| CN100576566C (en) | 2009-12-30 |
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