CN101197192B - Writing circuit and method for flash memory - Google Patents
Writing circuit and method for flash memory Download PDFInfo
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- CN101197192B CN101197192B CN2006101611402A CN200610161140A CN101197192B CN 101197192 B CN101197192 B CN 101197192B CN 2006101611402 A CN2006101611402 A CN 2006101611402A CN 200610161140 A CN200610161140 A CN 200610161140A CN 101197192 B CN101197192 B CN 101197192B
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Abstract
The invention relates to a write circuit and a write method for a flash memory. The invention utilizes fixed current to write the flash memory so as to adjust threshold voltage of the flash memory. When the write circuit writes the flash memory, the invention utilizes changes of drain voltage of the flash memory to judge whether the threshold voltage of the flash memory reaches the expected magnitude of voltage. Therefore, the invention can accurately adjust the threshold voltage after write and shorten write time.
Description
Technical field
The invention relates to the write circuit of a kind of flash memory (flash memory), and particularly about a kind of write circuit and wiring method with flash memory of floating gate (floating gate).
Background technology
Flash memory has light and handy and nonvolatile characteristic, and the application in therefore installing in action is quite extensive, for example the storage device of mobile phone, MP3 walkman, digital camera etc.And at present in the flash memory most widely used memory element be mainly floating-gate memory (floating gate memory), its similar in the metal-oxide half field effect transistor with floating grid (metal oxide semiconductortransistor, MOS).
In conventional art, the wiring method of floating-gate memory is set a high voltage differential (high voltage potential) usually between its control grid (controlgate) and drain electrode (drain), make electronics become trapped (trap) among floating gate.The threshold voltage of floating-gate memory (thresholdvoltage) then can be mended sunken electron amount and changes along with floating gate.Therefore, the writing mode of floating-gate memory mainly contains two kinds, wherein a kind of voltage for fixing drain electrode, and the voltage that changes control grid (control gate) causes required voltage difference, for example No. 6111791 disclosed wiring method of United States Patent (USP).Yet the resistance-capacitance time delay (RCdelay time) of character line (word line) is bigger usually, and therefore, the action that need write the more time can't reach the effect that writes fast.
Another kind of then the voltage of fixing control grid, the voltage that changes drain electrode causes required voltage difference, and the change degree of utilizing its electric current to change to come decision threshold voltage.US6937518B1 number disclosed wiring method of United States Patent (USP) for example.Yet this kind method needs progressively to change the voltage of drain electrode and monitor its electric current, needs charge pump that stable change in voltage and current-sensing circuit is provided, and its circuit realizes that difficulty is higher, and required chip area also may be bigger.And the time of utilizing the electric current rapid drawdown judges that whether the state that writes finish, and the assembly after it writes is specific to have bigger difference, and the threshold voltage after writing is more wayward, and the correctness of reading is descended.
Summary of the invention
One of them provides a kind of write circuit of flash memory purpose of the present invention, utilizes fixed current to carry out the write activity of flash memory, can reduce the complexity and the cost of circuit design, and shorten the write time.
One of them is that a kind of wiring method of flash memory is being provided for a purpose of the present invention, carry out the write activity of flash memory with fixed current and fixed railing pole tension, therefore, can reduce specification requirement, and make the threshold voltage after writing that preferable concentration degree be arranged outside charge pump (chargepump).
For reaching above-mentioned and other purpose, the present invention proposes a kind of write circuit of flash memory, is applicable to the write activity that carries out a memory element, and this write circuit comprises writing unit and detecting unit.Writing unit is in order to export a write current and a reference voltage, and detecting unit then is coupled between writing unit and the memory element.
Wherein, detecting unit comprises a N transistor npn npn, the 2nd N transistor npn npn and comparer.One end of the one N transistor npn npn is coupled to writing unit.The 2nd N transistor npn npn is coupled between a N transistor npn npn and the memory element.The positive input terminal of comparer is coupled to reference voltage, and the negative input end of comparer is coupled to the shared node of a N transistor npn npn and this writing unit, and the output terminal of comparer is coupled to the grid of the 2nd N transistor npn npn.
For reaching above-mentioned and other purpose, the present invention proposes a kind of write circuit of flash memory, is applicable to the write activity that carries out a memory array, can write a plurality of memory elements in regular turn.This write circuit comprises writing unit, detecting unit and a plurality of switch, and these switches are coupled between detecting unit and the memory element, the memory element of desiring to write in order to select (for example first memory element and second memory element).
Wherein, detecting unit comprises a N transistor npn npn, the 2nd N transistor npn npn and comparer.One end of the one N transistor npn npn is coupled to this writing unit.The 2nd N transistor npn npn is coupled between a N transistor npn npn and the memory element.The positive input terminal of comparer is coupled to reference voltage, and the negative input end of comparer is coupled to the shared node of a N transistor npn npn and this writing unit, and the output terminal of comparer is coupled to the grid of the 2nd N transistor npn npn.
Similarly, if it is fashionable to desire to carry out writing of second memory element, then can utilize switch, with write current conducting to the second memory element, and write voltage (in another embodiment of the present invention according to what second memory element was exported, can be the drain voltage of memory element), determine whether the threshold voltage of second memory element has reached desired magnitude of voltage.
The present invention utilizes fixed current and fixed railing pole tension to carry out the write activity of flash memory, and via the drain voltage of flash memory, judges the variation of its threshold voltage.Therefore, the present invention can adjust the threshold voltage after writing accurately, and reduces the design complexities of write circuit and to the specification demand of outside charge pump.In addition, the present invention just can be adjusted to threshold voltage required magnitude of voltage in the write activity of single, can significantly shorten the write time.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below, wherein:
Fig. 1 is the circuit diagram of the write circuit of flash memory according to an embodiment of the invention.
Fig. 2 is the circuit diagram of the write circuit of flash memory according to another embodiment of the present invention.
Fig. 3 is the oscillogram of write current and memory element characteristic according to another embodiment of the present invention.
Fig. 4 is the oscillogram of signal simulation according to another embodiment of the present invention.
Fig. 5 is the process flow diagram of the wiring method of flash memory according to another embodiment of the present invention.
Embodiment
Fig. 1 is the circuit diagram of the write circuit of flash memory according to an embodiment of the invention.Write circuit 100 comprises writing unit 110 and detecting unit 120, and 100 of writing units are used for the memory element FM in the storage unit 130 is carried out write activity.In the present embodiment, memory element FM is a floating-gate memory, just a kind of in the flash memory.The control grid of memory element FM is coupled to a character line (word line), and the character line can apply character line voltage V on the control end (control grid) of memory element FM
WL
What write circuit 100 was coupled to memory element FM writes end (drain electrode), and the source electrode of memory element FM then is coupled to earth terminal GND.When carrying out the write activity of memory element FM, the character line can be exported the character line voltage V of certain value
WLTo the control grid of memory element FM, and write circuit 100 can be exported the write current I of certain value
WRTo memory element FM.At this moment, the drain electrode meeting of memory element FM is according to write current I
WRWith character line voltage V
WLOutput writes voltage V
WR(drain voltage just).In other words, can formation write fashionable required voltage difference between the drain electrode of memory element FM and the grid.When memory element FM mend to fall into the variation that electronics produces threshold voltage because of floating grid (it is big that threshold voltage becomes), the electric current of conducting equals write current I in order to keep
WR, write voltage V
WRCan increase thereupon.Therefore, write voltage V
WRHave correlativity with threshold voltage, write circuit 100 is just by writing voltage V
WRVariation, know the threshold voltage of memory element FM by inference, when writing voltage V
WRWhen reaching predetermined value, just the write activity of memory element FM is finished in expression.
The present invention judges with control gate pole tension, drain voltage and the conducting electric current of memory element FM whether the threshold voltage of memory element FM reaches required predetermined value.Therefore, even there is the process variation factor to exist, cause the property difference between the different memory elements, after utilizing technological means of the present invention to finish write activity, its threshold voltage should be comparatively close.In the write activity of single, just threshold voltage can be adjusted to required numerical value, do not need repeatedly to write, can significantly shorten the write time.Simultaneously, because the present invention only need provide fixing write current and character line voltage can reach write activity, so its circuit framework realization cost is lower, uses better simply charge pump to provide required voltage can finish write activity.
Next, further specify the circuit framework of write circuit 100, the write current I that write circuit 100 is exported
WRProvided by writing unit 110,120 of detecting units are responsible for detecting and are write voltage V
WRThe main framework of writing unit 110 is a current mirror, mainly by P transistor npn npn (PMOS transistor) PM1, PM2 and current source I
REFForm.P transistor npn npn PM1 is coupled to operating voltage and current source I
REFBetween, P transistor npn npn PM2 is coupled between operating voltage VPUMP and the detecting unit 120.The grid of P transistor npn npn PM1 is coupled to the grid of P transistor npn npn PM2, and the grid of P transistor npn npn PM1 also is coupled to P transistor npn npn PM1 and current source I
REFShared node.Wherein, P transistor npn npn PM2 is according to current source I
REF, export corresponding write current I
WR, P transistor npn npn PM1 and current source T
REFShared node output reference voltage V
REF
Operating voltage VPUMP can be provided by external power source or inner charge pump, because write circuit 100 only needs charge pump that required operating voltage VPUMP is provided, so does not need the charge pump of highly energy-consuming can carry out the write activity of memory element FM.
Detecting unit 120 mainly is made up of N transistor npn npn (nmos pass transistor) NM3, NM4 and comparator C MP.N transistor npn npn NM3, NM4 series connection also is coupled between the drain electrode of P transistor npn npn PM2 and memory element FM.The grid of N transistor npn npn NM3 is coupled to strangulation voltage V
CLA, the grid of N transistor npn npn NM4 then is coupled to the output terminal of comparator C MP.The positive input terminal of comparator C MP is coupled to P transistor npn npn PM1 and current source I
REFShared node, the negative input end of comparator C MP then is coupled to the shared node of N transistor npn npn NM3 and P transistor npn npn PM2.The shared contact output comparative voltage V of N transistor npn npn NM3 and P transistor npn npn PM2
COM, comparator C MP is according to comparative voltage V
COMWith reference voltage V
REFOutput control voltage V
COMTo the grid of N transistor npn npn NM4, wherein write fashionable, comparative voltage V
CONFor logic high potential (in the present embodiment, as comparative voltage V
CONDuring for " H ", its current potential is essentially VPUMP; As comparative voltage V
CONBe " L " that its current potential is essentially 0).
Writing of memory element FM is fashionable carrying out, strangulation voltage V
CLABe stable reference voltage, make N transistor npn npn NM3 have the effect of amplifier, write current I
WRVia N transistor npn npn NM3, NM4 conducting to memory element FM.Memory element FM writes voltage V
WRAfter N transistor npn npn NM3 amplification, produce comparative voltage V
COMIf the desired magnitude of voltage of threshold voltage no show still of memory element FM, then comparative voltage V
COMLess than reference voltage V
REF, control voltage V
CONKeep noble potential with conducting N transistor npn npn NM4.When the threshold voltage of memory element FM rises to desired magnitude of voltage gradually along with write activity, write voltage V
WRCan rise thereupon, make comparative voltage V
COMGreater than reference voltage V
REFAt this moment, comparator C MP can export the control voltage V of electronegative potential
CONTo close N transistor npn npn NM4, detecting unit 120 is stop conducting write current I just
WRTo memory element FM.Utilize the threshold voltage of memory element FM to change, just can make memory element FM have the memory function of logical one and logical zero.
In the ablation process of memory element FM, character line voltage V
WLWith write current I
WRBe all definite value, via setting different character line voltage V
WLWith write current I
WRCan change the threshold voltage after writing speed and memory element FM write.Character line voltage V
WLWith write current I
WRCan and decide according to different memory element specification or process conditions.In addition, via reference voltage V
REFWith strangulation voltage V
CLASetting also can adjust the threshold voltage of memory element FM.Have in the present technique field and to know the knowledgeable usually,, should know its application mode easily by inference, do not add tired stating at this via exposure of the present invention.
In addition, write circuit of the present invention is also applicable to the write activity that carries out memory array, only needs to add between write circuit and memory array that switch selects the memory element desiring to write to get final product.Fig. 2 is the circuit diagram of the write circuit of flash memory according to another embodiment of the present invention.Comprise a plurality of memory elements in the memory array 210, memory element is arranged with array way, and the memory element of each row (row) is corresponding to a character line, and the memory element of each row (column) is corresponding to a bit lines.Character line WL0-WLN controls the control gate pole tension of all memory elements, and bit line DBL0-DBL7 then controls the source voltage and the drain voltage of the memory element of preceding 7 row, and the rest may be inferred by analogy for it.
In another embodiment of the present invention, write circuit 100 also can be coupled to different bit line (as bit line DBL2, DBL6) to write different memory elements via different switches (for example switch S 22, S24).In ablation process, the memory element that is chosen to (as memory element FM1), its drain electrode meeting writes voltage V via switch S 23 outputs
WROutput terminal to write circuit 100.Similarly, the threshold voltage variation along with memory element FM1 writes voltage V
WRAlso can change thereupon.When writing voltage V
WRCorresponding to reference voltage V
REFThe time (can be via the comparative voltage V after amplifying
COMWith reference voltage V
REFRelatively get), represent that promptly write activity finishes, write circuit 100 just can stop to export write current T
WR
For the arrangement mode of memory array 210, still comprise multiple different layout type, but its principle is similar.As long as can select the memory element desiring to write via character line and bit line, promptly applicable to the write circuit of present embodiment, have in the present technique field and to know the knowledgeable usually, via exposure of the present invention, should know its application mode easily by inference, do not add tired stating at this.
In another embodiment of the present invention, write circuit 100 also can be carried out write activity to different memory elements in regular turn.If the memory element (for example FM1, FM2) with same character line is an example, what can divide another name is first memory element and second memory element.In ablation process, when switch S 21, S31 conducting, write circuit 100 output write current IWR to memory element FM2 to carry out write activity; When switch S 23, S32 conducting, write circuit 100 output write current I
WRTo memory element FM2 to carry out write activity.In other words, as long as corresponding switch is set, just write circuit 100 can be carried out write activity to different memory elements one by one.As long as the configuration more switches, write circuit 100 just can for example be coupled to switch S 22, S24 the output of write circuit 100 to optionally more memory element being carried out write activity.In another embodiment of the present invention, many group write circuits can be set simultaneously, simultaneously a plurality of memory elements are carried out write activity, quicken writing of data.
Next, further technological means of the present invention is described in the waveform mode.Fig. 3 is the oscillogram of write current and memory element characteristic according to another embodiment of the present invention.The IV performance diagram of memory element is then shown in Figure 3, and the longitudinal axis is represented the conducting electric current I of memory element
DS, and transverse axis is represented drawing-source voltage (draining to the voltage difference of source electrode) V of memory element
DSThe control gate pole tension of memory element equals character line voltage, therefore, and at identical grid-source voltage (grid is to the voltage difference of source electrode) V
GSDown, threshold voltage is high more, its conducting electric current I
DSJust more little.So, threshold voltage V
TH1＜V
TH2＜V
TH3＜V
TH4In ablation process, threshold voltage can rise gradually, and the conducting electric current of memory element must equal write current I
WR, therefore, draw-source voltage V
DSMust and rise along with the upward living of threshold voltage.In the present embodiment, desired threshold voltage is V
TH3
Therefore, when drawing-source voltage V
DS(being the described voltage that writes of Fig. 1) reaches predetermined voltage V
PREThe time (the A point among Fig. 3), represent that promptly the threshold voltage of memory element has been adjusted to desired threshold voltage V
TH3, predetermined voltage V wherein
PREEqual strangulation voltage V
CLADeduct the V of N transistor npn npn NM3
GS(grid-source voltage) and V
IR-drop(voltage drop that dead resistance produced on the current path).At this moment, write current I
WRCan reduce to zero, just close N transistor npn npn NM4.Below explanation please refer to Fig. 1, in the present embodiment, and current source I
REFCan determine reference voltage V
REF, this reference voltage V
REFCan be used as judgement draws-source voltage V
DSWhether reach predetermined voltage V
PREFoundation.Set different strangulation voltage V simultaneously
CLACan be corresponding to different drawing-source voltage V
DS, make the memory element after writing have different threshold voltages.Threshold voltage is mainly by current source I
REF, reference voltage V
REF, strangulation voltage V
CLAWith character line voltage V
WLDetermine.
Fig. 4 is the oscillogram of signal simulation according to another embodiment of the present invention.Below explanation asks the while with reference to Fig. 1, as shown in Figure 4, in the ablation process of storer, reference voltage V
REFBe definite value, comparative voltage V
COMAlong with writing voltage V
WRAnd become.Write current I
WROn setting is definite value (for example 60 μ A, 70 μ A or 80 μ A), but may be because of comparative voltage V
COMChange and descend a little, this is because the drain voltage of P transistor npn npn PM2 can affected relation.Threshold voltage V when memory element
THWhen rising, write voltage V because of writing
WRComparative voltage V can be risen thereupon
COMThen along with writing voltage V
WRAnd rise, and have gain and write voltage V
WREffect.
As comparative voltage V
COMGreater than reference voltage V
REFThe time, just at time point T
OFF(the threshold voltage V of memory element
THEqual threshold values predetermined voltage V
THThe time) afterwards, comparator C MP is transition immediately, and the control voltage V of output electronegative potential
CONAt this moment, N transistor npn npn NM4 closes immediately, write current I
WRWith write voltage V
WRDescend fast immediately, also finish the write activity of memory element simultaneously.Wherein, as the write current I that sets
WRHeal when high, the write activity of memory element is just finished its threshold voltage V sooner
THReach threshold values predetermined voltage V sooner
TH
From another viewpoint, the present invention also proposes a kind of wiring method of flash memory, and Fig. 5 is the process flow diagram of the wiring method of flash memory according to another embodiment of the present invention.Comprise the following steps: that at first in step S510, provide the control end of character line voltage to memory element, this character line voltage is definite value.If memory element is a floating-gate memory, then its control end is the control grid of floating-gate memory.Then, in step S520, the output write current is to the end that writes of memory element, and to adjust the threshold voltage of memory element, this write current is a certain value.In step S530, the detecting memory element write the voltage that writes that end exports, for example detect the drain terminal voltage of floating-gate memory.Then, in step S540, when writing voltage, stop to export write current, and finish the write activity of memory element to memory element corresponding to reference voltage.Because under fixing write current, the writing voltage and can become of floating-gate memory along with threshold voltage.Therefore, when writing voltage, represent that promptly the threshold voltage of floating-gate memory has reached the threshold voltage value of expectation corresponding to reference voltage.
In another embodiment of the present invention,, can adopt the mode that writes one by one and carry out write activity if need write plural memory element the time.In step S510, provide character line voltage to all the other memory elements of desiring to write.And matching step S520 to S530, switch write current to different memory elements and detect it and write voltage, carry out writing of memory element one by one.When writing voltage, stop to export write current to memory element corresponding to reference voltage.All the other details of the wiring method of present embodiment do not add tired stating all with among the embodiment that is specified in above-mentioned Fig. 1-Fig. 4 at this.
The present invention utilizes fixed current to carry out the write activity of flash memory, just can judge the variation of its threshold voltage via the drain voltage of flash memory.Therefore, easy enforcement of circuit framework of the present invention and design cost are lower, and can adjust the threshold voltage after writing accurately.Simultaneously, because the voltage that must finely tune does not carry out write activity, therefore can reduce specification demand to outside charge pump.In addition, the present invention just can be adjusted to threshold voltage required numerical value in the write activity of single, do not need repeatedly to write, and can significantly shorten the write time.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any affiliated technical field has knows the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking accompanying being as the criterion that claim defines.
Claims (14)
1. the write circuit of a flash memory is applicable to the write activity that carries out a memory element, it is characterized in that, this write circuit comprises:
One writing unit is in order to export a write current and a reference voltage; And
One detecting unit is coupled between this writing unit and this memory element, and wherein this detecting unit comprises:
One the one N transistor npn npn, an end of a N transistor npn npn is coupled to this writing unit;
One the 2nd N transistor npn npn is coupled between a N transistor npn npn and this memory element, and
One comparer, the positive input terminal of this comparer is coupled to this reference voltage, and the negative input end of this comparer is coupled to the shared node of a N transistor npn npn and this writing unit, and the output terminal of this comparer is coupled to the grid of the 2nd N transistor npn npn.
2. the write circuit of flash memory as claimed in claim 1 is characterized in that, wherein this writing unit comprises:
One current mirror is in order to export this write current.
3. the write circuit of flash memory as claimed in claim 2 is characterized in that, wherein this current mirror comprises:
One the one P transistor npn npn is coupled between an operating voltage and the current source; And
One the 2nd P transistor npn npn, be coupled between this operating voltage and this detecting unit, the grid of the one P transistor npn npn is coupled to the grid of the 2nd P transistor npn npn, and the grid of a P transistor npn npn also is coupled to the shared node of a P transistor npn npn and this current source;
Wherein, the 2nd P transistor npn npn is exported corresponding this write current according to this current source, and the shared node of a P transistor npn npn and this current source is exported this reference voltage.
4. the write circuit of flash memory as claimed in claim 3, it is characterized in that, wherein a N transistor npn npn and the 2nd N transistor npn npn are coupled between the 2nd P transistor npn npn and this memory element, and the grid of a N transistor npn npn is coupled to a strangulation voltage; The positive input terminal of this comparer is coupled to the shared node of a P transistor npn npn and this current source, the negative input end of this comparer is coupled to the shared node of a N transistor npn npn and the 2nd P transistor npn npn, and exports the grid of a control voltage to the 2nd N transistor npn npn.
5. the write circuit of flash memory as claimed in claim 4 is characterized in that, wherein in that to carry out writing of this memory element fashionable, and this strangulation voltage-activated.
6. the write circuit of flash memory as claimed in claim 1, it is characterized in that, wherein this memory element comprises floating-gate memory, the drain electrode end of this floating-gate memory is coupled to this detecting unit, and export one and write voltage, the source terminal of this floating-gate memory is coupled to an earth terminal, the control grid of this floating-gate memory is coupled to a character line, and receive this character line voltage, the drain electrode of this floating-gate memory is the end that writes of this memory element, and the control gate of this floating-gate memory is the control end of this memory element very.
7. the write circuit of a flash memory is applicable to the write activity that carries out a memory array, and this memory array comprises a plurality of memory elements, it is characterized in that, this write circuit comprises:
One writing unit is in order to export a write current and a reference voltage;
One detecting unit is coupled to this writing unit, and wherein this detecting unit comprises:
One the one N transistor npn npn, an end of a N transistor npn npn is coupled to this writing unit;
One the 2nd N transistor npn npn is coupled between a N transistor npn npn and the described a plurality of memory element, and
One comparer, the positive input terminal of this comparer is coupled to this reference voltage, and the negative input end of this comparer is coupled to the shared node of a N transistor npn npn and this writing unit, and the output terminal of this comparer is coupled to the grid of the 2nd N transistor npn npn; And
A plurality of switches are coupled between this detecting unit and the described a plurality of memory element, in order to select described a plurality of memory element.
8. the write circuit of flash memory as claimed in claim 7 is characterized in that, wherein this writing unit comprises:
One current mirror is in order to export this write current.
9. the write circuit of flash memory as claimed in claim 8 is characterized in that, wherein this current mirror comprises:
One the one P transistor npn npn is coupled between an operating voltage and the current source; And
One the 2nd P transistor npn npn, be coupled between this operating voltage and this detecting unit, the grid of the one P transistor npn npn is coupled to the grid of the 2nd P transistor npn npn, and the grid of a P transistor npn npn also is coupled to the shared node of a P transistor npn npn and this current source;
Wherein, the 2nd P transistor npn npn is exported corresponding this write current according to this current source, and the shared node of a P transistor npn npn and this current source is exported this reference voltage.
10. the write circuit of flash memory as claimed in claim 9, it is characterized in that, wherein a N transistor npn npn and the 2nd N transistor npn npn are coupled between the 2nd P transistor npn npn and the described a plurality of memory element, and the grid of a N transistor npn npn is coupled to a strangulation voltage; The positive input terminal of this comparer is coupled to the shared node of a P transistor npn npn and this current source, the negative input end of this comparer is coupled to the shared node of a N transistor npn npn and the 2nd P transistor npn npn, and exports the grid of a control voltage to the 2nd N transistor npn npn.
11. the write circuit of flash memory as claimed in claim 10 is characterized in that, wherein in that to carry out writing of described a plurality of memory elements fashionable, and this strangulation voltage-activated.
12. the write circuit of flash memory as claimed in claim 7 is characterized in that, wherein the shared node of a N transistor npn npn and this writing unit is exported a comparative voltage, and the grid of a N transistor npn npn is coupled to a strangulation voltage; The positive input terminal of this comparer is coupled to this reference voltage, and the negative input end of this comparer is coupled to this comparative voltage, and the output terminal of this comparer is coupled to the grid of the 2nd N transistor npn npn; Wherein, this writing unit is exported this write current to this storage unit via a N transistor npn npn and the 2nd N transistor npn npn, and make this comparative voltage write voltage corresponding to one, this comparer is according to this comparative voltage and this reference voltage, output one is controlled voltage to the 2nd N transistor npn npn, when this comparative voltage is lower than this reference voltage, and this comparer conducting the 2nd N transistor npn npn, when this comparative voltage was higher than this reference voltage, this comparer was closed the 2nd N transistor npn npn.
13. the write circuit of flash memory as claimed in claim 12 is characterized in that, wherein in that to carry out writing of described a plurality of memory elements fashionable, and this strangulation voltage-activated.
14. the write circuit of flash memory as claimed in claim 7, it is characterized in that, wherein said a plurality of memory element comprises floating-gate memory, the drain electrode end of this floating-gate memory is coupled to this detecting unit, and export one and write voltage, the source terminal of this floating-gate memory is coupled to an earth terminal, the grid of this floating-gate memory is coupled to a character line, and receive this character line voltage, the drain electrode of this floating boom utmost point storer is the end that writes of described a plurality of memory elements, and the source electrode of this floating-gate memory is the control end of described a plurality of memory elements.
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| CN102270491B (en) * | 2011-03-10 | 2015-09-09 | 上海华虹宏力半导体制造有限公司 | With the flash memory write circuit that source line voltage compensates |
| CN102624229B (en) * | 2012-03-31 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Booster circuit and integrated circuit |
| CN103426472B (en) * | 2013-07-31 | 2017-03-01 | 辉芒微电子（深圳）有限公司 | The programing system of Nor flash storage and method |
| TWI571871B (en) * | 2015-10-19 | 2017-02-21 | 円星科技股份有限公司 | Memory write tracking device and method |
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| US6081448A (en) * | 1997-09-19 | 2000-06-27 | Stmicroelectronics S.R.L. | Method and device for analog programming of flash EEPROM memory cells with autoverify |
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2006
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| US5684741A (en) * | 1995-12-26 | 1997-11-04 | Intel Corporation | Auto-verification of programming flash memory cells |
| US5712815A (en) * | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
| US6081448A (en) * | 1997-09-19 | 2000-06-27 | Stmicroelectronics S.R.L. | Method and device for analog programming of flash EEPROM memory cells with autoverify |
| US6002611A (en) * | 1998-07-22 | 1999-12-14 | Halo Lsi Design & Device Technology, Inc. | Fast, low current program with auto-program for flash memory |
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