Summary of the invention
Technical problem to be solved by this invention is for fear of because use directly access storage control and so that the direct access storage operation Efficiency Decreasing between the bus apparatus and destroy bus structures of central authorities.
For addressing the above problem, the present invention with IP core, directly access storage control, advanced microcontroller bus architecture main interface and advanced microcontroller bus architecture and consist of the device that can finish direct access memory function from Interface integration.Each building block that regards to down the direct access to storage device of the present invention is done to introduce one by one:
Advanced microcontroller bus architecture links to each other with bus from interface, is used to receive and transmit the system signal that CPU notice intellectual property core is directly visited storage operation;
Intellectual property core receives and sends according to system signal and directly visits store operation request signal and operation information; Receive the feedback and the notification signal of DASD;
Directly visit memory controller, receive also according to directly visiting store operation request signal and operation information, enabled instruction, the activation bit of the transmission of transmission bus data; Receive and send the bus data transmission ending and instruct according to the bust this information that advanced microcontroller bus architecture main interface feeds back; Receive and send internal data or receive external data; The notice intellectual property core is directly visited storage operation success or failure;
Advanced microcontroller bus architecture main interface links to each other with bus, and reception enabled instruction and activation bit start with transfer of data and the feedback of bus directly accesses storage control; Receive the transfer of data of command for stopping termination and bus, and will be transferred to from the external data that bus receives direct access storage control; The internal data of directly accessing the storage control transmission is sent to bus.
Correspondingly, the present invention has also adopted a kind of method of direct access storage operation, may further comprise the steps: CPU directly accesses storage operation to IP core transmitting system signal notice; IP core sends directly access request signal storage and operation information to direct access storage control; Directly the reception of access storage control is directly accessed request signal storage and operation information and is fed back to IP core; IP core receives feedback and disposes request signal; Directly the access storage control sends enabled instruction and activation bit according to the operation information that receives to advanced microcontroller bus architecture main interface; Advanced microcontroller bus architecture main interface receives enabled instruction and activation bit starts the bus data transmission that directly access is stored, receive external data from bus and be transferred to direct access storage control or be sent to bus from direct access storage control reception internal data, and the bus data transmission course is fed back to direct access storage control; Directly the access storage control keeps proceeding of bus data transmission or sends command for stopping to advanced microcontroller bus architecture main interface stopping the bus data transmission and notifying IP core directly to access the storage operation failure according to the feedback of reception; After bus data was transmitted, advanced microcontroller bus architecture main interface notice directly access storage control bus data was transmitted, and directly accessed storage control notice IP core and directly accessed the storage operation success.
Compared with prior art, the present invention has the following advantages:
The direct access to storage device of the present invention by with intellectual property core, directly visit memory controller, advanced microcontroller bus architecture main interface and advanced microcontroller bus architecture and constitute the device that can finish direct visit memory function from interface is integrated, need not the receiving of process central straight and ask memory controller, and rejected the inside moderator that memory controller is asked in the central straight receiving, therefore area is less, has reduced chip cost;
2. directly visiting methods of storage operating from the present invention can see, directly the data transmission of intellectual property core and bus apparatus all unifies to finish and adopt by advanced microcontroller bus architecture main interface the bus transfer of standard in the visit storage operation on bus, so does not destroy bus structure;
3. directly access the methods of storage operating and can also see from the present invention, directly access storage operation institute the transmission of data only directly transmits between the direct access to storage device of the present invention and bus apparatus by bus and need not directly to access storage control through central authorities, and therefore directly access storage operation efficient improves.
Embodiment
The direct access to storage device of the present invention by with intellectual property core 1, directly visit memory controller 5, data buffer 3, buffer controller 4, advanced microcontroller bus architecture main interface 6 and advanced microcontroller bus architecture 7 and integrate from interface.Make IP core 1 can pass through Advanced High-performance Bus (AHB, Advanced High-performance Bus) directly with bus on equipment realize directly accessing and store data transfer operation.
As shown in Figure 1, the direct access to storage device of the present invention (not label) comprising:
Advanced microcontroller bus architecture links to each other with bus from interface 7, is used for receiving and transmitting the system signal that CPU notice IP core 1 is directly accessed storage operation;
IP core 1 receives and sends according to system signal and directly accesses store operation request signal and operation information; Receive feedback and the notification signal of DASD 5;
Directly visit memory controller 5, receive also according to directly visiting store operation request signal and operation information, enabled instruction, the activation bit of the transmission of transmission bus data; The bust this information that receives and feed back according to advanced microcontroller bus architecture main interface 6 sends the instruction of bus data transmission ending; Receive and send internal data or receive external data; Notice intellectual property core 1 is directly visited storage operation success or failure;
Advanced microcontroller bus architecture main interface 6 links to each other with bus, and reception enabled instruction and activation bit start with transfer of data and the feedback of bus directly accesses storage control 5; Receive the transfer of data of command for stopping termination and bus, and will be transferred to from the external data that bus receives direct access storage control 5; The internal data of directly accessing storage control 5 transmissions is sent to bus.
The direct access to storage device of the present invention can also comprise data buffer 3, and storage is external data or the internal data of access storage operation directly.Buffer controller 4 adopts Port Multiplier to realize, gives for the internal data transfer of the external data data writing buffer that will directly access storage control 5 receptions or 3 storages of reading out data buffer and directly accesses storage control 5.Certainly, the direct access to storage device of the present invention does not need to rely on data buffer 3 and cache controller 4 realizes directly visiting memory function, increases these two parts just in order to make direct visit storage operation process for the preservation of internal data and external data with handle convenient.
Described intellectual property core 1 can also comprise register group 2, is used to store advanced microcontroller bus architecture from the system signal of interface 7 transmission and the operation information of intellectual property core 1 generation.Make the system signal of IP core reception and the operation information signal of generation classify clearer and more definite by in IP core, adding register group.
Described direct visit memory controller 5 comprise with the interface module (not shown) of intellectual property core 1, with the interface module (not shown) of advanced microcontroller bus architecture main interface 6, with the interface module (not shown) and the inner function module (not shown) of buffer controller 4.Wherein each interface module is responsible for transmitting with the signal of corresponding component, for example with the data-signal transmission of the responsible directly access of the interface module of buffer controller 4 storage control 5 with cache controller 4.And inner function module is finished instruction transmission and receiving function, and the request signal that for example receives intellectual property core 1 sends feedback signal and is transferred to intellectual property core 1 by the interface module with intellectual property core 1.
Described system signal comprises equipment state signal and device address signal, and wherein the equipment state signal comprises source device status signal or target device status signal, and whether expression source device or target device be available for direct visit storage; The device address signal comprises source device address signal or destination device address signal, and expression is the source device or the destination device address of visit storage operation directly.
Described operation information comprises read-write state, transmission size of data, source device address signal base and destination device address signal base.
Described activation bit comprises read-write state, transmission size of data, transport-type, current transmission state, source device address and destination device address.
Described internal data be intellectual property core will be on bus the data that transmit of equipment.
The data that the described external data bus apparatus that to be advanced microcontroller bus architecture main interface receive from bus transmits.
Fig. 2 is the method that the present invention directly accesses storage operation, comprising: CPU directly accesses storage operation to IP core transmitting system signal notice; IP core sends directly access request signal storage and operation information to direct access storage control; Directly the reception of access storage control is directly accessed request signal storage and operation information and is fed back to IP core; IP core receives feedback and disposes request signal; Directly the access storage control sends enabled instruction and activation bit according to the operation information that receives to advanced microcontroller bus architecture main interface; Advanced microcontroller bus architecture main interface receives enabled instruction and activation bit starts the bus data transmission that directly access is stored, receive external data from bus and be transferred to direct access storage control or be sent to bus from direct access storage control reception internal data, and the bus data transmission course is fed back to direct access storage control; Directly the access storage control keeps proceeding of bus data transmission or sends command for stopping to advanced microcontroller bus architecture main interface stopping the bus data transmission and notifying IP core directly to access the storage operation failure according to the feedback of reception; After bus data was transmitted, advanced microcontroller bus architecture main interface notice directly access storage control bus data was transmitted, and directly accessed storage control notice IP core and directly accessed the storage operation success.
Elaborate for two kinds of direct access storage operations of read and write respectively below in conjunction with Fig. 2 and Fig. 3.
In the write operation, it is the source device of directly accessing storage operation that CPU10 notice bus arbiter 8 is specified the direct access to storage device of the present invention, and bus apparatus 11 conducts are the target device of access storage directly.Comprise the following steps:
Step 21, CPU produces system signal and comprises that target device status signal Opposite_IP_ready and destination device address signal base External_base_addr send the notice intellectual property core to intellectual property core and directly visit storage operation, for the Opposite_IP_ready signal, if value is then represented also inaccessible of target device for " 0 "; If value represents then that for " 1 " target device is addressable, is " 1 " herein, the register group in the intellectual property core obtains these signals and temporary from advanced microcontroller bus architecture from interface;
Step 22, IP core sends direct access request signal storage DMA_request and directly accesses store operation information to direct access storage control, comprise the DMA_direction signal, the read-write state of expression and target device is herein owing to be that write operation is thought " 1 "; The DMA_size signal, the size of expression and target device the transmission of data; The Internal_base_addr signal, expression source device address signal base; The External_base_addr signal, expression destination device address signal base;
Step 23, directly the visit memory controller receives the direct visit request signal storage that intellectual property core is sent, return a feedback signal DMA_acknowledge, obtain the direct visit store operation information that intellectual property core sends simultaneously and will directly visit storage finish signal DMA_end be changed to invalid, send to intellectual property core, wherein directly visit the internal clocking control of request signal storage by intellectual property core, the clock control that signal is produced by Advanced High-performance Bus is finished in feedback signal and direct visit storage, concrete sequential relationship as shown in Figure 5, wherein system signal sys_clk is that Advanced High-performance Bus produces clock, using signal app_clk is the intellectual property core internal clocking, we can find out therefrom that the clock frequency that bus produces will be higher than the intellectual property core clock internal, for guaranteeing feedback signal, direct visit storage is finished these signals of signal and can be sampled by slower intellectual property core internal clocking, these signals must latch the time of several at least clock period, the designer can directly be configured and select in the visit memory controller by the frequency multiple relation decision of two clocks concrete what clock period;
Step 24, if intellectual property core is received the feedback signal of direct visit memory controller, it is invalid request signal can be changed to, otherwise, can keep the request signal value invalid for height just is changed to request signal up to overtime or other reasons always; Simultaneously, directly the visit memory controller sends enabled instruction to advanced microcontroller bus architecture main interface, be cue Call_Master, simultaneously according to the direct visit store operation information of accepting, send activation bit to main interface and comprise read-write state signal HWRITE_root, this moment, HWRITE_root was " 1 ", and expression writes data to target device; Transmission size of data signal HSIZE_root, transport-type signal HBURST_root, expression burst transfer; Current transmission state signal HTRANS_root comprises discontinuously, continuously, waits for, and busy four kinds of states, be continuous state this moment; Source device address signal Internal_addr adds that by direct visit memory controller the side-play amount (offset) that is no more than the transmission size of data constitutes on source device address signal base Internal_base_addr; Destination device address signal HADDR adds that by direct visit memory controller the side-play amount (offset) that is no more than the transmission size of data constitutes on destination device address signal base External_base_addr equally;
Step 25, advanced microcontroller bus architecture main interface receives enabled instruction and activation bit starts the bus data transmission that directly access is stored, directly the access storage control is according to learning it is write operation with target device with the read-write state signal value of target device for " 1 ", therefore from data buffer, read internal data by cache controller, and advanced microcontroller bus architecture main interface learns it is to the target device data writing according to the read-write state signal HWRITE_root of activation bit for " 1 ", therefore receive the internal data write bus from direct access storage control, in bus data writing process, advanced microcontroller bus architecture main interface can return feedback signal to direct access storage control, be transmission state response signal HRESP, comprise the normal OK of transmission, loading error occurring ERROR, if directly accessing the transmission state response signal that storage control receives is OK, then can keep advanced microcontroller bus architecture main interface proceeding to the bus data writing; If directly accessing the transmission state response signal that storage control receives is ERROR, directly the access storage control can send command for stopping to advanced microcontroller bus architecture main interface and stop advanced microcontroller bus architecture main interface to the bus data writing, and to send direct access event memory signal DMA_result to IP core be that the information of failure represents directly to access the storage operation failure;
Step 26, when advanced microcontroller bus architecture main interface after bus writes data and finishes, the direct visit of advanced microcontroller bus architecture main interface notice memory controller writes data to bus and finishes, directly the visit memory controller to intellectual property core send direct visit storage stop signal DMA_end and directly visit event memory signal DMA_result be that the storage operation success is directly visited in the information representation of success, it with DMA_end by identical clock control, also need to latch several clock period to be sampled by the intellectual property core internal clocking guaranteeing.
In the read operation, it is the source device of directly accessing storage operation that CPU10 specifies the direct access to storage device of the present invention to bus arbiter 8 transmission signals, and bus apparatus 11 is as the target device of directly accessing storage.The step of read operation and write operation is similar, may further comprise the steps:
Step 21, CPU produces system signal and comprises that target device status signal Opposite_IP_ready and destination device address signal base External_base_addr send the notice intellectual property core to intellectual property core and directly visit storage operation, this moment, the Opposite_IP_ready value was " 1 ", the expression target device is addressable, and the register group in the intellectual property core obtains these signals and temporary from advanced microcontroller bus architecture from interface;
Step 22, intellectual property core is sent direct visit request signal storage DMA_request and is directly visited store operation information to direct visit memory controller, comprises that the DMA_direction signal is " 0 ", represents the read operation with target device; Expression and target device transmission size of data; The DMA_size signal; The Internal_base_addr signal of expression source device address signal base; The External_base_addr signal of expression destination device address signal base;
Step 23, directly the visit memory controller receives the direct visit request signal storage that intellectual property core is sent, return a feedback signal DMA_acknowledge, obtain the direct visit store operation information that intellectual property core sends simultaneously and will directly visit storage stop signal DMA_end and be changed to invalidly, send to intellectual property core;
Step 24, if intellectual property core is received the feedback signal of direct visit memory controller, it is invalid request signal can be changed to, otherwise, can keep the request signal value invalid for height just is changed to request signal up to overtime or other reasons always; Simultaneously, directly the visit memory controller sends enabled instruction to advanced microcontroller bus architecture main interface, be cue Call_Master, simultaneously according to the direct visit store operation information of accepting, send activation bit to main interface and comprise read-write state signal HWRITE_root, this moment, HWRITE_root was " 0 ", and expression is from the target device reading of data; Transmission size of data signal HSIZE_root, transport-type signal HBURST_root, expression burst transfer; Current transmission state signal HTRANS_root comprises discontinuously, continuously, waits for, and busy four kinds of states, be continuous state this moment; Source device address signal Internal_addr adds that by direct visit memory controller the side-play amount (offset) that is no more than the transmission size of data constitutes on source device address signal base Internal_base_addr; Destination device address signal HADDR adds that by direct visit memory controller the side-play amount (offset) that is no more than the transmission size of data constitutes on destination device address signal base External_base_addr equally;
Step 25, advanced microcontroller bus architecture main interface receives enabled instruction and activation bit starts the bus data transmission that directly access is stored, directly the access storage control is according to learning it is read operation with target device with the read-write state signal value of target device for " 0 ", therefore directly the access storage control is in the state that advanced microcontroller bus architecture main interface transmits data that receives of waiting for, and advanced microcontroller bus architecture main interface learns it is from the target device reading out data according to the read-write state signal HWRITE_root of activation bit for " 0 ", therefore send direct access storage control to from the bus reading external data, directly the access storage control receives external data, write external data by cache controller to data buffer, from bus reading out data process, advanced microcontroller bus architecture main interface can return transmission state response signal HRESP to direct access storage control, if directly accessing the transmission state response signal that storage control receives is OK, then can keep proceeding of advanced microcontroller bus architecture main interface reading external data; If directly accessing the transmission state response signal that storage control receives is ERROR, directly the access storage control can send command for stopping to advanced microcontroller bus architecture main interface and stop advanced microcontroller bus architecture main interface reading external data, and to send direct access event memory signal DMA_result to IP core be that the information of failure represents directly to access the storage operation failure;
Step 26, after advanced microcontroller bus architecture main interface reads external data and finishes, the direct visit of advanced microcontroller bus architecture main interface notice memory controller reads external data and finishes, and when direct visit memory controller by cache controller after data buffer writes external data and finishes, directly visit memory controller to intellectual property core send direct visit storage stop signal DMA_end and directly visit event memory signal DMA_result be that the storage operation success is directly visited in the information representation of success.
From above two embodiments as can be seen, by further optimization to the direct access to storage device structure of the present invention, increase data buffer and realize the storage of internal data and external data, increase cache controller and realize that read-write to the data buffer makes direct visit storage operation process for the preservation of internal data and external data with handle convenient.Make the signal classification of intellectual property core reception and generation clearer and more definite by in intellectual property core, adding register group.
Similarly, directly access further specializing of methods of storage operating by the present invention, so that the operating process orderliness is clearer, the operation purpose in each step is also clearer and more definite for the careful division of system signal, operation information and activation bit state.
Further, in order to make structure more complete, the direct access to storage device of the present invention can also increase advanced microcontroller bus architecture as shown in Figure 5 and realize that from the signalling channel of interface 7 and cache controller 4 CPU is by the function of advanced microcontroller bus architecture from the read-write operation of interface 7 and 4 pairs of data buffers 3 of cache controller; Increase register group 2 and realize that from the signalling channel of interface 7 intellectual property core carries out interrupt operation by advanced microcontroller bus architecture from interface 7 notice CPU to advanced microcontroller bus architecture, the signalling channel that refreshes the function of CPU state and increase intellectual property core 1 and cache controller 4 realizes that the data of intellectual property core and cache controller get in touch with.But the additional increase of above structure is not that to finish direct access storage operation necessary.
In sum, the direct access to storage device of the present invention by with intellectual property core, directly to visit memory controller, advanced microcontroller bus architecture main interface and advanced microcontroller bus architecture integrated from interface, make intellectual property core can by Advanced High-performance Bus directly with bus on equipment realize directly visiting storage operation.Directly access methods of storage operating by the present invention again and on Advanced High-performance Bus, realize in higher efficiency described direct access storage operation.Those skilled in the art can be more easily corresponding to making expansion on the basis that the present invention describes, and for example, the bus apparatus described in the present invention can be equipment or the memory with apparatus of the present invention structure.Similarly, those skilled in the art also can be easy to obtain the conclusion that the present invention is applicable to AS bus (ASB, Advanced System Bus).