CN101188143B - Hardware writing protection method, single board and device - Google Patents
Hardware writing protection method, single board and device Download PDFInfo
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- CN101188143B CN101188143B CN2007103021033A CN200710302103A CN101188143B CN 101188143 B CN101188143 B CN 101188143B CN 2007103021033 A CN2007103021033 A CN 2007103021033A CN 200710302103 A CN200710302103 A CN 200710302103A CN 101188143 B CN101188143 B CN 101188143B
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Abstract
The invention example discloses a write-protect method of hardware. A space of a flash memory is divided into subspaces by the write-protect method of hardware, and the subspaces comprise a write-protect subspace and a write-protect free subspace to save corresponding relation between each subspace and an address signal. The write-protect method of hardware comprises the steps that the coding to the receiving address signal is performed; the data is not written into the subspace corresponding to the address signal when judging that the subspace corresponding to the address signal is the write-protect subspace; the data is written into the subspace corresponding to the address signal when the subspace corresponding to the address signal is the write-protect free subspace. The embodiment of the invention also discloses a write-protect veneer and a device of hardware. The embodiment of the invention realizes the functions of the flash memory and a read only memory on a chip of the flash memory, and the cost is reduced.
Description
Technical field
The present invention relates to data storage technology, relate in particular to method, veneer and the device of hardware writing protection.
Background technology
Flash memory (FLASH Memory) is fast wiping type storer, is easy to wipe and rewrite, and has the characteristics of quick access, and still can keep institute's stored data signal under powering-off state, and power consumption is little.Because the distinct advantages of FLASH Memory applies to make on the veneer that upgrading is very convenient.And FLASH Memory can be used as the solid-state large-capacity storer, and its integrated level improves constantly, and price reduces.
And the importing ROM (read-only memory) of using on the veneer (BOOTROM, BOOT Read-OnlyMemory) is read-only, can not rewrite, and can't adapt to online upgrading.
At present, BOOTROM that uses on the veneer and FLASH Memory separate, and realize BOOTROM function and FLASH Memory function respectively by two chips, and cost is higher, described BOOTROM function comprises read-only function, and described FLASH Memory function comprises read-write function.
Summary of the invention
The embodiment of the invention provides a kind of method of hardware writing protection, and this method can realize reducing cost BOOTROM function and FLASH Memory function on a slice FLASHMemory chip.
The embodiment of the invention provides a kind of veneer of hardware writing protection, and this veneer can be realized reducing cost BOOTROM function and FLASH Memory function on a slice FLASHMemory chip.
The embodiment of the invention provides a kind of device of hardware writing protection, and this device can be realized reducing cost BOOTROM function and FLASH Memory function on a slice FLASHMemory chip.
A kind of method of hardware writing protection, this method is divided into the subspace with FLASH Memory space, comprises write-protected subspace and does not have write-protected subspace, and preserve the corresponding relation between each sub spaces and the address signal, this method comprises:
The address signal that receives is deciphered; judge the address signal correspondence be write-protected subspace the time; data are not write the subspace corresponding with address signal, and corresponding is when not having write-protected subspace, and data are write the subspace corresponding with address signal.
A kind of veneer of hardware writing protection is characterized in that, this veneer comprises the device and the flash memory of hardware writing protection;
The device of described hardware writing protection, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, data are not write, corresponding is when not having write-protected subspace, data are write described write-protected subspace and not have write-protected subspace be each subspace in FLASHMemory space;
Described FLASH Memory is used to receive the data that the device of described hardware writing protection writes.
A kind of device of hardware writing protection, this device comprise address decoding judge module and data writing module;
Described address decoding judge module, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, the control data writing module does not write data the subspace corresponding with address signal, corresponding is when not having write-protected subspace, and the control data writing module writes the subspace corresponding with address signal with data;
The data writing module writes the described subspace corresponding with address signal with data under the control of address decoding judge module, data are not write under the control of address decoding judge module.
From such scheme as can be seen; by the embodiment of the invention scheme FLASH Memory chip is carried out write-protect control; judge the corresponding write-protected subspace of address signal; then data are not write the subspace corresponding with address signal; judging the address signal correspondence does not have write-protected subspace, then data is write the subspace corresponding with address signal.Like this, on a slice FLASH Memory chip, realize BOOTROM function and FLASH Memory function simultaneously, reduced cost.
Description of drawings
Fig. 1 is the method exemplary process diagram of embodiment of the invention hardware writing protection;
Fig. 2 is the method flow diagram example of embodiment of the invention hardware writing protection;
Fig. 3 is the single plate structure synoptic diagram of embodiment of the invention hardware writing protection.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
Referring to Fig. 1, method exemplary process diagram for embodiment of the invention hardware writing protection, this method is divided into the subspace with FLASH Memory space in advance, comprise the write-protected subspace of needs and need not write-protected subspace, the write-protected subspace of wherein said needs is read-only space, can not write, described to need not write-protected subspace be the readable space of writing; Preserve the corresponding relation between each sub spaces and the address signal.Here, need not write-protected subspace and be called and do not have write-protected subspace, the write-protected subspace of described needs is called write-protected subspace described.
This method may further comprise the steps:
Embodiment of the invention scheme is divided into FLASH Memory chip write-protected subspace and does not have write-protected subspace, has realized FLASH Memory function and BOOTROM function on a slice FLASH Memory chip.But FLASH Memory chip can also be divided into write-protected subspace, not have the write-protect subspace of write-protected subspace and release, this moment is when judging in the step 101, also comprise: but judge the whether write-protect subspace of correspondence release of address signal, but if judge the write-protect subspace of correspondence release, judge then whether the sign receive is with identical with the corresponding release sign of the address signal that receives, if then this space is a released state, execution in step 103; Otherwise this space is a locking state, and then execution in step 102.
In the prior art, BOOTROM is read-only, can not rewrite the functional requirement in the time of can't realizing ageing state.So-called ageing state, the state of veneer when testing exactly, when needing in the test process BOOTROM rewritten, the situation that the read-only characteristics that occur because of BOOTROM can't be satisfied the demands.
For addressing the above problem, this method is taked to carry out following steps before step 101: judge whether veneer is in ageing state, if, execution in step 103, otherwise, execution in step 101.Like this, when veneer is in ageing state, just can read and write whole FLASH Memory space.
Below by Fig. 2 the method for embodiment of the invention hardware writing protection is illustrated, in advance FLASH Memory space is divided into the subspace, but comprise the write-protect subspace of write-protected subspace release and do not have write-protected subspace, preserve the corresponding relation between each sub spaces and the address signal; But the write-protect subspace of release is divided into zone more than, and release sign of each zone correspondence is preserved each zone and release sign corresponding relation before in advance.
This method may further comprise the steps:
Judge whether veneer is in ageing state and judges just whether veneer is in test mode, during judgement, can pass through central processing unit (CPU, Central Processing Unit) the test mode information of Chuan Songing is obtained present single board state, also can obtain the information whether veneer is in test mode by alternate manner.
The described address signal that receives is the address signal of visit FLASH Memory chip, as, can be to send from CPU.
Write-protected subspace has the BOOTROM function, is read-only space, can not rewrite it; Do not have write-protected subspace to have FLASH Memory function, be read-write space; In order to use FLASH Memory space more neatly; but the embodiment of the invention also is provided with the write-protect subspace of release; can read and write it when but the write-protect subspace of release is in released state, can only read it when being in locking state, can not carry out data and write.
When but needs are visited the write-protect subspace of release, in the Input Address signal, also need import sign.
But the write-protect subspace of release is divided into several regions, respectively write-protect is carried out in each zone, like this, but just can realize multiple flexible demands in the write-protect subspace of release.
Referring to Fig. 3, be the single plate structure synoptic diagram of embodiment of the invention hardware writing protection, this veneer comprises the device and the FLASH Memory of hardware writing protection;
The device of described hardware writing protection, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, data are write, corresponding is when not having write-protected subspace, data are not write described write-protected subspace and not have write-protected subspace be each subspace of FLASHMemory;
Described FLASH Memory is used to receive the data that the device of described hardware writing protection writes.
Device to hardware writing protection describes below, and this device comprises address decoding judge module and data writing module;
Described address decoding judge module, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, the control data writing module does not write data the subspace corresponding with address signal, corresponding is when not having write-protected subspace, and the control data writing module writes the subspace corresponding with address signal with data;
The data writing module writes the described subspace corresponding with address signal with data under the control of address decoding judge module, data are not write under the control of address decoding judge module.
Alternatively; but the subspace of described address signal correspondence comprises the write-protect subspace of release; this moment, this device comprised release sign judge module; be used for the startup command that receiver address decoding judge module transmits; judge whether the corresponding release sign of sign that receives and the address signal that receives is identical; the order that is used to start release sign judge module that sends to release sign judge module when but described startup command is judged the write-protect subspace of the address signal correspondence release that receives for the address decoding judge module; if; then the control data writing module writes the subspace corresponding with address signal with the data that receive; otherwise the control data writing module does not write the data that receive.
Alternatively, this device comprises the ageing state judge module, is used to judge whether veneer is in ageing state, if, then the control data writing module writes the subspace corresponding with address signal with the data that receive, otherwise, send address signal to the address decoding judge module.
This device can be realized by the synthetic combinational logic circuit of separating component, also can pass through CPLD (CPLD, Complex Programmble Logic Device)/simple programmable logical device (EPLD, Easy Programmble Logic Device) realizes.
The characteristics that the embodiment of the invention is big according to FLASH Memory capacity, price is low; by the hardware writing protection device FLASH Memory chip is carried out write-protect control; like this; only need in veneer, to add the device of hardware writing protection; just can realize BOOTROM function and FLASH Memory function simultaneously at a slice FLASH Memory chip; thereby, replaced BOOTROM and the FLASH Memory chip on the veneer with a slice FLASH Memory chip, reduced cost.And, realized read-write to the BOOTROM space, can satisfy online upgrading, multinomial function such as aging.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the method for a hardware writing protection is characterized in that, flash memory space is divided into the subspace, comprises write-protected subspace and does not have write-protected subspace, and preserve the corresponding relation between each sub spaces and the address signal, this method comprises:
The address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, data are not write the subspace corresponding with address signal, and corresponding is when not having write-protected subspace, and data are write the subspace corresponding with address signal;
But described subspace also comprises the write-protect subspace of release; described the address signal that receives is deciphered after; this method comprises: but judge the address signal correspondence be the write-protect subspace of release the time; judge then whether the corresponding release sign of sign that receives and the address signal that receives is identical; if; then data are write the subspace corresponding with address signal, otherwise, data are not write the subspace corresponding with address signal.
2. the method for claim 1 is characterized in that, but the write-protect subspace of described release is more than one zone, the corresponding release sign in each zone.
3. method as claimed in claim 1 or 2 is characterized in that, described the address signal that receives is deciphered before, this method comprises:
Judge whether veneer is in ageing state, if, then data are write the subspace corresponding with address signal, otherwise, the described step that the address signal that receives is deciphered carried out.
4. the device of a hardware writing protection is characterized in that, this device comprises address decoding judge module and data writing module;
Described address decoding judge module, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, the control data writing module does not write data the subspace corresponding with address signal, corresponding is when not having write-protected subspace, and the control data writing module writes the subspace corresponding with address signal with data;
The data writing module writes the described subspace corresponding with address signal with data under the control of address decoding judge module, data are not write under the control of address decoding judge module;
But the subspace of described address signal correspondence comprises the write-protect subspace of release; this device comprises release sign judge module; be used for the startup command that receiver address decoding judge module transmits; judge whether the corresponding release sign of sign that receives and the address signal that receives is identical; the order that is used to start release sign judge module that sends to release sign judge module when but described startup command is judged the write-protect subspace of the address signal correspondence release that receives for the address decoding judge module; if; then the control data writing module writes the subspace corresponding with address signal with the data that receive; otherwise the control data writing module does not write the data that receive.
5. device as claimed in claim 4, it is characterized in that, this device comprises the ageing state judge module, be used to judge whether veneer is in ageing state, if, then the control data writing module writes the subspace corresponding with address signal with the data that receive, otherwise, send address signal to the address decoding judge module.
6. the veneer of a hardware writing protection is characterized in that, this veneer comprises the device and the flash memory of hardware writing protection;
The device of described hardware writing protection, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, data are not write, corresponding is when not having write-protected subspace, data are write described write-protected subspace and not have write-protected subspace be each subspace of flash memory space;
Described flash memory is used to receive the data that the device of described hardware writing protection writes;
The device of described hardware writing protection comprises address decoding judge module and data writing module;
Described address decoding judge module, be used for the address signal that receives is deciphered, judge the address signal correspondence be write-protected subspace the time, the control data writing module does not write data the subspace corresponding with address signal, corresponding is when not having write-protected subspace, and the control data writing module writes the subspace corresponding with address signal with data;
The data writing module writes the described subspace corresponding with address signal with data under the control of address decoding judge module, data are not write under the control of address decoding judge module;
But the subspace of described address signal correspondence comprises the write-protect subspace of release; the device of described hardware writing protection comprises release sign judge module; be used for the startup command that receiver address decoding judge module transmits; judge whether the corresponding release sign of sign that receives and the address signal that receives is identical; the order that is used to start release sign judge module that sends to release sign judge module when but described startup command is judged the write-protect subspace of the address signal correspondence release that receives for the address decoding judge module; if; then the control data writing module writes the subspace corresponding with address signal with the data that receive; otherwise the control data writing module does not write the data that receive.
7. veneer as claimed in claim 6; it is characterized in that; the device of described hardware writing protection comprises the ageing state judge module; be used to judge whether veneer is in ageing state; if; then the control data writing module writes the subspace corresponding with address signal with the data that receive, otherwise, send address signal to the address decoding judge module.
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| CN2007103021033A CN101188143B (en) | 2007-12-14 | 2007-12-14 | Hardware writing protection method, single board and device |
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| CN2007103021033A CN101188143B (en) | 2007-12-14 | 2007-12-14 | Hardware writing protection method, single board and device |
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| CN101188143B true CN101188143B (en) | 2010-10-13 |
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| CN109753448A (en) * | 2017-11-03 | 2019-05-14 | 展讯通信（上海）有限公司 | Memory read-write guard method and device |
| CN112118246B (en) * | 2020-09-11 | 2022-04-19 | 北京微密科技发展有限公司 | Block chain trusted storage execution hardware environment based on converged memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345413A (en) * | 1993-04-01 | 1994-09-06 | Microchip Technology Incorporated | Default fuse condition for memory device after final test |
| US6321314B1 (en) * | 1999-06-09 | 2001-11-20 | Ati International S.R.L. | Method and apparatus for restricting memory access |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345413A (en) * | 1993-04-01 | 1994-09-06 | Microchip Technology Incorporated | Default fuse condition for memory device after final test |
| US6321314B1 (en) * | 1999-06-09 | 2001-11-20 | Ati International S.R.L. | Method and apparatus for restricting memory access |
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