CN101184071B - Blind SNR estimating method based on pseudo-error rate statistics - Google Patents

Blind SNR estimating method based on pseudo-error rate statistics Download PDF

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CN101184071B
CN101184071B CN2007101799717A CN200710179971A CN101184071B CN 101184071 B CN101184071 B CN 101184071B CN 2007101799717 A CN2007101799717 A CN 2007101799717A CN 200710179971 A CN200710179971 A CN 200710179971A CN 101184071 B CN101184071 B CN 101184071B
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詹亚锋
邢腾飞
包建荣
陆建华
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Tsinghua University
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Abstract

The invention relates to a blind signal-to-noise ratio estimation method based on pseudo bit error rate statistic, belonging to a technical field of signal-to-noise ratio estimation in digital communication. The invention is characterized in comprising the following steps: baseband processing, discretization filter match, eliminating existed carrier wave frequency, phase error and timing error; selecting decision point by decision device, and pseudo bit error rate statistic and signal-to-noise ratio mapping. The invention performs pseudo bit error rate statistic by utilizing the message of multi sampling points in each modulation symbol of discretization system, and again performs one-to-one mapping by utilizing corresponding relation between the pseudo bit error rate and the signal-to-noise ratio, thereby obtaining signal-to-noise ratio estimation value. The invention is applicable for BPSK and QPSK modulation signal; no additional training sequences are needed, and can perform the signal-to-noise ratio estimation at lower complexity and reasonable performance and is suitable for various occasions where the signal-to-noise ratio estimation is required.

Description

Blind SNR estimating method based on pseudo-error rate statistics
Technical field
The present invention relates to a kind of blind SNR estimating method based on pseudo-error rate statistics, be applicable to BPSK and qpsk modulation signal, need not extra expenses such as training sequence, can realize the estimation of signal to noise ratio with very low complexity and rational performance, belong to signal-to-noise ratio (SNR) estimation technical field in the digital communication.
Background technology
In most of digital communication systems, tend to introduce noise in the signal that receiver is received.The ratio of received signal and noise power is defined as signal to noise ratio, can be used as the important tolerance of performance index of communication system such as the decision error rate, frame error rate.In addition, in order to realize optimum performance, key algorithm in many communication systems and system unit need be known the information of signal to noise ratio.For example, chnnel codings such as low density parity check code need accurately that signal to noise ratio reaches best decoding threshold simultaneously with the avoidant property loss of energy; And modulation in the adaptive link control and coded system choose the quantitative description that also needs channel quality, the i.e. information of signal to noise ratio; In addition, signal to noise ratio also plays a part decision transmitter through-put power in the power control of spread spectrum communication system.Therefore, the application demand of a series of reality has promoted the research of signal-to-noise ratio estimation algorithm.
The signal value that signal-to-noise ratio estimation algorithm utilizes one section interval inner receiver to observe usually, by specific computing with the structure statistic as the estimation of signal to noise ratio.The signal-to-noise ratio estimation algorithm that has multiple effective digital modulation signals at present in the document.These algorithms mainly can be divided into three major types:
The first kind is a maximum likelihood estimate, and its main feature is that its statistic is constructed by the statistical signal treatment theory of strictness, function admirable and be easy to the assessment.The limitation of this type of algorithm is that the form of its statistic is often comparatively complicated, thereby computation complexity is very high; If introduce iteration structure in order to improve performance, then complexity can be higher.So being unsuitable for the hardware-efficient of real system, realizes maximum likelihood algorithm.
Second class is the square estimation technique, and its main feature is based on the structure that experience is carried out statistic, and its each rank square computing by received signal obtains moderate performance.The limitation of this type of algorithm is that the structure of its statistic is strict inadequately, is difficult to reach theoretical optimal performance by rule of thumb; Wherein better algorithm tends to use the High Order Moment (as six rank, eight rank squares etc.) of signal, and this will bring high computational complexity, and also real system is unaffordable often.
The 3rd class is the frequency domain estimation technique, and its main feature is to utilize the discrete Fourier transform of signal that it is converted to frequency domain, constructs statistic then and carries out signal-to-noise ratio (SNR) estimation.It is slightly poor that its performance is compared preceding two class algorithms, and it is advantageous that the bigger frequency departure of characteristics antagonism that can utilize frequency domain data exclusive.The limitation of this type of algorithm is that the implementation complexity of discrete Fourier transform is very high, can bring bigger burden to real system equally.
In addition, these signal-to-noise ratio estimation algorithms also have the branch that training sequence auxiliary (DA) and non-training sequence are assisted (NDA) more than.The former inserts one section known training sequence of receiver section in the transmission data sequence, so that receiver carries out the structure of signal to noise ratio statistic; And the latter is also referred to as busy signal-to-noise ratio estimation algorithm.The DA algorithm performance is better than NDA, and its cost of paying then is because the reduction of the effective transmission speed that the expense of training sequence is introduced.
In summary, the main deficiency that existing signal-to-noise ratio estimation algorithm exists is that computational complexity is too high, realizes paying very big cost in real system.
Summary of the invention
The objective of the invention is to propose a kind of blind SNR estimating method based on pseudo-error rate statistics, utilized the information of a plurality of sampled points in each modulation symbol of discrete system to carry out pseudo-error rate statistics, utilize corresponding relation dull between pseudo-error rate and the signal to noise ratio to shine upon one by one again, thereby obtain the estimated value of signal to noise ratio.This method is applicable to BPSK and qpsk modulation signal, need not extra expenses such as training sequence, can realize the estimation of signal to noise ratio with very low complexity and rational performance, is applicable to all kinds of application scenarios that need signal-to-noise ratio (SNR) estimation.
The invention is characterized in that described method contains following steps successively:
Step (1): received signal at first through a base band processor, obtains baseband modulation signal by processing.For the baseband signal in the described received signal, comprise base band bpsk signal and base band QPSK signal, this base band processor is not done any processing, directly passes through; For the bandpass signal in the described received signal, comprise logical bpsk signal of band and the logical QPSK signal of band, making quadrature frequency conversion with the quadrature frequency conversion circuit in this base band processor handles, obtain having the logical BPSK complex signal of band after the base bandization of carrier frequency and phase deviation, perhaps the logical QPSK complex signal of the band after the base bandization.
The base band BPSK received signal of input is a real signal, comprises a circuit-switched data information; The base band QPSK received signal of input is a complex signal, comprises I, Q two paths of data information.The band of input connects to collect mail and number is real signal, and BPSK is comprised a circuit-switched data information, and QPSK is comprised I, Q two paths of data information.
Step (2): the baseband signal of the base band processor of step (1) output or the bandpass signal after the base bandization at first through a discretization processor, are carried out discretization to signal and handle.This processor is the integral multiple of symbol rate and multiple greater than 2 discrete signal to sample rate, does not do any processing and directly passes through; Continuous signal is carried out the sampling that sample rate is every symbol N sampled point, to obtain corresponding discrete signal.This discrete sampling is realized by analog to digital converter (ADC).Wherein, establish N for greater than 2 natural number; The value of N is unsuitable excessive, and promptly the sample rate of discretization device should be realized by the ADC chip under the current device level;
Step (3): the base band discrete signal of the discretization processor of step (2) output or the logical discrete signal of the band after the base bandization are carried out matched filtering; The impulse response of this matched filter is for adopting the root-raised cosine pulse of identical rolloff-factor α, wherein 0≤α≤1 with transmitting.This impulse sampling rate is similarly N, and its impulse response sequence is a sequence of real numbers { h -KN..., h -1, h 0, h 1..., h KN, its expression formula is: N=-KN ... ,-1,0,1 ..., KN, wherein:
Figure GSB00000567199700032
Be the continuous impulse of root-raised cosine signal,
Figure GSB00000567199700033
Represent continuous inverse Fourier transform, T sBe symbol period, and the expression formula of the Fourier transform H (ω) of h (t) is:
H ( &omega; ) = S 0 , 0 &le; | &omega; | < &pi; ( 1 - &alpha; ) T s S 0 2 { 1 - sin [ T s 2 &alpha; ( &omega; - &pi; T s ) ] } , &pi; ( 1 - &alpha; ) T s &le; | &omega; | &le; &pi; ( 1 + &alpha; ) T s 0 , | &omega; | > &pi; ( 1 + &alpha; ) T s
S wherein 0Be a constant, hereinafter will provide definite method of its value.K is the natural number greater than 1, and is unsuitable excessive, gets 1<K≤10 usually, thereby simultaneously the resource overhead of matched filter is controlled in the reasonable range in that performance loss is insignificant; 2K represents the number of symbols that this matched filter impulse response is occupied.This pulse has unit energy, promptly
Figure GSB00000567199700035
Event is obtained according to above-mentioned steps and is contained S 0{ h -KN..., h -1, h 0, h 1..., h KNAfter, can calculate S 0Value.Remember h in addition l=0, l is absolute value all integers greater than K;
Step (4): the baseband signal matched filter output that step (3) is obtained, after the matched filtering or the bandpass signal after the base bandization be through a synchronizer, the carrier frequency, phase deviation and the timing offset that exist with correction.When the received signal of the input of step (1) was baseband signal, this synchronizer adopted regularly correcting method that signal is handled; And when it was bandpass signal, this synchronizer adopted carrier wave and timing correcting method that signal serial is successively handled.Obtain not having the baseband signal of carrier frequency and phase deviation and timing offset thus, this burst can be designated as ..., y -1, y 0, y 1..., be real sequence for bpsk signal, be complex sequences for the QPSK signal.Carrier wave is corrected with the step of regularly correcting as follows:
Step (4.1): synchronizer adopts the first timing synchronous circuit to correct timing offset to the baseband signal of exporting from the matched filter of step (3), obtains not having the baseband signal of timing offset, be designated as ... .., y -1, y 0, y 1... ..} is real sequence for BPSK, and QPSK is a complex sequences, and it is synchronous that this first timing synchronous circuit carries out timing successively according to the following steps;
Step (4.1.1): the real part I ' of the baseband signal of after described matched filtering, exporting (m) in, the signal I ' (n of the optimum sampling point position of each symbol current selected 0), the signal I ' (n of previous sampled point 0-1), the signal I ' (n of a sampled point afterwards 0+ 1) sends into a timing error extractor, calculate and obtain a signal of timing error ε by following formula t(n), n is the sampled point sequence number:
ε t(n)=sign (I ' (n 0)) * [I ' (n 0+ 1)-I ' (n 0-1)], symbol sign is a sign function, and value is 1 during the independent variable nonnegative number, and value is-1 during for negative;
Wherein, when starting working in system, this optimum sampling point position is chosen arbitrarily;
Step (4.1.2): described signal of timing error ε t(n) send into the timing error value E that a single order digital lowpass loop filter obtains accumulating t(n), E t(n)=E t(n-1)+K 1ε t(n)
K 1Be filter factor, K 1<1;
Step (4.1.3): judge accumulated error value E with a comparator t(n) whether reach the threshold values of setting, if reach the threshold values of setting, then, send an optimum sampling point position simultaneously and adjust signal, the position of control optimum sampling point the accumulated error zero clearing, make its polarity according to accumulated error, if just, then carry the previous unit sampling interval, otherwise, just postpone a unit sampling interval, thereby find optimum sampling point I ' (n 0);
Step (4.2): the carrier synchronization circuit and second that the bandpass signal of synchronizer after to the base bandization of the matched filter of step (3) output adopts serial connection successively regularly synchronous circuit is corrected, with the bandpass signal after the base bandization that obtains not having carrier frequency and phase deviation, be designated as ... .., y -N, y 0, y N... ..} is a real signal for bpsk signal, is complex signal for the QPSK signal, and its correction step is as follows:
Step (4.2.1): the I/Q two-way digital baseband signal I that does not pass through frequency correction that the bandpass signal after the base bandization of the described matched filter of step (4.2) output is comprised Band' (n), Q Band' (n) send into a phase discriminator in the carrier synchronization circuit that comprises the polarity type phase discriminator, extract phase error signal ε as follows c(n):
ε c(n)=I Band' (n) * Q Band' (n), n is the sampler label;
Step (4.2.2): described phase error signal ε c(n) a second order digital loop filters in incoming carrier recovers to encircle carries out filtering, and its sequential is:
The phase error accumulating signal φ (n+1) of n+1 sampled point is:
φ(n+1)=φ(n)+K 1′f(n)+K 2′ε c(n),
The frequency error accumulating signal f (n+1) of n+1 sampled point is:
f(n+1)=f(n)+ε c(n),
Wherein, constant K 1', K 2' be two filtering parameters that are used for frequency, phase place of this second order digital loop filters, as the sample frequency f of analog to digital converter described in the step (2) sDuring much larger than the natural frequency of carrier recovery loop, K 2'=2 η ω nT s, K 1'=ω nT s,
Wherein, ω n=2 π f nBe the natural frequency of described second order digital loop, η is a damping coefficient, T s=1/f s,
Step (4.2.3): the error accumulation signal psi (n+1) that the filtering through step (4.2.2) second order digital loop is obtained is as the input of local digital controlled oscillator NCO in the described carrier synchronization circuit, to adjust the frequency of local oscillation signal;
Step (4.2.4): the I/Q two-way digital baseband signal I that the bandpass signal after the base bandization that is input to the described carrier synchronization circuit of step (4.2) is comprised Band(m), Q Band(m) output signal cos φ (n), the sin φ (n) with local digital controlled oscillator multiplies each other in phase rotation circuit, carries out the phase place rotation, obtains the I/Q two-way digital baseband signal I through frequency correction Band' (m), Q Band' (m):
I Band' (m)=I Band(m) * cos φ (n)+Q Band(m) * sin φ (n),
Q Band' (m)=Q Band(m) * cos φ (n)-I Band(m) * sin φ (n),
The difference of m and n is the computing time-delay of described whole carrier synchronization circuit;
Step (4.2.5):, in the time of one section setting, add up I for bpsk signal Band' (m), Q Band' (m) separately average energy is chosen the wherein a road big useful signal as carrierfree frequency and phase deviation of energy, be sent to second regularly synchronous circuit carry out timing synchronously; For the QPSK signal, directly I Band' (m), Q Band' (m) being sent to the second timing synchronous circuit respectively carries out timing synchronously;
Step (4.2.6): to be sent in the step (4.2.5) second regularly synchronous circuit signal set by step (4.1) described method carry out timing synchronously, the timing offset that exists with correction;
Step (4.2.7): the regularly synchronous baseband signal of process step (4.1), or through step (4.2.1) to step (4.2.6) through carrier frequency and Phase synchronization and correct and regularly synchronous base bandization after bandpass signal be sent to the determination point Chooser, according to the following steps, each modulation symbol is chosen two determination points respectively, divide two-way output, the sample frequency on each road is sampled point of each symbol;
Step (5): the burst that step (4) is obtained is chosen two determination points through a determination point Chooser respectively to each modulation symbol, divides two-way output, and the sample rate on each road is 1 sampled point of every symbol; Wherein one the tunnel is formed by the optimum sampling point of each symbol, does not promptly have the sampled point of intersymbol interference, for ..., y -N, y 0, y N...; Another road is one of other any sampled points of each symbol, promptly has the sampled point of intersymbol interference, for ..., y -N+f, y f, y N+f..., wherein f is a natural number, span is 1 to arrive
Figure GSB00000567199700061
For being not less than
Figure GSB00000567199700062
Smallest positive integral; The position of another road sampled point of the position of optimum sampling point and f the sampled point of delaying time wherein, is provided by the timing synchronous circuit in the step (4);
Step (6): the two-way determination point signal that step (5) is obtained passes through a pseudo-error rate statistics device, carries out the statistics of pseudo-error rate; Here pseudo-error rate refers to the probability that two-way sampled signal court verdict does not wait, promptly opposite polarity probability; Choose M and be the statistics siding-to-siding block length, M is a natural number, gets 10 usually 2~10 3The above order of magnitude is to guarantee estimated accuracy; Then for bpsk signal, the estimated value P of pseudo-error rate PFor:
P P = 1 M &Sigma; l = 0 M - 1 &xi; ( y 1 N , y lN + f ) , Wherein &xi; ( y lN , y lN + f ) = 1 , y lN &times; y lN + f < 0 0 , y lN &times; y lN + f &GreaterEqual; 0 ;
For the QPSK signal, the estimated value P of pseudo-error rate PFor:
P P = 1 2 M &Sigma; l = 0 M - 1 { &xi; ( Re [ y lN ] , Re [ y lN + f ] ) + &xi; ( Im [ y lN ] , Im [ y lN + f ] ) } ,
Wherein function R e represents to get a real, and function Im represents to get the imaginary part of a plural number,
&xi; ( Re [ y lN ] , Re [ y lN + f ] ) = 1 , Re [ y lN ] &times; Re [ y kN + f ] < 0 0 , Re [ y lN ] &times; Re [ y lN + f ] &GreaterEqual; 0 ,
&xi; ( Im [ y lN ] , Im [ y lN + f ] ) = 1 , Im [ y lN ] &times; Im [ y kN + f ] < 0 0 , Im [ y lN ] &times; Im [ y lN + f ] &GreaterEqual; 0 .
Step (7): the estimated value P of the pseudo-error rate that step (6) is obtained PBy a signal to noise ratio mapper, utilize functional relation dull between pseudo-error rate and the signal to noise ratio, obtain the estimated value ρ of signal to noise ratio by numerical method.This numerical method is usually by the realization of tabling look-up, and the pseudo-error rate that calculated in advance is good and the numerical value of signal to noise ratio are stored in the memory, and the pseudo-error rate that utilizes estimation to obtain is searched the signal to noise ratio corresponding with it and got final product.The form of this monotonic function is as follows:
P P = 1 - 1 2 ( 4 &Phi; ( 0 , &infin; , 0 ) + &Psi; ( g 2 , 1 ) + &Psi; ( g 1 , 1 ) + 2 &Psi; ( 1,0 ) ) , Wherein:
&Phi; ( 0 , &infin; , 0 ) = 1 &pi; [ arctan ( 1 - G f 1 + G f ) + arctan ( G f 2 1 - G f 2 ) ] ,
&Psi; ( a , b ) = &Integral; - a 0 &rho; 8 &pi; e - &rho;x 2 2 [ 1 - 2 erfc ( &rho; ( b + G f x ) 2 ( 1 - G f 2 ) ) ] dx , A and b are the limit of integration, and x is an integration variable, and erfc is the complementary error function, and it is defined as
Figure GSB000005671997000611
T is an independent variable, and z is an integration variable, g 1=G f+ G F-N, g 2=G f-G F-N, G f = &Sigma; k = - KN KN h k h k + f , G f - N = &Sigma; k = - KN KN h k h k + f - N .
The blind SNR estimating method that the present invention proposes based on pseudo-error rate statistics, its major advantage comprises: computation complexity is very low, is easy to realize, thereby need not that training sequence is auxiliary a higher efficiency of transmission, algorithm for estimating such as performance and maximum likelihood is suitable, is applicable to all kinds of concrete application.For discrete receiver, the operand of pseudo-error rate statistics is very little, only need utilize the information of a plurality of sampled points of every symbol, and the similarities and differences and the stored counts of judgement two-way sampled signal polarity get final product; And the prior computing by function, store with tabling look-up and combine, the mapping from the pseudo-error rate to the signal to noise ratio only needs simple table lookup operation to finish.
Description of drawings
Fig. 1 is the FB(flow block) of signal-noise ratio estimation method.
Fig. 2 is the schematic block circuit diagram of SNR estimator system.
Fig. 3 is the schematic block circuit diagram of base band processor.
Fig. 4 is the schematic block circuit diagram of discretization processor.
Fig. 5 is the composition frame chart of synchronizer.
Fig. 6 is regularly the schematic block circuit diagram of synchronous circuit.
Fig. 7 is the schematic block circuit diagram of carrier synchronization circuit.
Fig. 8 is the schematic block circuit diagram of determination point Chooser.
Embodiment
Below in conjunction with accompanying drawing, introduce content of the present invention in detail:
Fig. 1 is the FB(flow block) of signal-noise ratio estimation method.As shown in Figure 1.The signal that receiver receives obtains not having the discrete sample signals sequence of frequency and timing offset after successively through base band processor, discretization processor, matched filtering, operation such as synchronous.This sequence obtains the determination point sequence of two-way sample rate equal symbol rate through the determination point selector; This sequence obtains the estimated value of pseudo-error rate again by the pseudo-error rate statistics device.At last should value through signal to noise ratio mapper, obtain the estimated signal to noise ratio that goes out.
Fig. 2 is the schematic block circuit diagram of SNR estimator system.Corresponding with Fig. 1, the signal that receives once through realizing each circuit module of signal-noise ratio estimation method, finally obtains estimated signal to noise ratio.
Below be the arthmetic statement and the specific implementation method thereof of each several part:
Fig. 3 is the schematic block circuit diagram of base band processor.As shown in Figure 2, received signal obtains baseband modulation signal through the base band processor by processing; The specific implementation method is:
(1) if the signal that receives is base band BPSK or QPSK signal, then this base band processor is not done any processing, directly passes through;
(2) if being band, the signal that receives leads to BPSK or QPSK signal, then making quadrature frequency conversion with the quadrature frequency conversion circuit in this base band processor handles, obtain having the logical BPSK complex signal of band after the base bandization of carrier frequency and phase deviation, perhaps the logical QPSK complex signal of the band after the base bandization;
The base band BPSK received signal of input is a real signal, comprises a circuit-switched data information; The base band QPSK received signal of input is a complex signal, comprises I, Q two paths of data information.The band of input connects to collect mail and number is real signal, and BPSK is comprised a circuit-switched data information, and QPSK is comprised I, Q two paths of data information.
Fig. 4 is the schematic block circuit diagram of discretization processor.As shown in Figure 3, the bandpass signal after baseband signal or the base bandization obtains the base band discrete signal through the discretization processor by processing; The specific implementation method is:
(1) if the signal that receives is a sample rate is the integral multiple of symbol rate and multiple greater than 2 discrete sample signals, then this processor is not done any processing to signal and is directly passed through;
(2) if the signal that receives is a continuous signal, then this processor carries out the sampling that sample rate is every symbol N sampled point to signal, to obtain corresponding discrete signal.This discrete sampling is realized by analog to digital converter (ADC).Wherein, establish N for greater than 2 natural number; The value of N is unsuitable excessive, and promptly the sample rate of discretization device should be realized by the ADC chip under the current device level.
Subsequently, the logical discrete signal of base band discrete signal that the discretization processor obtains or the band after the base bandization carries out matched filtering through a matched filter to signal; The impulse response of this matched filter is for adopting the root-raised cosine pulse of identical rolloff-factor α, wherein 0≤α≤1 with transmitting.This impulse sampling rate is similarly N, and its impulse response sequence is a sequence of real numbers { h -KN..., h -1, h 0, h 1..., h KN, its expression formula is:
Figure GSB00000567199700081
N=-KN ... ,-1,0,1 ..., KN, wherein:
Figure GSB00000567199700082
Be the continuous impulse of root-raised cosine signal,
Figure GSB00000567199700083
Represent continuous inverse Fourier transform, T sBe symbol period, and the expression formula of the Fourier transform H (ω) of h (t) is:
H ( &omega; ) = S 0 , 0 &le; | &omega; | < &pi; ( 1 - &alpha; ) T s S 0 2 { 1 - sin [ T s 2 &alpha; ( &omega; - &pi; T s ) ] } , &pi; ( 1 - &alpha; ) T s &le; | &omega; | &le; &pi; ( 1 + &alpha; ) T s 0 , | &omega; | > &pi; ( 1 + &alpha; ) T s
S wherein 0Be a constant, hereinafter will provide definite method of its value.K is the natural number greater than 1, and is unsuitable excessive, gets 1<K≤10 usually, thereby simultaneously the resource overhead of matched filter is controlled in the reasonable range in that performance loss is insignificant; 2K represents the number of symbols that this matched filter impulse response is occupied.This pulse has unit energy, promptly
Figure GSB00000567199700091
Event is obtained according to above-mentioned steps and is contained S 0{ h -KN..., h -1, h 0, h 1..., h KNAfter, can calculate S 0Value.Remember h in addition l=0, l is absolute value all integers greater than K;
Fig. 5 is the composition frame chart of synchronizer.As shown in Figure 5, the baseband signal after the matched filtering or the bandpass signal after the base bandization be through synchronizer, the carrier frequency, phase deviation and the timing offset that exist with correction; The specific implementation method is:
(1) when the signal of receiver input is baseband signal, this synchronizer to signal adopt first regularly synchronous circuit signal is handled, obtaining not having the baseband signal of timing offset, this burst can be designated as ..., y -1, y 0, y 1..., be real sequence for bpsk signal, be complex sequences for the QPSK signal;
(2) when the signal of receiver input is bandpass signal, this synchronizer adopts the carrier synchronization circuit and the second timing synchronous circuit that signal is handled, obtaining not having the baseband signal of carrier frequency and phase deviation and timing offset, this burst can be designated as ..., y -N, y 0, y N..., be real sequence for bpsk signal, be complex sequences for the QPSK signal.Carrier wave and timing are corrected and are realized with the order serial.
Fig. 6 is first and second regularly schematic block circuit diagram of synchronous circuit.As shown in Figure 6, the baseband signal after the matched filtering or through the bandpass signal after the base bandization after carrier frequency and the phase correction through synchronizer regularly, the timing offset that exists with correction; The specific implementation method is:
(1) baseband signal of after matched filtering, exporting or through the real part I ' of the bandpass signal after the base bandization after carrier frequency and the phase correction (m) in, the signal I ' (n of the optimum sampling point position of each symbol current selected 0), the signal I ' (n of previous sampled point 0-1), the signal I ' (n of a sampled point afterwards 0+ 1) sends into a timing error extractor, calculate and obtain a signal of timing error ε by following formula t(n), n is the sampled point sequence number:
ε t(n)=sign (I ' (n 0)) * [I ' (n 0+ 1)-I ' (n 0-1)], symbol sign is a sign function, and value is 1 during the independent variable nonnegative number, and value is-1 during for negative;
Wherein, when starting working in system, this optimum sampling point position is chosen arbitrarily;
(3) described signal of timing error ε t(n) send into the timing error value E that a single order digital lowpass loop filter obtains accumulating t(n), E t(n)=E t(n-1)+K 1ε t(n), K 1Be filter factor, K 1<1;
(3) judge accumulated error value E with a comparator t(n) whether reach the threshold values of setting, if reach the threshold values of setting, then, send an optimum sampling point position simultaneously and adjust signal, the position of control optimum sampling point the accumulated error zero clearing, make its polarity according to accumulated error, if just, then carry the previous unit sampling interval, otherwise, just postpone a unit sampling interval, thereby find optimum sampling point I ' (n 0).
Fig. 7 is the schematic block circuit diagram of carrier synchronization device.As shown in Figure 7, bandpass signal after the base bandization after the matched filtering is through the carrier synchronization device, the carrier frequency, the phase deviation that exist with correction; The specific implementation method is:
(1) the I/Q two-way digital baseband signal I that does not pass through frequency correction that the bandpass signal after the base bandization of matched filter output is comprised Band' (n), Q Band' (n) send into a phase discriminator in the carrier synchronization circuit that comprises the polarity type phase discriminator, extract phase error signal ε as follows c(n):
ε c(n)=I Band' (n) * Q Band' (n), n is the sampler label;
(2) described phase error signal ε c(n) a second order digital loop filters of importing in this carrier recovery loop carries out filtering, and its sequential is:
The phase error accumulating signal φ (n+1) of n+1 sampled point is:
φ(n+1)=φ(n)+K 1′f(n)+K 2′ε c(n),
The frequency error accumulating signal f (n+1) of n+1 sampled point is:
f(n+1)=f(n)+ε c(n),
Wherein, constant K 1', K 2' be two filtering parameters that are used for frequency, phase place of this second order digital loop filters, as the sample frequency f of aforementioned analog to digital converter sDuring much larger than the natural frequency of described carrier recovery loop, K 2'=2 η ω nT s, K 1'=ω nT s,
Wherein, ω n=2 π f nBe the natural frequency of described second order digital loop, η is a damping coefficient, T s=1/f s,
(3) the input of the error accumulation signal psi (n+1) that obtains through the second order digital loop filtering of (2), to adjust the frequency of local oscillation signal as local digital controlled oscillator NCO in the described carrier synchronization circuit;
(4) the I/Q two-way digital baseband signal I that the bandpass signal after the base bandization of described carrier synchronization circuit is comprised Band(m), Q Band(m) output signal cos φ (n), the sin φ (n) with local digital controlled oscillator multiplies each other in phase rotation circuit, carries out the phase place rotation, obtains the I/Q two-way digital baseband signal I through frequency correction Band' (m), Q Band' (m):
I Band' (m)=I Band(m) * cos φ (n)+Q Band(m) * sin φ (n),
Q Band' (m)=Q Band(m) * cos φ (n)-I Band(m) * sin φ (n),
The difference of m and n is the computing time-delay of described whole carrier synchronization circuit;
(5), in the time of one section setting, add up I for bpsk signal Band' (m), Q Band' (m) separately average energy is chosen the wherein a road big useful signal as carrierfree frequency and phase deviation of energy, be sent to second regularly synchronous circuit carry out timing synchronously; For the QPSK signal, directly I Band' (m), Q Band' (m) being sent to the second timing synchronous circuit respectively carries out timing synchronously;
Fig. 8 is the schematic block circuit diagram of determination point Chooser.As shown in Figure 8, the burst after is chosen two determination points through a determination point Chooser respectively to each modulation symbol synchronously, divides two-way output, and the sample rate on each road is 1 sampled point of every symbol; The specific implementation method is:
(1) first via is formed by the optimum sampling point of each symbol, does not promptly have the sampled point of intersymbol interference, for ..., y -N, y 0, y N...;
(2) the second tunnel for being one of other any sampled points of each symbol, promptly has the sampled point of intersymbol interference, for ..., y -N+f, y f, y N+f..., wherein f is a natural number, span is 1 to arrive
Figure GSB00000567199700111
For being not less than
Figure GSB00000567199700112
Smallest positive integral.
The position of another road sampled point of the position of optimum sampling point and f the sampled point of delaying time wherein, is provided by aforementioned timing synchronous circuit.
Next, the two-way determination point signal that the determination point Chooser obtains carries out the statistics of pseudo-error rate by a pseudo-error rate statistics device; Here pseudo-error rate refers to the probability that two-way sampled signal court verdict does not wait, promptly opposite polarity probability; Choose M and be the statistics siding-to-siding block length, M is a natural number, gets 10 usually 2~10 3The above order of magnitude is to guarantee estimated accuracy; Then for bpsk signal, the estimated value P of pseudo-error rate PFor:
P P = 1 M &Sigma; l = 0 M - 1 &xi; ( y 1 N , y lN + f ) , Wherein &xi; ( y lN , y lN + f ) = 1 , y lN &times; y lN + f < 0 0 , y lN &times; y lN + f &GreaterEqual; 0 ;
For the QPSK signal, the estimated value P of pseudo-error rate PFor:
P P = 1 2 M &Sigma; l = 0 M - 1 { &xi; ( Re [ y lN ] , Re [ y lN + f ] ) + &xi; ( Im [ y lN ] , Im [ y lN + f ] ) } ,
Wherein function R e represents to get a real, and function Im represents to get the imaginary part of a plural number,
&xi; ( Re [ y lN ] , Re [ y lN + f ] ) = 1 , Re [ y lN ] &times; Re [ y kN + f ] < 0 0 , Re [ y lN ] &times; Re [ y lN + f ] &GreaterEqual; 0 ,
&xi; ( Im [ y lN ] , Im [ y lN + f ] ) = 1 , Im [ y lN ] &times; Im [ y kN + f ] < 0 0 , Im [ y lN ] &times; Im [ y lN + f ] &GreaterEqual; 0 .
At last, the estimated value P of the pseudo-error rate that obtains of pseudo-error rate statistics device PBy a signal to noise ratio mapper, utilize functional relation dull between pseudo-error rate and the signal to noise ratio, obtain the estimated value ρ of signal to noise ratio by numerical method.This numerical method is usually by the realization of tabling look-up, and the pseudo-error rate that calculated in advance is good and the numerical value of signal to noise ratio are stored in the memory, and the pseudo-error rate that utilizes estimation to obtain is searched the signal to noise ratio corresponding with it and got final product.The form of this monotonic function is as follows:
P P = 1 - 1 2 ( 4 &Phi; ( 0 , &infin; , 0 ) + &Psi; ( g 2 , 1 ) + &Psi; ( g 1 , 1 ) + 2 &Psi; ( 1,0 ) ) , Wherein:
&Phi; ( 0 , &infin; , 0 ) = 1 &pi; [ arctan ( 1 - G f 1 + G f ) + arctan ( G f 2 1 - G f 2 ) ] ,
&Psi; ( a , b ) = &Integral; - a 0 &rho; 8 &pi; e - &rho;x 2 2 [ 1 - 2 erfc ( &rho; ( b + G f x ) 2 ( 1 - G f 2 ) ) ] dx , A and b are the limit of integration, and x is an integration variable, and erfc is the complementary error function, and it is defined as
Figure GSB00000567199700124
T is an independent variable, and z is an integration variable, g 1=G f+ G F-N, g 2=G f-G F-N, G f = &Sigma; k = - KN KN h k h k + f , G f - N = &Sigma; k = - KN KN h k h k + f - N .
By above step, finally obtain the estimated value ρ of signal to noise ratio.
As previously mentioned, according to the present invention, based on the blind SNR estimating method of pseudo-error rate statistics avoided existing all kinds of algorithm computation complexities too high, realize the excessive limitation of cost, simplified hardware configuration and realized cost; It is auxiliary that it need not training sequence, thereby higher efficiency of transmission is arranged; The algorithm for estimating of optimum such as performance and maximum likelihood is suitable, has stronger versatility; Have the circuit design and the realization of succinct practicality, structure law simultaneously, it is integrated to be easy to chip.

Claims (1)

1. based on the blind SNR estimating method of pseudo-error rate statistics, it is characterized in that containing successively following steps:
Step (1): the received signal that receiver is received obtains baseband modulation signal through the base band processor:
For the baseband signal in the described received signal, comprise base band bpsk signal and base band QPSK signal, this base band processor is not done any processing, directly passes through;
For the bandpass signal in the described received signal, comprise logical bpsk signal of band and the logical QPSK signal of band, making quadrature frequency conversion with the quadrature frequency conversion circuit in this base band processor handles, obtain having the logical BPSK complex signal of band after the base bandization of carrier frequency and phase deviation, perhaps the logical QPSK complex signal of the band after the base bandization;
Step (2): the discretization processor carries out the discretization processing to the baseband signal or the bandpass signal after the base bandization of the described base band processor output of step (1):
For sample rate is that the integral multiple of symbol rate and multiple are not done any processing greater than 2 discrete signal and directly passed through;
Then carry out the sampling that sample rate is every symbol N sampled point with analog to digital converter for continuous signal, obtain corresponding discrete signal, wherein, N is the natural number greater than 2, and the upper limit of N should can realize being as the criterion with current analog to digital converter;
Step (3): matched filter carries out matched filtering to the base band discrete signal or the logical discrete signal of the band after the base bandization of discretization processor output in the step (2):
The impulse response of this matched filter is for adopting the root-raised cosine pulse of identical rolloff-factor α, 0≤α≤1 with transmitting;
This impulse sampling rate is similarly N, and its impulse response sequence is a sequence of real numbers { h -KN...., h -1, h 0, h 1... h KN, h nExpression formula be: N=-KN ... ,-1,0,1 ... KN, wherein h (t) is the continuous impulse of root-raised cosine signal,
h ( t ) = 1 2 &pi; &Integral; - &infin; &infin; H ( &omega; ) e j&omega;t d&omega; ,
H ( &omega; ) = S 0 , 0 &le; | &omega; | < &pi; ( 1 - &alpha; ) T s S 0 2 { 1 - sin [ T s 2 &alpha; ( &omega; - &pi; T s ) ] } , &pi; ( 1 - &alpha; ) T s &le; | &omega; | &le; &pi; ( 1 + &alpha; ) T s 0 , | &omega; | > &pi; ( 1 + &alpha; ) T s
T sBe symbol period,
The value of K is 1<K≤10, and 2K represents the symbolic number that this matched filter impulse response is occupied,
S 0Be constant, by { the h after obtaining -KN...., h -1, h 0, h 1... h KNHas unit energy promptly in conjunction with pulse
Figure FSB00000567199600021
Condition calculate;
Step (4): carrier frequency, phase deviation and timing offset that synchronizer is corrected existence according to the following steps to the baseband signal matched filter from step (3) output, after the matched filtering or the bandpass signal after the base bandization:
Step (4.1): synchronizer adopts the first timing synchronous circuit to correct timing offset to the baseband signal of exporting from the matched filter of step (3), obtains not having the baseband signal of timing offset, be designated as ... .., y -1, y 0, y 1... ..} is real sequence for BPSK, and QPSK is a complex sequences, and it is synchronous that this first timing synchronous circuit carries out timing successively according to the following steps;
Step (4.1.1): the real part I ' of the baseband signal of after described matched filtering, exporting (m) in, the signal I ' (n of the optimum sampling point position of each symbol current selected 0), the signal I ' (n of previous sampled point 0-1), the signal I ' (n of a sampled point afterwards 0+ 1) sends into a timing error extractor, calculate and obtain a signal of timing error ε by following formula t(n), n is the sampled point sequence number:
ε t(n)=sign (I ' (n 0)) * [I ' (n 0+ 1)-I ' (n 0-1)], symbol sign is a sign function, and value is 1 during the independent variable nonnegative number, and value is-1 during for negative;
Wherein, when starting working in system, this optimum sampling point position is chosen arbitrarily;
Step (4.1.2): described signal of timing error ε t(n) send into the timing error value E that a single order digital lowpass loop filter obtains accumulating t(n), E t(n)=E t(n-1)+K 1ε t(n)
K 1Be filter factor, K 1<1;
Step (4.1.3): judge accumulated error value E with a comparator t(n) whether reach the threshold values of setting, if reach the threshold values of setting, then, send an optimum sampling point position simultaneously and adjust signal, the position of control optimum sampling point the accumulated error zero clearing, make its polarity according to accumulated error, if just, then carry the previous unit sampling interval, otherwise, just postpone a unit sampling interval, thereby find optimum sampling point I ' (n 0);
Step (4.2): the carrier synchronization circuit and second that the bandpass signal of synchronizer after to the base bandization of the matched filter of step (3) output adopts serial connection successively regularly synchronous circuit is corrected, with the bandpass signal after the base bandization that obtains not having carrier frequency and phase deviation, be designated as ... .., y -N, y 0, y N... ..} is a real signal for bpsk signal, is complex signal for the QPSK signal, and the correction step is as follows:
Step (4.2.1): the I/Q two-way digital baseband signal I that does not pass through frequency correction that the bandpass signal after the base bandization of the described matched filter of step (4.2) output is comprised Band' (n), Q Band' (n) send into a phase discriminator in the carrier synchronization circuit that comprises the polarity type phase discriminator, extract phase error signal ε as follows c(n):
ε c(n)=I Band' (n) * Q Band' (n), n is the sampler label;
Step (4.2.2): described phase error signal ε c(n) a second order digital loop filters in incoming carrier recovers to encircle carries out filtering, and its sequential is:
The phase error accumulating signal φ (n+1) of n+1 sampled point is:
φ(n+1)=φ(n)+K 1′f(n)+K 2′ε c(n),
The frequency error accumulating signal f (n+1) of n+1 sampled point is:
f(n+1)=f(n)+ε c(n),
Wherein, constant K 1', K 2' be two filtering parameters that are used for frequency, phase place of this second order digital loop filters, as the sample frequency f of analog to digital converter described in the step (2) sDuring much larger than the natural frequency of carrier recovery loop, K 2'=2 η ω nT s, K 1'=ω nT s,
Wherein, ω n=2 π f nBe the natural frequency of described second order digital loop, η is a damping coefficient, T s=1/f s,
Step (4.2.3): the error accumulation signal psi (n+1) that the filtering through step (4.2.2) second order digital loop is obtained is as the input of local digital controlled oscillator NCO in the described carrier synchronization circuit, to adjust the frequency of local oscillation signal;
Step (4.2.4): the I/Q two-way digital baseband signal I that the bandpass signal after the base bandization that is input to the described carrier synchronization circuit of step (4.2) is comprised Band(m), Q Band(m) output signal cos φ (n), the sin φ (n) with local digital controlled oscillator multiplies each other in phase rotation circuit, carries out the phase place rotation, obtains the I/Q two-way digital baseband signal I through frequency correction Band' (m), Q Band' (m):
I Band' (m)=I Band(m) * cos φ (n)+Q Band(m) * sin φ (n),
Q Band' (m)=Q Band(m) * cos φ (n)-I Band(m) * sin φ (n),
The difference of m and n is the computing time-delay of described whole carrier synchronization circuit;
Step (4.2.5):, in the time of one section setting, add up I for bpsk signal Band' (m), Q Band' (m) separately average energy is chosen the wherein a road big useful signal as carrierfree frequency and phase deviation of energy, be sent to second regularly synchronous circuit carry out timing synchronously; For the QPSK signal, directly I Band' (m), Q Band' (m) being sent to the second timing synchronous circuit respectively carries out timing synchronously;
Step (4.2.6): to be sent in the step (4.2.5) second regularly synchronous circuit signal set by step (4.1) described method carry out timing synchronously, the timing offset that exists with correction;
Step (4.2.7); The regularly synchronous baseband signal of process step (4.1), or through step (4.2.1) to step (4.2.6) through carrier frequency and Phase synchronization and correct and regularly synchronous base bandization after bandpass signal be sent to the determination point Chooser, according to the following steps, each modulation symbol is chosen two determination points respectively, divide two-way output, the sample frequency on each road is sampled point of each symbol;
Step (5): choose determination point with the determination point Chooser:
Step (5.1): the first via is made up of the optimum sampling point of each symbol, is no intersymbol interference, is designated as:
... .., y -N, y 0, y N... ..}; The position of optimum sampling point wherein, is provided by step (4);
Step (5.2): the second tunnel is one of other any sampled points of each symbol, promptly has the sampled point of intersymbol interference, be designated as ... .., y -N+f, y f, y N+f... ..}, wherein f is a natural number, span is: 1 arrives
Figure FSB00000567199600041
For being not less than the smallest positive integral of N/2; Wherein, this signals sampling point position, road obtains for optimum sampling point position f the sampled point of time-delay that is provided by the timing synchronous circuit in the step (4);
Step (6): the pseudo-error rate statistics device carries out pseudo-error rate statistics to the two-way determination point signal that the determination point Chooser obtains, and is calculated as follows the probability P that two-way sampled point court verdict does not wait p, promptly opposite polarity probability is chosen M and is statistics length of an interval degree, and M is a natural number, gets 10 2~10 3The above order of magnitude, to guarantee estimated accuracy:
For bpsk signal, the estimated value P of pseudo-error rate pFor
P P = 1 M &Sigma; l = 0 M - 1 &xi; ( y 1 N , y lN + f ) , Wherein &xi; ( y lN , y lN + f ) = 1 , y lN &times; y lN + f < 0 0 , y lN &times; y lN + f &GreaterEqual; 0 ;
For the QPSK signal, the estimated value P of pseudo-error rate pFor:
P P = 1 2 M &Sigma; l = 0 M - 1 { &xi; ( Re [ y lN ] , Re [ y lN + f ] ) + &xi; ( Im [ y lN ] , Im [ y lN + f ] ) } ,
Wherein function R e represents to get a real, and function Im represents to get the imaginary part of a plural number,
&xi; ( Re [ y lN ] , Re [ y lN + f ] ) = 1 , Re [ y lN ] &times; Re [ y kN + f ] < 0 0 , Re [ y lN ] &times; Re [ y lN + f ] &GreaterEqual; 0 ,
&xi; ( Im [ y lN ] , Im [ y lN + f ] ) = 1 , Im [ y lN ] &times; Im [ y kN + f ] < 0 0 , Im [ y lN ] &times; Im [ y lN + f ] &GreaterEqual; 0 ;
The estimated value P of the pseudo-error rate that step (7) obtains step (6) PBy a signal to noise ratio mapper, utilize functional relation dull between pseudo-error rate and the signal to noise ratio, obtain the estimated value ρ of signal to noise ratio by numerical method; This numerical method is usually by the realization of tabling look-up, and the pseudo-error rate that calculated in advance is good and the numerical value of signal to noise ratio are stored in the memory, and the pseudo-error rate that utilizes estimation to obtain is searched the signal to noise ratio corresponding with it and got final product; The form of this monotonic function is as follows:
P P = 1 - 1 2 ( 4 &Phi; ( 0 , &infin; , 0 ) + &Psi; ( g 2 , 1 ) + &Psi; ( g 1 , 1 ) + 2 &Psi; ( 1,0 ) ) , Wherein:
&Phi; ( 0 , &infin; , 0 ) = 1 &pi; [ arctan ( 1 - G f 1 + G f ) + arctan ( G f 2 1 - G f 2 ) ] ,
&Psi; ( a , b ) = &Integral; - a 0 &rho; 8 &pi; e - &rho;x 2 2 [ 1 - 2 erfc ( &rho; ( b + G f x ) 2 ( 1 - G f 2 ) ) ] dx , A and b are the limit of integration, and x is an integration variable, and erfc is the complementary error function, and it is defined as
Figure FSB00000567199600053
T is an independent variable, and z is an integration variable, g 1=G f+ G F-N, g 2=G f-G F-N, G f = &Sigma; k = - KN KN h k h k + f , G f - N = &Sigma; k = - KN KN h k h k + f - N .
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