CN101184066B - TD-SCDMA and 3G terminal digital baseband modulator - Google Patents
TD-SCDMA and 3G terminal digital baseband modulator Download PDFInfo
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Abstract
The invention provides a digital baseband modulation system for a TD-SCDMA and a third mobile communication terminal (3G, containing cdma 2000, UMTS, TD-SCDMA) for accomplishing channelized and extended modulation, and scrambling extended modulation of the TD-SCDMA/3G terminal. The digital baseband modulation system comprises a plurality of functional modules of a DSP core, a clock generator, a DSP programmable interrupt controller, a CPU sub-system, a digital baseband modulator, a channelized code generator, a random scrambling generator, a middle sequence generator, an RF frequency synthesizer and a system main timer. The digital baseband modulator comprises five functional modules of a data interface module, a controller of the modulator, a clock generation module, an expander and a baseband filter. The controller of the modulator in the digital baseband modulator comprises five sub-modules of a serial number decoder, an enable signal generator, an interrupt signal generator, a power control signal generator and a timing control signal generator. The digital baseband modulation system comprises four operation status models of a modulator closing, a modulator initialization, a modulating work and a modulator termination model.
Description
Technical field
The present invention proposes the digital baseband modulating system of a kind of TD-SCDMA of being used for, B3G (Beyond 3G), 4G (the 4th third-generation mobile communication) terminal.The digital baseband modulation technique that the present invention proposes belongs to the mobile communication technology field.
Background technology
The digital baseband modulating system, what finish is to desiring to send to the reverse link traffic channel data of base station, reach control channel data such as access channel, up Common Control Channel, up Dedicated Control Channel and carry out the function of digital baseband modulation, comprise and finish following operation: (1) does channelizing expansion modulation to the data that will send, and modulates as OVSF (quadrature rate-compatible function); (2) data of finishing channelization modulation are done scrambler expansion modulation at random; (3) data of finishing above-mentioned expansion modulation are done baseband filtering.
Realize above-mentioned digital baseband modulating system, is at first must obtain accurately and the clearly answer of following problem: 1. this digital baseband modulating system which functional module made of? is 2. the above-mentioned functions module finished and so on function respectively? 3. possess which type of interface between the above-mentioned functions module, receive and dispatch what signal each other; 4. which is a nucleus module among the above-mentioned functions module? is 5. this nucleus module which function sub-modules made of? what function does and the latter finish respectively? receive and dispatch what signal each other? 6. expanding modulated process is under the driving of what signal, realize synchronously request and receive channel sign indicating number, scrambler, intermediate sequence sign indicating number and treat modulating data at random? is 7. what kind of the mode of operation of this digital baseband modulating system?
Summary of the invention:
The present invention proposes the digital baseband modulating system of a kind of TD-SCDMA of being used for, B3G (Beyond 3G), 4G (the 4th third-generation mobile communication) terminal, the formation of this digital baseband modulating system, inside and outside input and output connection have been offered some clarification on, signal that transmits between the functional module and signal transmit synchronisation control means, and the mode of operation of this digital baseband modulating system.
The formation block diagram of the digital baseband modulating system of realization TD-SCDMA, the B3G that the present invention of being shown in Figure 1 proposes (Beyond 3G), 4G (the 4th third-generation mobile communication) terminal, this digital baseband modulating system is made of following functional module:
(1) DSP nuclear: DSP nuclear is provided for finishing the data of digital baseband modulation to digital baseband modulator, and starts and close the necessary digital baseband modulator of digital baseband modulated process and enable indication; For the digital baseband modulated process, exist input and output to be connected between DSP nuclear and DSP programmable interrupt controller, digital baseband processor, system's master timer, searcher, the clock generator; Wherein, the DSP stone grafting is received the interrupt signal of sending from the DSP clock signal and the DSP programmable interrupt controller of clock generator output; DSP by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, data to be modulated and digital baseband modulator are enabled indication send to digital baseband modulator; DSP nuclear control searcher is to the search procedure of network cell; DSP nuclear also is responsible for the control system master timer and is indicated update system master's timing signal synchronously according to searcher locking cell downlink;
(2) clock generator: clock generator provides the work clock signal to these modules with DSP nuclear, DSP programmable interrupt controller, cpu subsystem, digital baseband modulator, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, system's master timer, the searcher at random; Clock generator also provides digital baseband modulator reset signal mod_rst_b to digital baseband modulator, realizes resetting to digital baseband modulator;
(3) DSP programmable interrupt controller: for the digital baseband modulated process, exist input and output to be connected between DSP programmable interrupt controller and digital baseband modulator, DSP nuclear, the clock generator; The DSP programmable interrupt controller receives the interrupt request singal from digital baseband modulator, generates the interrupt request singal that is used to finish the digital baseband modulation that sends to DSP nuclear according to the latter; The DSP programmable interrupt controller receives the clock signal from clock generator;
(4) cpu subsystem: for the digital baseband modulated process, exist input and output to be connected between cpu subsystem and digital baseband modulator, the clock generator; Cpu subsystem provides CPU idle signal, CPU to enter the park mode signal to digital baseband modulator, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Cpu subsystem receives the clock signal from clock generator;
(5) digital baseband modulator: digital baseband modulator is responsible for finishing channelizing expansion modulation, the scrambler expansion is modulated and baseband filtering at random; Digital baseband modulator comprises data interface module, modulator control device, expander, clock generating module, baseband filter; Digital baseband modulator is with DSP nuclear, DSP programmable interrupt controller, system's master timer, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, cpu subsystem, rf frequency synthesizer, radio-frequency power amplifier, clock generator, the Analog Baseband at random;
Digital baseband modulator by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, the data to be modulated and the digital baseband modulator that receive from the output of DSP nuclear enable indication; Digital baseband modulator receives the work clock signal from clock generator, operation under the work clock signal drives; The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided digital baseband modulator, realizes resetting to digital baseband modulator; Digital baseband modulator receives the master timer chip timings enable signal from system's master timer, expands the chip synchronization reference signal of modulation as self; CPU idle signal, CPU that digital baseband modulator receives from cpu subsystem output enter the park mode signal, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Digital baseband modulator receives the automatic frequency control locking signal from the output of rf frequency synthesizer, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time opens or close radio-frequency power amplifier;
Digital baseband modulator is regularly to DSP programmable interrupt controller output interrupt requests; Digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, synchronously respectively to channel code generator, scrambler generator or intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal; Similarly, under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, digital baseband modulator is synchronously respectively from the channel code generator, scrambler generator, intermediate sequence generator obtain channel code, scrambler, intermediate sequence sign indicating number at random at random; Digital baseband modulator enables control signal with radio-frequency power amplifier and sends to radio-frequency power amplifier; The data that digital baseband modulator will be finished modulation send to Analog Baseband;
(6) channel code generator: exist input and output to be connected between channel code generator and digital baseband modulator, the clock generator; The channel code generator receives channel code chip sequence number and the request signal from digital baseband modulator output, channel code chip sequence number and request signal according to digital baseband modulator output produce channel code, and the channel code that produces is sent to digital baseband modulator; The channel code generator receives the work clock signal from clock generator, operation under the work clock signal drives;
(7) scrambler generator at random: exist input and output to be connected between scrambler generator and digital baseband modulator, the clock generator at random; The scrambler generator receives chip sequence number of scrambler at random and the request signal from digital baseband modulator output at random, chip sequence number of scrambler at random and request signal according to digital baseband modulator output produce scrambler at random, and the scrambler at random that will produce sends to digital baseband modulator; The scrambler generator receives the work clock signal from clock generator at random, operation under the work clock signal drives;
(8) intermediate sequence generator: exist input and output to be connected between intermediate sequence generator and digital baseband modulator, the clock generator; The intermediate sequence generator receives intermediate sequence chip sequence number and the request signal from digital baseband modulator output, intermediate sequence chip sequence number and request signal according to digital baseband modulator output produce the intermediate sequence sign indicating number, and the intermediate sequence sign indicating number that produces is sent to digital baseband modulator; Intermediate sequence sign indicating number generator receives the work clock signal from clock generator, operation under the work clock signal drives;
(9) rf frequency synthesizer: for digital baseband modulation, the rf frequency synthesizer is examined with DSP, exist input and output to be connected between the digital baseband modulator; The rf frequency synthesizer receives frequency synthesis and the lock control signal from DSP nuclear, whether control the situation of locking radio frequency frequency according to automatic frequency, to digital baseband modulator output automatic frequency control locking signal, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time open or close radio-frequency power amplifier;
(10) system's master timer: for digital baseband modulation, exist input and output to be connected between system's master timer and DSP nuclear, searcher, digital baseband modulator, the clock generator; System's master timer is indicated synchronously according to searcher locking cell downlink under the DSP nuclear control, receives the downlink synchronous signal from searcher, is used for update system master timing signal; System's master timer is used to the downlink synchronous signal from searcher, produces initial timing signal and the ascending time slot chip timings enable signal of ascending time slot that sends to digital baseband modulator; It sends the initial timing signal of ascending time slot to digital baseband modulator at the initial preceding 1/16 chip place of ascending time slot, and each chip after ascending time slot is initial begins preceding 1/16 chip place to ascending time slot chip timings enable signal of digital baseband modulator transmission; The system master timer receive from clock generator the work clock signal.
Each signal description of interface is shown in table 1-1 between digital baseband modulator among Fig. 1 and other functional module.
Fig. 2 is the inside composition frame chart of the digital baseband modulator shown in Fig. 1, and this digital baseband modulator is made of following functional module:
(1) clock generating module: clock generating module and outside clock generator, and exist input and output to connect between the data interface module of digital baseband modulator inside, modulator control device module, expander module, baseband filter module.The clock generating module receives the clock signal from clock generator, produces the work clock signal that offers inner each functional module of digital baseband modulator.The clock generating submodule is received 2 clock signals from clock generator, mod_clk (this clock be spread-spectrum code chip speed N doubly, as 16 times, 32 times etc.), the DSP clock---" clkout_dsp ".
16 times of spreading rate clocks (note is made ck_cx16) of the work clock signal of inner each functional module of digital baseband modulator are produced by this clock generating module, and under modulator clock enable signal mod_clken gate, as the clock source of each functional module of digital baseband modulator inside.
Inner 16 times of spreading rate clocks are from a local caches output, being input as by the mod_clk signal of synchronous again modulator clock enable signal mod_clken institute gate of this local caches disturbed to avoid inner 16 times of fast clocks to be subjected to short-time pulse waveform.The delay of local clock buffer and type by the zone of local load capacitance and chip forming process delay with route postpone determined.Modulator clock enable signal mod_clken is from master clock module (clock generator).
The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided the clock generating module, produces the synchronous reset signal srst_b of digital baseband modulator.Synchronous reset signal srst_b produces modulator reset signal mod_rst_b by the 16 times of fast clocks in inside with gate synchronously again, is in definite state to guarantee all registers after the deexcitation that resets.
(2) data interface module: Fig. 4 illustrates the memory-mapped registers group of data interface module.Data interface module provides the data-interface of digital baseband modulator and DSP, realizes the data communication between digital baseband modulator and the DSP.The register (memory-mapped register) relevant with DSP all is placed in this module in the digital baseband modulator that table 1-2 lists, and digital baseband modulator can directly be conducted interviews to these registers.These registers also can directly be read by DSP.As shown in Figure 4.
Data interface module and outside DSP nuclear, and exist input and output to connect between the inner modulator control device module, expander module, clock generating module.Data interface module receive from DSP nuclear by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, to the visit of internal memory mapping register.Data interface module receives the work clock from the clock generating module.Data interface module receive from the modulator control device the shift enable signal of each channel data.Data interface module enables modulation rate, digital baseband modulator indication bit, ascending time slot transmission enable signal, power amplifier parameter warm-up time, the invalid index signal of Analog Baseband clock and sends data switching index signal to send to the modulator control device.Also under the shift enable signal effect from the modulator control device, the transfer of data of with selected transmission rate each channel being deposited by data serializer arrives expander module to data interface module.
1. system register: the system register group comprises 2 I/O mouth registers, and they are used for controlling modulator block.The channel quantity that these registers and modulator block design are supported is irrelevant.These 2 registers comprise the physics flip and flop generator, are readable writing to DSP.
2. service register group: the service register group comprises the gain register and the data register of all channels.
3. data serializer: data interface module also comprises data serializer, and the transfer of data that data serializer is deposited each channel with selected transmission rate is to expander module.As shown in Figure 4.When being activated, the data of these registers will be moved out of when shift enable signal (being produced by the digital baseband modulator controller module).
(3) modulator control device module: Fig. 3 is the block diagram of modulator control device module MOD_CTRL.Modulator control device module is the vital part of digital baseband modulator, all submodules of control figure baseband modulator; Modulator control device module is with outside cpu subsystem, system's master timer, DSP programmable interrupt controller, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, Analog Baseband, radio-frequency power amplifier, the rf frequency synthesizer at random; Simultaneously, modulator control device module also with between the data interface module of digital baseband modulator inside, expander module, baseband filter module, the clock generating module exists input and output to be connected; The modulator control device receives master timer chip timings enable signal and the ascending time slot enable signal from system's master timer, reception is from the modulation rate of data interface module, the digital baseband modulator enable signal, ascending time slot transmission enable signal, power amplifier parameter warm-up time, invalid index signal of Analog Baseband clock and transmission data are switched index signal, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception is from the CPU free time of cpu subsystem, CPU enters sleep signal, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; Modulator control device module is according to parameter and the signal received, at the ascending time slot enable signal, under the driving of master timer chip timings enable signal and work clock, channel code chip sequence number is sent to the channel code generator, scrambler chip sequence number sends to scrambler generator at random at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the digital baseband modulator interrupt request singal of DSP programmable interrupt controller, generation sends to the digital baseband modulator chip timings enable signal of baseband filter, the power amplifier that generation sends to radio-frequency power amplifier enables control signal, generation sends to the difference tranmitting data register of analog baseband, produces the multiplexing selection signal and the phase count that send to baseband filter;
As shown in Figure 3, the modulation controller module is made of following submodule:
1. sequence number decoder: system's master timer, the channel code generator of sequence number decoder and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, between the data interface module of sequence number decoder and digital baseband modulator inside, the clock generator module, and with the enable signal generator of modulator control device inside modules between exist input and output to be connected; The sequence number decoder receives the reference signal of modulating chip count from the ascending time slot enable signal of system's master timer as up expansion, the sequence number decoder receives the modulation rate from data interface module, reception is from the digital baseband modulator chip timings enable signal of the enable signal generator of modulator control device inside modules, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The sequence number decoder is according to the signal and the data parameter that receive, decodes channel code chip sequence number, scrambler chip sequence number, intermediate sequence sequence number at random, and modulation chip sequence number; The sequence number decoder is under the driving of digital baseband modulator chip timings enable signal and work clock, channel code chip sequence number is sent to the channel code generator, scrambler chip sequence number sends to scrambler generator at random at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, modulation chip sequence number is sent to the enable signal generator of modulator control device inside modules;
2. enable signal generator: system's master timer, the channel code generator of enable signal generator and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, the enable signal generator is also and between the data interface module of digital baseband modulator inside, expander module, baseband filter module, clock generator module, and exists input and output to be connected between the sequence number decoder of modulator control device inside modules and the interrupt signal generator; The enable signal generator generates the employed enable signal of all modulators; All enable signals all are pulse train, and each pulse duration is 1/16 chip; The reception of enable signal generator is led regularly the chip timings enable signal as the chip timings reference signal from system's master timer, reception is from the modulation rate of data interface module with from the modulation chip sequence number of sequence number decoder, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The enable signal generator is according to above-mentioned signal and the data parameter received, under main regularly chip timings enable signal and work clock driving, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the sequence number decoder, the digital baseband modulator chip timings enable signal of baseband filter and timing controling signal generator, also produce the power amplifier that sends to the power control signal generator and enable control signal, and produce the symbol enable signal that sends to the interrupt signal generator;
3. interrupt signal generator: exist input and output to be connected between the DSP programmable interrupt controller of interrupt signal generator and digital baseband modulator outside; Simultaneously, the interrupt signal generator is also and between the digital baseband modulator clock internal generator module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The interrupt signal generator receives the symbol enable signal from the enable signal generator, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The interrupt signal generator produces the digital baseband modulator interrupt request singal that sends to the DSP programmable interrupt controller according to the symbol enable signal; Interrupt generator and periodically the DSP programmable interrupt controller is produced the digital baseband modulator interruption; This interrupt request singal produces at first at each data symbol that will modulate; Interrupt rate is 20KHz;
4. power control signal generator: exist input and output to be connected between the radio-frequency power amplifier of power control signal generator and digital baseband modulator outside, rf frequency synthesizer, the cpu subsystem; Simultaneously, the power control signal generator also with between the data interface module of digital baseband modulator inside, the clock generator module exists input and output to be connected; The power control signal generator is that radio-frequency power amplifier produces the power control signal; The power control signal generator receives digital baseband modulator enable signal, ascending time slot transmission enable signal and power amplifier parameter warm-up time from data interface module, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception enters sleep signal from CPU free time, the CPU of cpu subsystem, and receives 16 times of spreading rate clock signals in inside and synchronous reset signal from the clock generating module; The power control signal generator produces the power amplifier that sends to radio-frequency power amplifier and enables control signal according to the signal that receives;
5. timing controling signal generator: exist input and output to be connected between the Analog Baseband of timing controling signal generator and digital baseband modulator outside; Simultaneously, the timing controling signal generator is also and between the data interface module of digital baseband modulator inside, baseband filter module, clock generator module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The timing controling signal generator is that baseband filter BBF and analog baseband BBA produce clock control signal; The timing controling signal generator receives digital baseband modulator enable signal, the invalid index signal of Analog Baseband clock from data interface module and sends data and switches index signal, reception is from the digital baseband modulator chip timings enable signal of enable signal generator, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The timing controling signal generator is according to the signal that receives, under the driving of digital baseband modulator chip timings enable signal and work clock, generation sends to the difference tranmitting data register of analog baseband, produces the multiplexing selection signal and the phase count that send to baseband filter.
Table 1-3 provides the description of the input/output signal of said modulator controller submodule.
(4) expander module: expander module is with outside channel code generator, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random.Simultaneously, expander module also with between the data interface module of digital baseband modulator inside, modulator control device module, baseband filter module, the clock generating module exists input and output to be connected.Expander receives the expansion enable signal from the modulator control device, reception is from the modulating data for the treatment of of each channel of data interface module, reception is from the channel code chip of channel code generator, reception is from the chip of scrambler at random of scrambler generator at random, reception receives the work clock from the clock generating module from the intermediate sequence sign indicating number chip of intermediate sequence generator.Expander module is according to the signal that receives, finishes the channelizing expansion modulation for the treatment of modulating data and scrambler expansion modulation at random from each channel of data interface module.The data that expander module will be finished modulation send to baseband filter.As shown in Figure 5.
(5) baseband filter: exist input and output to be connected between baseband filter and the outside Analog Baseband.Simultaneously, baseband filter also with between the modulator control device module of digital baseband modulator inside, expander module, the clock generating module exists input and output to be connected.Baseband filter receives from the digital baseband modulator chip timings enable signal of modulator control device, multiplexing selection signal and phase count, receives the modulating data from expander module, receives the work clock from the clock generating module.Expander module is according to the signal that receives, finishes the baseband filtering from the modulating data of expander module.The data that baseband filter will be finished baseband filtering send to the Analog Baseband processing subsystem.
This digital baseband modulating system has four kinds of mode of operation patterns: the modulator " shut " mode"; The modulator initialize mode; The modulation mode of operation; The modulator termination pattern.
(1) digital baseband modulator " shut " mode": when the digital baseband modulator " shut " mode", digital baseband modulator is not worked thereby CPU closes the clock of modulator; The asynchronous reset signal that clock generator is issued digital baseband modulator should keep invalid, because this signal low level is effective, thereby is high level at this moment; It is 0 that digital baseband modulator in the modulator control register enables indication bit MOD_EN;
(2) digital baseband modulator initialization: when travelling carriage will send access channel or reverse traffic channel data, earlier will be before sending data finishing initialization step;
1. at first, CPU will enable the clock of digital baseband modulator;
2. then, it waits for 3 modulator clock cycle at least, just provides asynchronous reset signal to digital baseband modulator;
3. it is effective that asynchronous reset signal will keep at least 2 modulator clock cycle, then just by deexcitation;
4. simultaneously, CPU sends to DSP with the information that is necessary such as radio-frequency power amplifier PA warm-up time etc.;
5. when digital baseband modulator sends data, CPU will draw high that 2 control bits---CPU idle signal IDLE_B and CPU enter the level of park mode signal SLEEP_B, starts work to realize digital baseband modulator control radio-frequency power amplifier PA;
6. after the digital baseband modulator asynchronous reset signal was by the CPU deexcitation, DSP reply radio-frequency power amplifier PA preheating register was provided with suitable numerical value; The value of all DSP memory-mapped registers is both initialized to 0;
7. initialization final step is carried out initialization to the control register of digital baseband modulator;
1) if it is 0 that digital baseband modulator enables indication bit MOD_EN, digital baseband modulator does not provide regularly, and most of internal register will can not change;
2) after digital baseband modulator resets, power amplifier enables to control the mod_pa_on signal and is dragged down, and closes to guarantee radio-frequency power amplifier PA;
3) unless be operated in test pattern and change with BBA/ radio-frequency power amplifier PA interface, otherwise the higher bit of modulator control register should be changed to 0;
(3) modulation mode of operation:
1. as long as digital baseband modulator is under the enabled state, in the initial moment of each request modulating data, modulator produces an interruption that sends to the DSP interrupt handler;
2. DSP can begin to transmit data;
3. digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, utilize modulation rate and to the modulation chip count, decode channel code chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number and modulation chip sequence number at random;
4. digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, respectively synchronously to channel code generator, scrambler generator or intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal;
5. digital baseband modulator is under the driving of master timer chip timings enable signal, work clock, synchronously receive from channel code generator, scrambler generator at random, the perhaps chip sent of intermediate sequence generator, and the data of synchronously DSP being sent are sent into expander by turn, finish channelizing expansion and scrambler expansion at random, and baseband filtering;
(4) digital baseband modulator stops:
1. when digital baseband modulator stops, DSP receive last request modulating data, have no progeny in from modulator, DSP should wait at least that 13 chip period guarantee that baseband filter sends wherein remaining data, and modulator cuts out radio-frequency power amplifier PA;
2. then, DSP is set to 0 by digital baseband modulator being enabled indication bit MOD_EN, and modulator is not worked;
3. DSP guarantees to close radio-frequency power amplifier PA simultaneously;
4. after, DSP can notify CPU to close the clock of digital baseband modulator.
Description of drawings
Fig. 1 is a system block diagram of realizing the digital baseband modulated process.
Fig. 2 is the inside composition frame chart of digital baseband modulator.
Fig. 3 is the block diagram of modulator control device module.
Fig. 4 is the memory-mapped registers group schematic diagram of data interface module.
To be expander be connected block diagram with input/output signal between other module to Fig. 5.
Embodiment
Embodiment 1: the formation block diagram of the digital baseband modulating system of realization TD-SCDMA, the B3G that the present invention of being shown in Figure 1 proposes (Beyond 3G), 4G (the 4th third-generation mobile communication) terminal, and this digital baseband modulating system is made of following functional module:
1, DSP nuclear: DSP nuclear is provided for finishing the data of digital baseband modulation to digital baseband modulator, and starts and close the necessary digital baseband modulator of digital baseband modulated process and enable indication; For the digital baseband modulated process, exist input and output to be connected between DSP nuclear and DSP programmable interrupt controller, digital baseband processor, system's master timer, searcher, the clock generator; Wherein, the DSP stone grafting is received the interrupt signal of sending from the DSP clock signal and the DSP programmable interrupt controller of clock generator output; DSP by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, data to be modulated and digital baseband modulator are enabled indication send to digital baseband modulator; DSP nuclear control searcher is to the search procedure of network cell; DSP nuclear also is responsible for the control system master timer and is indicated update system master's timing signal synchronously according to searcher locking cell downlink;
2, clock generator: clock generator provides the work clock signal to these modules with DSP nuclear, DSP programmable interrupt controller, cpu subsystem, digital baseband modulator, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, system's master timer, the searcher at random; Clock generator also provides digital baseband modulator reset signal mod_rst_b to digital baseband modulator, realizes resetting to digital baseband modulator;
3, DSP programmable interrupt controller: for the digital baseband modulated process, exist input and output to be connected between DSP programmable interrupt controller and digital baseband modulator, DSP nuclear, the clock generator; The DSP programmable interrupt controller receives the interrupt request singal from digital baseband modulator, generates the interrupt request singal that is used to finish the digital baseband modulation that sends to DSP nuclear according to the latter; The DSP programmable interrupt controller receives the clock signal from clock generator;
4, cpu subsystem: for the digital baseband modulated process, exist input and output to be connected between cpu subsystem and digital baseband modulator, the clock generator; Cpu subsystem provides CPU idle signal, CPU to enter the park mode signal to digital baseband modulator, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Cpu subsystem receives the clock signal from clock generator;
5, digital baseband modulator: digital baseband modulator is responsible for finishing channelizing expansion modulation, the scrambler expansion is modulated and baseband filtering at random; Digital baseband modulator comprises data interface module, modulator control device, expander, clock generating module, baseband filter; Digital baseband modulator is with DSP nuclear, DSP programmable interrupt controller, system's master timer, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, cpu subsystem, rf frequency synthesizer, radio-frequency power amplifier, clock generator, the Analog Baseband at random;
Digital baseband modulator by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, the data to be modulated and the digital baseband modulator that receive from the output of DSP nuclear enable indication; Digital baseband modulator receives the work clock signal from clock generator, operation under the work clock signal drives; The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided digital baseband modulator, realizes resetting to digital baseband modulator; Digital baseband modulator receives the master timer chip timings enable signal from system's master timer, expands the chip synchronization reference signal of modulation as self; CPU idle signal, CPU that digital baseband modulator receives from cpu subsystem output enter the park mode signal, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Digital baseband modulator receives the automatic frequency control locking signal from the output of rf frequency synthesizer, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time opens or close radio-frequency power amplifier;
Digital baseband modulator is regularly to DSP programmable interrupt controller output interrupt requests; Digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, synchronously respectively to channel code generator, scrambler generator or intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal; Similarly, under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, digital baseband modulator is synchronously respectively from the channel code generator, scrambler generator, intermediate sequence generator obtain channel code, scrambler, intermediate sequence sign indicating number at random at random; Digital baseband modulator enables control signal with radio-frequency power amplifier and sends to radio-frequency power amplifier; The data that digital baseband modulator will be finished modulation send to Analog Baseband;
6, channel code generator: exist input and output to be connected between channel code generator and digital baseband modulator, the clock generator; The channel code generator receives channel code chip sequence number and the request signal from digital baseband modulator output, channel code chip sequence number and request signal according to digital baseband modulator output produce channel code, and the channel code that produces is sent to digital baseband modulator; The channel code generator receives the work clock signal from clock generator, operation under the work clock signal drives;
7, scrambler generator at random: exist input and output to be connected between scrambler generator and digital baseband modulator, the clock generator at random; The scrambler generator receives chip sequence number of scrambler at random and the request signal from digital baseband modulator output at random, chip sequence number of scrambler at random and request signal according to digital baseband modulator output produce scrambler at random, and the scrambler at random that will produce sends to digital baseband modulator; The scrambler generator receives the work clock signal from clock generator at random, operation under the work clock signal drives;
8, intermediate sequence generator: exist input and output to be connected between intermediate sequence generator and digital baseband modulator, the clock generator; The intermediate sequence generator receives intermediate sequence chip sequence number and the request signal from digital baseband modulator output, intermediate sequence chip sequence number and request signal according to digital baseband modulator output produce the intermediate sequence sign indicating number, and the intermediate sequence sign indicating number that produces is sent to digital baseband modulator; Intermediate sequence sign indicating number generator receives the work clock signal from clock generator, operation under the work clock signal drives;
9, rf frequency synthesizer: for digital baseband modulation, the rf frequency synthesizer is examined with DSP, exist input and output to be connected between the digital baseband modulator; The rf frequency synthesizer receives frequency synthesis and the lock control signal from DSP nuclear, whether control the situation of locking radio frequency frequency according to automatic frequency, to digital baseband modulator output automatic frequency control locking signal, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time open or close radio-frequency power amplifier;
10, system's master timer: for digital baseband modulation, exist input and output to be connected between system's master timer and DSP nuclear, searcher, digital baseband modulator, the clock generator; System's master timer is indicated synchronously according to searcher locking cell downlink under the DSP nuclear control, receives the downlink synchronous signal from searcher, is used for update system master timing signal; System's master timer is used to the downlink synchronous signal from searcher, produces initial timing signal and the ascending time slot chip timings enable signal of ascending time slot that sends to digital baseband modulator; It sends the initial timing signal of ascending time slot to digital baseband modulator at the initial preceding 1/16 chip place of ascending time slot, and each chip after ascending time slot is initial begins preceding 1/16 chip place to ascending time slot chip timings enable signal of digital baseband modulator transmission; The system master timer receive from clock generator the work clock signal.
Each signal description of interface is shown in table 1-1 between digital baseband modulator among Fig. 1 and other functional module.
Embodiment 2: Fig. 2 is the inside composition frame chart of the digital baseband modulator shown in Fig. 1, and this digital baseband modulator is made of following functional module:
1, clock generating module: clock generating module and outside clock generator, and exist input and output to connect between the data interface module of digital baseband modulator inside, modulator control device module, expander module, baseband filter module.The clock generating module receives the clock signal from clock generator, produces the work clock signal that offers inner each functional module of digital baseband modulator.The clock generating submodule is received 2 clock signals from clock generator, mod_clk (this clock be spread-spectrum code chip speed N doubly, as 16 times, 32 times etc.), the DSP clock---" clkout_dsp ".
16 times of spreading rate clocks (note is made ck_cx16) of the work clock signal of inner each functional module of digital baseband modulator are produced by this clock generating module, and under modulator clock enable signal mod_clken gate, as the clock source of each functional module of digital baseband modulator inside.
Inner 16 times of spreading rate clocks are from a local caches output, being input as by the mod_clk signal of synchronous again modulator clock enable signal mod_clken institute gate of this local caches disturbed to avoid inner 16 times of fast clocks to be subjected to short-time pulse waveform.The delay of local clock buffer and type by the zone of local load capacitance and chip forming process delay with route postpone determined.Modulator clock enable signal mod_clken is from master clock module (clock generator).
The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided the clock generating module, produces the synchronous reset signal srst_b of digital baseband modulator.Synchronous reset signal srst_b produces modulator reset signal mod_rst_b by the 16 times of fast clocks in inside with gate synchronously again, is in definite state to guarantee all registers after the deexcitation that resets.
2, data interface module: Fig. 4 illustrates the memory-mapped registers group of data interface module.Data interface module provides the data-interface of digital baseband modulator and DSP, realizes the data communication between digital baseband modulator and the DSP.The register (memory-mapped register) relevant with DSP all is placed in this module in the digital baseband modulator that table 1-2 lists, and digital baseband modulator can directly be conducted interviews to these registers.These registers also can directly be read by DSP.Shown in Fig. 4.
Data interface module and outside DSP nuclear, and exist input and output to connect between the inner modulator control device module, expander module, clock generating module.Data interface module receive from DSP nuclear by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, to the visit of internal memory mapping register.Data interface module receives the work clock from the clock generating module.Data interface module receive from the modulator control device the shift enable signal of each channel data.Data interface module enables modulation rate, digital baseband modulator indication bit, ascending time slot transmission enable signal, power amplifier parameter warm-up time, the invalid index signal of Analog Baseband clock and sends data switching index signal to send to the modulator control device.Also under the shift enable signal effect from the modulator control device, the transfer of data of with selected transmission rate each channel being deposited by data serializer arrives expander module to data interface module.
(1) system register: the system register group comprises 2 I/O mouth registers, and they are used for controlling modulator block.The channel quantity that these registers and modulator block design are supported is irrelevant.These 2 registers comprise the physics flip and flop generator, are readable writing to DSP.
(2) service register group: the service register group comprises the gain register and the data register of all channels.
(3) data serializer: data interface module also comprises data serializer, and the transfer of data that data serializer is deposited each channel with selected transmission rate arrives expander module.As shown in Figure 4.When being activated, the data of these registers will be moved out of when shift enable signal (being produced by the digital baseband modulator controller module).
3, modulator control device module: Fig. 3 is the block diagram of modulator control device module MOD_CTRL.Modulator control device module is the vital part of digital baseband modulator, all submodules of control figure baseband modulator; Modulator control device module is with outside cpu subsystem, system's master timer, DSP programmable interrupt controller, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, Analog Baseband, radio-frequency power amplifier, the rf frequency synthesizer at random; Simultaneously, modulator control device module also with between the data interface module of digital baseband modulator inside, expander module, baseband filter module, the clock generating module exists input and output to be connected; The modulator control device receives master timer chip timings enable signal and the ascending time slot enable signal from system's master timer, reception is from the modulation rate of data interface module, the digital baseband modulator enable signal, ascending time slot transmission enable signal, power amplifier parameter warm-up time, invalid index signal of Analog Baseband clock and transmission data are switched index signal, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception is from the CPU free time of cpu subsystem, CPU enters sleep signal, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; Modulator control device module is according to parameter and the signal received, at the ascending time slot enable signal, under the driving of master timer chip timings enable signal and work clock, channel code chip sequence number is sent to the channel code generator, scrambler chip sequence number sends to scrambler generator at random at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the digital baseband modulator interrupt request singal of DSP programmable interrupt controller, generation sends to the digital baseband modulator chip timings enable signal of baseband filter, the power amplifier that generation sends to radio-frequency power amplifier enables control signal, generation sends to the difference tranmitting data register of analog baseband, produces the multiplexing selection signal and the phase count that send to baseband filter;
As shown in Figure 3, the modulation controller module is made of following submodule:
(1) sequence number decoder: system's master timer, the channel code generator of sequence number decoder and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, between the data interface module of sequence number decoder and digital baseband modulator inside, the clock generator module, and with the enable signal generator of modulator control device inside modules between exist input and output to be connected; The sequence number decoder receives the reference signal of modulating chip count from the ascending time slot enable signal of system's master timer as up expansion, the sequence number decoder receives the modulation rate from data interface module, reception is from the digital baseband modulator chip timings enable signal of the enable signal generator of modulator control device inside modules, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The sequence number decoder is according to the signal and the data parameter that receive, decodes channel code chip sequence number, scrambler chip sequence number, intermediate sequence sequence number at random, and modulation chip sequence number; The sequence number decoder is under the driving of digital baseband modulator chip timings enable signal and work clock, channel code chip sequence number is sent to the channel code generator, scrambler chip sequence number sends to scrambler generator at random at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, modulation chip sequence number is sent to the enable signal generator of modulator control device inside modules;
(2) enable signal generator: system's master timer, the channel code generator of enable signal generator and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, the enable signal generator is also and between the data interface module of digital baseband modulator inside, expander module, baseband filter module, clock generator module, and exists input and output to be connected between the sequence number decoder of modulator control device inside modules and the interrupt signal generator; The enable signal generator generates the employed enable signal of all modulators; All enable signals all are pulse train, and each pulse duration is 1/16 chip; The reception of enable signal generator is led regularly the chip timings enable signal as the chip timings reference signal from system's master timer, reception is from the modulation rate of data interface module with from the modulation chip sequence number of sequence number decoder, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The enable signal generator is according to above-mentioned signal and the data parameter received, under main regularly chip timings enable signal and work clock driving, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the sequence number decoder, the digital baseband modulator chip timings enable signal of baseband filter and timing controling signal generator, also produce the power amplifier that sends to the power control signal generator and enable control signal, and produce the symbol enable signal that sends to the interrupt signal generator;
(3) interrupt signal generator: exist input and output to be connected between the DSP programmable interrupt controller of interrupt signal generator and digital baseband modulator outside; Simultaneously, the interrupt signal generator is also and between the digital baseband modulator clock internal generator module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The interrupt signal generator receives the symbol enable signal from the enable signal generator, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The interrupt signal generator produces the digital baseband modulator interrupt request singal that sends to the DSP programmable interrupt controller according to the symbol enable signal; Interrupt generator and periodically the DSP programmable interrupt controller is produced the digital baseband modulator interruption; This interrupt request singal produces at first at each data symbol that will modulate; Interrupt rate is 20KHz;
(4) power control signal generator: exist input and output to be connected between the radio-frequency power amplifier of power control signal generator and digital baseband modulator outside, rf frequency synthesizer, the cpu subsystem; Simultaneously, the power control signal generator also with between the data interface module of digital baseband modulator inside, the clock generator module exists input and output to be connected; The power control signal generator is that radio-frequency power amplifier produces the power control signal; The power control signal generator receives digital baseband modulator enable signal, ascending time slot transmission enable signal and power amplifier parameter warm-up time from data interface module, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception enters sleep signal from CPU free time, the CPU of cpu subsystem, and receives 16 times of spreading rate clock signals in inside and synchronous reset signal from the clock generating module; The power control signal generator produces the power amplifier that sends to radio-frequency power amplifier and enables control signal according to the signal that receives;
(5) timing controling signal generator: exist input and output to be connected between the Analog Baseband of timing controling signal generator and digital baseband modulator outside; Simultaneously, the timing controling signal generator is also and between the data interface module of digital baseband modulator inside, baseband filter module, clock generator module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The timing controling signal generator is that baseband filter BBF and analog baseband BBA produce clock control signal; The timing controling signal generator receives digital baseband modulator enable signal, the invalid index signal of Analog Baseband clock from data interface module and sends data and switches index signal, reception is from the digital baseband modulator chip timings enable signal of enable signal generator, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The timing controling signal generator is according to the signal that receives, under the driving of digital baseband modulator chip timings enable signal and work clock, generation sends to the difference tranmitting data register of analog baseband, produces the multiplexing selection signal and the phase count that send to baseband filter.
Table 1-3 provides the description of the input/output signal of said modulator controller submodule.
4, expander module: expander module is with outside channel code generator, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random.Simultaneously, expander module also with between the data interface module of digital baseband modulator inside, modulator control device module, baseband filter module, the clock generating module exists input and output to be connected.Expander receives the expansion enable signal from the modulator control device, reception is from the modulating data for the treatment of of each channel of data interface module, reception is from the channel code chip of channel code generator, reception is from the chip of scrambler at random of scrambler generator at random, reception receives the work clock from the clock generating module from the intermediate sequence sign indicating number chip of intermediate sequence generator.Expander module is according to the signal that receives, finishes the channelizing expansion modulation for the treatment of modulating data and scrambler expansion modulation at random from each channel of data interface module.The data that expander module will be finished modulation send to baseband filter.As shown in Figure 5.
5, baseband filter: exist input and output to be connected between baseband filter and the outside Analog Baseband.Simultaneously, baseband filter also with between the modulator control device module of digital baseband modulator inside, expander module, the clock generating module exists input and output to be connected.Baseband filter receives from the digital baseband modulator chip timings enable signal of modulator control device, multiplexing selection signal and phase count, receives the modulating data from expander module, receives the work clock from the clock generating module.Expander module is according to the signal that receives, finishes the baseband filtering from the modulating data of expander module.The data that baseband filter will be finished baseband filtering send to the Analog Baseband processing subsystem.
Embodiment 3: this digital baseband modulating system has four kinds of mode of operation patterns: the modulator " shut " mode"; The modulator initialize mode; The modulation mode of operation; The modulator termination pattern.
1. digital baseband modulator " shut " mode": when the digital baseband modulator " shut " mode", digital baseband modulator is not worked thereby CPU closes the clock of modulator; The asynchronous reset signal that clock generator is issued digital baseband modulator should keep invalid, because this signal low level is effective, thereby is high level at this moment; It is 0 that digital baseband modulator in the modulator control register enables indication bit MOD_EN;
2. digital baseband modulator initialization: when travelling carriage will send access channel or reverse traffic channel data, earlier will be before sending data finishing initialization step; (1) at first, CPU will enable the clock of digital baseband modulator; (2) then, it waits for 3 modulator clock cycle at least, just provides asynchronous reset signal to digital baseband modulator; (3) it is effective that asynchronous reset signal will keep at least 2 modulator clock cycle, then just by deexcitation; (4) simultaneously, CPU sends to DSP with the information that is necessary such as radio-frequency power amplifier PA warm-up time etc.; (5) when digital baseband modulator sends data, CPU will draw high that 2 control bits---CPU idle signal IDLE_B and CPU enter the level of park mode signal SLEEP_B, starts work to realize digital baseband modulator control radio-frequency power amplifier PA; (6) after the digital baseband modulator asynchronous reset signal is by the CPU deexcitation, DSP reply radio-frequency power amplifier PA preheating register is provided with suitable numerical value; The value of all DSP memory-mapped registers is both initialized to 0; (7) initialization final step is carried out initialization to the control register of digital baseband modulator; 1) if it is 0 that digital baseband modulator enables indication bit MOD_EN, digital baseband modulator does not provide regularly, and most of internal register will can not change; 2) after digital baseband modulator resets, power amplifier enables to control the mod_pa_on signal and is dragged down, and closes to guarantee radio-frequency power amplifier PA; 3) unless be operated in test pattern and change with BBA/ radio-frequency power amplifier PA interface, otherwise the higher bit of modulator control register should be changed to 0;
3. modulation mode of operation: (1) as long as digital baseband modulator is under the enabled state, in the initial moment of each request modulating data, modulator produces an interruption that sends to the DSP interrupt handler; (2) DSP can begin to transmit data; (3) digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, utilize modulation rate and to the modulation chip count, decode channel code chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number and modulation chip sequence number at random; (4) digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, respectively synchronously to channel code generator, scrambler generator or intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal; (5) digital baseband modulator is under the driving of master timer chip timings enable signal, work clock, synchronously receive from channel code generator, scrambler generator at random, the perhaps chip sent of intermediate sequence generator, and the data of synchronously DSP being sent are sent into expander by turn, finish channelizing expansion and scrambler expansion at random, and baseband filtering;
4. digital baseband modulator stops: 1. when digital baseband modulator stops, DSP receive last request modulating data, have no progeny in from modulator, DSP should wait at least that 13 chip period guarantee that baseband filter sends wherein remaining data, and modulator cuts out radio-frequency power amplifier PA; 2. then, DSP is set to 0 by digital baseband modulator being enabled indication bit MOD_EN, and modulator is not worked; 3. DSP guarantees to close radio-frequency power amplifier PA simultaneously; 4. after, DSP can notify CPU to close the clock of digital baseband modulator.
What need understand is: though the foregoing description is to the present invention's detailed explanation of contrasting; but these explanations, just to simple declaration of the present invention, rather than limitation of the present invention; any innovation and creation that do not exceed in the connotation of the present invention all fall within the scope of protection of the present invention.Interface signal between table 1-1 digital baseband modulator and the external function module is described
Table 1-2 digital baseband modulator memory-mapped register
| The register title | Describe | The address |
| The base address | ? | Determine as required |
| The register title | ? | Address offset |
| MOD_CTRL | The modulator control register | 0xCBC0 |
| PA_WARMUP | Power amplifier preheating (pa warmup) register | 0xCBC2 |
| MOD2K_PDCH_GAIN | The uplink special physical channel gain register | 0xCBE7 |
| MOD2K_PRACH_GAIN | The Physical Random Access Channel gain register | 0xCBE8 |
| MOD2K_PUSCH_GAIN | Up shared physical channel gain register | 0xCBE9 |
| MOD2K_PDCH_DATA | The uplink special physical channel data register | 0xCBEC |
| MOD2K_PRACH_DATA | The Physical Random Access Channel data register | 0xCBED |
| MOD2K_PUSCH_LSW_DATA | Up shared physical channel hangs down bit (LSW) data register | 0xCBEE |
| MOD2K_PUSCH_MSW_DATA | Up shared physical channel higher bit position (MSW) data register | 0xCBEF |
The description of the input/output signal of table 1-3 modulator control device submodule
Claims (4)
1. the digital baseband modulating system of a TD-SCDMA, Beyond 3G, the 4th third-generation mobile communication terminal, it is characterized in that: this digital baseband modulating system is made of following functional module:
(1) DSP nuclear: DSP nuclear is provided for finishing the data of digital baseband modulation to digital baseband modulator, and starts and close the necessary digital baseband modulator of digital baseband modulated process and enable indication; For the digital baseband modulated process, exist input and output to be connected between DSP nuclear and DSP programmable interrupt controller, digital baseband modulator, system's master timer, searcher, the clock generator; Wherein, the DSP stone grafting is received the interrupt signal of sending from the DSP clock signal and the DSP programmable interrupt controller of clock generator output; DSP nuclear by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, data to be modulated and digital baseband modulator are enabled indication send to digital baseband modulator; DSP nuclear control searcher is to the search procedure of network cell; DSP nuclear also is responsible for the control system master timer and is indicated update system master's timing signal synchronously according to searcher locking cell downlink;
(2) clock generator: clock generator provides the work clock signal to these modules with DSP nuclear, DSP programmable interrupt controller, cpu subsystem, digital baseband modulator, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, system's master timer, the searcher at random; Clock generator also provides digital baseband modulator reset signal mod_rst_b to digital baseband modulator, realizes resetting to digital baseband modulator;
(3) DSP programmable interrupt controller: for the digital baseband modulated process, exist input and output to be connected between DSP programmable interrupt controller and digital baseband modulator, DSP nuclear, the clock generator; The DSP programmable interrupt controller receives the interrupt request singal from digital baseband modulator, generates the interrupt request singal that is used to finish the digital baseband modulation that sends to DSP nuclear according to the latter; The DSP programmable interrupt controller receives the clock signal from clock generator;
(4) cpu subsystem: for the digital baseband modulated process, exist input and output to be connected between cpu subsystem and digital baseband modulator, the clock generator; Cpu subsystem provides CPU idle signal, CPU to enter the park mode signal to digital baseband modulator, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Cpu subsystem receives the clock signal from clock generator;
(5) digital baseband modulator: digital baseband modulator is responsible for finishing channelizing expansion modulation, the scrambler expansion is modulated and baseband filtering at random; Digital baseband modulator comprises data interface module, modulator control device, expander, clock generating module, baseband filter; Digital baseband modulator is with DSP nuclear, DSP programmable interrupt controller, system's master timer, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, cpu subsystem, rf frequency synthesizer, radio-frequency power amplifier, clock generator, the Analog Baseband at random;
Digital baseband modulator by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, the data to be modulated and the digital baseband modulator that receive from the output of DSP nuclear enable indication; Digital baseband modulator receives the work clock signal from clock generator, operation under the work clock signal drives; The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided digital baseband modulator, realizes resetting to digital baseband modulator; Digital baseband modulator receives the master timer chip timings enable signal from system's master timer, expands the chip synchronization reference signal of modulation as self; CPU idle signal, CPU that digital baseband modulator receives from cpu subsystem output enter the park mode signal, so that digital baseband modulator is in time closed radio-frequency power amplifier when CPU free time or dormancy; Digital baseband modulator receives the automatic frequency control locking signal from the output of rf frequency synthesizer, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time opens or close radio-frequency power amplifier;
Digital baseband modulator is regularly to DSP programmable interrupt controller output interrupt requests; Digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, synchronously respectively to channel code generator, scrambler generator and intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal; Similarly, under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, digital baseband modulator is synchronously respectively from the channel code generator, scrambler generator, intermediate sequence generator obtain channel code, scrambler, intermediate sequence sign indicating number at random at random; Digital baseband modulator enables control signal with radio-frequency power amplifier and sends to radio-frequency power amplifier; The data that digital baseband modulator will be finished modulation send to Analog Baseband;
(6) channel code generator: exist input and output to be connected between channel code generator and digital baseband modulator, the clock generator; The channel code generator receives channel code chip sequence number and the request signal from digital baseband modulator output, channel code chip sequence number and request signal according to digital baseband modulator output produce channel code, and the channel code that produces is sent to digital baseband modulator; The channel code generator receives the work clock signal from clock generator, operation under the work clock signal drives;
(7) scrambler generator at random: exist input and output to be connected between scrambler generator and digital baseband modulator, the clock generator at random; The scrambler generator receives chip sequence number of scrambler at random and the request signal from digital baseband modulator output at random, chip sequence number of scrambler at random and request signal according to digital baseband modulator output produce scrambler at random, and the scrambler at random that will produce sends to digital baseband modulator; The scrambler generator receives the work clock signal from clock generator at random, operation under the work clock signal drives;
(8) intermediate sequence generator: exist input and output to be connected between intermediate sequence generator and digital baseband modulator, the clock generator; The intermediate sequence generator receives intermediate sequence chip sequence number and the request signal from digital baseband modulator output, intermediate sequence chip sequence number and request signal according to digital baseband modulator output produce the intermediate sequence sign indicating number, and the intermediate sequence sign indicating number that produces is sent to digital baseband modulator; Intermediate sequence sign indicating number generator receives the work clock signal from clock generator, operation under the work clock signal drives;
(9) rf frequency synthesizer: for digital baseband modulation, the rf frequency synthesizer is examined with DSP, exist input and output to be connected between the digital baseband modulator; The rf frequency synthesizer receives frequency synthesis and the lock control signal from DSP nuclear, whether control the situation of locking radio frequency frequency according to automatic frequency, to digital baseband modulator output automatic frequency control locking signal, so that digital baseband modulator shows according to automatic frequency control lock definiteness, in time open or close radio-frequency power amplifier;
(10) system's master timer: for digital baseband modulation, exist input and output to be connected between system's master timer and DSP nuclear, searcher, digital baseband modulator, the clock generator; System's master timer is indicated synchronously according to searcher locking cell downlink under the DSP nuclear control, receives the downlink synchronous signal from searcher, is used for update system master timing signal; System's master timer is used to the downlink synchronous signal from searcher, produces initial timing signal and the ascending time slot chip timings enable signal of ascending time slot that sends to digital baseband modulator; It sends the initial timing signal of ascending time slot to digital baseband modulator at the initial preceding 1/16 chip place of ascending time slot, and each chip after ascending time slot is initial begins preceding 1/16 chip place to ascending time slot chip timings enable signal of digital baseband modulator transmission; The system master timer receive from clock generator the work clock signal.
2. the digital baseband modulating system of TD-SCDMA according to claim 1, Beyond 3G, the 4th third-generation mobile communication terminal is characterized in that, this digital baseband modulator is made of following functional module:
(1) clock generating module: clock generating module and outside clock generator, and exist input and output to connect between the data interface module of digital baseband modulator inside, modulator control device module, expander module, baseband filter module; The clock generating module receives the clock signal from clock generator, produces the work clock signal that offers inner each functional module of digital baseband modulator; The clock generating submodule is received 2 clock signals from clock generator, mod_clk clock and DSP clock, and the N that described mod_clk clock is a spread-spectrum code chip speed times, by synchronous again modulator clock enable signal mod_clken institute gate;
16 times of spreading rate clocks of the work clock signal of inner each functional module of digital baseband modulator are produced by this clock generating module, and under modulator clock enable signal mod_clken gate, as the clock source of each functional module of digital baseband modulator inside;
Inner 16 times of spreading rate clocks are from a local clock buffer output, being input as by the mod_clk signal of synchronous again modulator clock enable signal mod_clken institute gate of this local clock buffer disturbed to avoid inner 16 times of spreading rate clocks to be subjected to short-time pulse waveform; The delay of local clock buffer and type are determined by the zone delay and the route delay of local load capacitance and chip forming process; Modulator clock enable signal mod_clken is from master clock module---clock generator;
The digital baseband modulator reset signal mod_rst_b that provides from clock generator also is provided the clock generating module, produces the synchronous reset signal srst_b of digital baseband modulator; Synchronous reset signal srst_b produces modulator reset signal mod_rst_b by the 16 times of spreading rate clocks in inside with gate synchronously again, is in definite state to guarantee all registers after the deexcitation that resets;
(2) data interface module: data interface module provides the data-interface of digital baseband modulator and DSP nuclear, realizes the data communication between digital baseband modulator and the DSP nuclear; Memory-mapped register relevant with DSP nuclear in the digital baseband modulator all is placed in this module, and digital baseband modulator can directly be conducted interviews to these registers; These registers also can directly be read by DSP nuclear;
Data interface module and outside DSP nuclear, and exist input and output to connect between the inner modulator control device module, expander module, clock generating module; Data interface module receive from DSP nuclear by DSP address bus, DSP data/address bus, DSP write enable signal, DSP reads enable signal, DSP clock signal, to the visit of internal memory mapping register; Data interface module receives the work clock from the clock generating module; Data interface module receives the shift enable signal from each channel data of modulator control device; Data interface module enables modulation rate, digital baseband modulator indication bit, ascending time slot transmission enable signal, power amplifier parameter warm-up time, the invalid index signal of Analog Baseband clock and sends data switching index signal to send to the modulator control device; Also under the shift enable signal effect from the modulator control device, the transfer of data of with selected transmission rate each channel being deposited by data serializer arrives expander module to data interface module;
(3) modulator control device module: modulator control device module is the vital part of digital baseband modulator, all submodules of control figure baseband modulator; Modulator control device module is with outside cpu subsystem, system's master timer, DSP programmable interrupt controller, channel code generator, exist input and output to be connected between scrambler generator, intermediate sequence generator, Analog Baseband, radio-frequency power amplifier, the rf frequency synthesizer at random; Simultaneously, modulator control device module also with between the data interface module of digital baseband modulator inside, expander module, baseband filter module, the clock generating module exists input and output to be connected; The modulator control device receives master timer chip timings enable signal and the ascending time slot enable signal from system's master timer, reception is from the modulation rate of data interface module, the digital baseband modulator enable signal, ascending time slot transmission enable signal, power amplifier parameter warm-up time, invalid index signal of Analog Baseband clock and transmission data are switched index signal, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception is from the CPU free time of cpu subsystem, CPU enters sleep signal, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; Modulator control device module is according to parameter and the signal received, at the ascending time slot enable signal, under the driving of master timer chip timings enable signal and work clock, with channel code chip sequence number send to the channel code generator and will be at random scrambler chip sequence number send to scrambler generator at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the digital baseband modulator interrupt request singal of DSP programmable interrupt controller, generation sends to the digital baseband modulator chip timings enable signal of baseband filter, the power amplifier that generation sends to radio-frequency power amplifier enables control signal, generation sends to the difference tranmitting data register of Analog Baseband, produces the multiplexing selection signal and the phase count that send to baseband filter;
(4) expander module: expander module is with outside channel code generator, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, expander module also with between the data interface module of digital baseband modulator inside, modulator control device module, baseband filter module, the clock generating module exists input and output to be connected; Expander receives the expansion enable signal from the modulator control device, reception is from the modulating data for the treatment of of each channel of data interface module, reception is from the channel code chip of channel code generator, reception is from the chip of scrambler at random of scrambler generator at random, reception receives the work clock from the clock generating module from the intermediate sequence sign indicating number chip of intermediate sequence generator; Expander module is according to the signal that receives, finishes the channelizing expansion modulation for the treatment of modulating data and scrambler expansion modulation at random from each channel of data interface module; The data that expander module will be finished modulation send to baseband filter;
(5) baseband filter: exist input and output to be connected between baseband filter and the outside Analog Baseband; Simultaneously, baseband filter also with between the modulator control device module of digital baseband modulator inside, expander module, the clock generating module exists input and output to be connected; Baseband filter receives from the digital baseband modulator chip timings enable signal of modulator control device, multiplexing selection signal and phase count, receives the modulating data from expander module, receives the work clock from the clock generating module; Expander module is according to the signal that receives, finishes the baseband filtering from the modulating data of expander module; The data that baseband filter will be finished baseband filtering send to Analog Baseband.
3. the digital baseband modulating system of TD-SCDMA according to claim 1, Beyond 3G, the 4th third-generation mobile communication terminal is characterized in that: this modulator control device is made of following submodule:
(1) sequence number decoder: system's master timer, the channel code generator of sequence number decoder and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, between the data interface module of sequence number decoder and digital baseband modulator inside, the clock generating module, and with the enable signal generator of modulator control device inside modules between exist input and output to be connected; The sequence number decoder receives the reference signal of modulating chip count from the ascending time slot enable signal of system's master timer as up expansion, the sequence number decoder receives the modulation rate from data interface module, reception is from the digital baseband modulator chip timings enable signal of the enable signal generator of modulator control device inside modules, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The sequence number decoder is according to the signal and the data parameter that receive, decodes channel code chip sequence number, scrambler chip sequence number, intermediate sequence sequence number at random, and modulation chip sequence number; The sequence number decoder is under the driving of digital baseband modulator chip timings enable signal and work clock, with channel code chip sequence number send to the channel code generator and will be at random scrambler chip sequence number send to scrambler generator at random, perhaps intermediate sequence chip sequence number is sent to the intermediate sequence generator, modulation chip sequence number is sent to the enable signal generator of modulator control device inside modules;
(2) enable signal generator: system's master timer, the channel code generator of enable signal generator and digital baseband modulator outside, exist input and output to be connected between scrambler generator, the intermediate sequence generator at random; Simultaneously, the enable signal generator is also and between the data interface module of digital baseband modulator inside, expander module, baseband filter module, clock generating module, and exists input and output to be connected between the sequence number decoder of modulator control device inside modules and the interrupt signal generator; The enable signal generator generates the employed enable signal of all modulators; All enable signals all are pulse train, and each pulse duration is 1/16 chip; The reception of enable signal generator is led regularly the chip timings enable signal as the chip timings reference signal from system's master timer, reception is from the modulation rate of data interface module with from the modulation chip sequence number of sequence number decoder, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The enable signal generator is according to above-mentioned signal and the data parameter received, under main regularly chip timings enable signal and work clock driving, generation send to the channel code generator and at random the scrambler generator the sign indicating number request signal, perhaps produce the intermediate sequence sign indicating number request signal that sends to the intermediate sequence generator, and generation sends to the shift enable signal of each channel of data interface module, generation sends to the expansion enable signal of expander, generation sends to the sequence number decoder, the digital baseband modulator chip timings enable signal of baseband filter and timing controling signal generator, also produce the power amplifier that sends to the power control signal generator and enable control signal, and produce the symbol enable signal that sends to the interrupt signal generator;
(3) interrupt signal generator: exist input and output to be connected between the DSP programmable interrupt controller of interrupt signal generator and digital baseband modulator outside; Simultaneously, the interrupt signal generator is also and between the digital baseband modulator clock internal generation module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The interrupt signal generator receives the symbol enable signal from the enable signal generator, and from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The interrupt signal generator produces the digital baseband modulator interrupt request singal that sends to the DSP programmable interrupt controller according to the symbol enable signal; The interrupt signal generator periodically produces digital baseband modulator to the DSP programmable interrupt controller and interrupts; This interrupt request singal produces at first at each data symbol that will modulate; Interrupt rate is 20KHz;
(4) power control signal generator: exist input and output to be connected between the radio-frequency power amplifier of power control signal generator and digital baseband modulator outside, rf frequency synthesizer, the cpu subsystem; Simultaneously, the power control signal generator also with between the data interface module of digital baseband modulator inside, the clock generating module exists input and output to be connected; The power control signal generator is that radio-frequency power amplifier produces the power control signal; The power control signal generator receives digital baseband modulator enable signal, ascending time slot transmission enable signal and power amplifier parameter warm-up time from data interface module, reception is from the automatic frequency control lock indication signal of rf frequency synthesizer, reception enters sleep signal from CPU free time, the CPU of cpu subsystem, and receives 16 times of spreading rate clock signals in inside and synchronous reset signal from the clock generating module; The power control signal generator produces the power amplifier that sends to radio-frequency power amplifier and enables control signal according to the signal that receives;
(5) timing controling signal generator: exist input and output to be connected between the Analog Baseband of timing controling signal generator and digital baseband modulator outside; Simultaneously, the timing controling signal generator is also and between the data interface module of digital baseband modulator inside, baseband filter module, clock generating module, and exists input and output to be connected between the enable signal generator of modulator control device inside modules; The timing controling signal generator is that baseband filter BBF and Analog Baseband BBA produce clock control signal; The timing controling signal generator receives digital baseband modulator enable signal, the invalid index signal of Analog Baseband clock from data interface module and sends data and switches index signal, reception is from the digital baseband modulator chip timings enable signal of enable signal generator, and reception is from the 16 times of spreading rate clock signals in inside and the synchronous reset signal of clock generating module; The timing controling signal generator is according to the signal that receives, under the driving of digital baseband modulator chip timings enable signal and work clock, generation sends to the difference tranmitting data register of Analog Baseband, produces the multiplexing selection signal and the phase count that send to baseband filter.
4. the digital baseband modulating system of TD-SCDMA according to claim 1, Beyond 3G, the 4th third-generation mobile communication terminal is characterized in that: there are following 4 kinds of mode of operations in this digital baseband modulating system:
(1) digital baseband modulator " shut " mode": when the digital baseband modulator " shut " mode", digital baseband modulator is not worked thereby CPU closes the clock of modulator; The asynchronous reset signal that clock generator is issued digital baseband modulator keeps invalid, because this signal low level is effective, thereby is high level at this moment; It is 0 that digital baseband modulator in the modulator control register enables indication bit MOD_EN;
(2) digital baseband modulator initialization: when travelling carriage will send access channel or reverse traffic channel data, before sending data, will finish initialization step earlier;
1. at first, CPU will enable the clock of digital baseband modulator;
2. then, it waits for 3 modulator clock cycle at least, just provides asynchronous reset signal to digital baseband modulator;
3. it is effective that asynchronous reset signal will keep at least 2 modulator clock cycle, then just by deexcitation;
4. simultaneously, CPU sends to DSP nuclear with the information that is necessary, this information comprises radio-frequency power amplifier PA warm-up time;
5. when digital baseband modulator sends data, CPU will draw high that 2 control bits---CPU idle signal IDLE_B and CPU enter the level of park mode signal SLEEP_B, starts work to realize digital baseband modulator control radio-frequency power amplifier PA;
6. after the digital baseband modulator asynchronous reset signal was by the CPU deexcitation, DSP checked radio-frequency power amplifier PA preheating register suitable numerical value is set; The value of all DSP memory-mapped registers is both initialized to 0;
7. initialization final step is carried out initialization to the control register of digital baseband modulator;
1) if it is 0 that digital baseband modulator enables indication bit MOD_EN, digital baseband modulator does not provide regularly, and most of internal register will can not change;
2) after digital baseband modulator resets, power amplifier enables to control the mod_pa_on signal and is dragged down, and closes to guarantee radio-frequency power amplifier PA;
3) unless be operated in test pattern and change with Analog Baseband BBA/ radio-frequency power amplifier PA interface, otherwise the higher bit of modulator control register is changed to 0;
(3) modulation mode of operation:
1. as long as digital baseband modulator is under the enabled state, in the initial moment of each request modulating data, modulator produces an interruption that sends to the DSP interrupt handler;
2. DSP nuclear begins to transmit data;
3. digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, utilize modulation rate and to the modulation chip count, decode channel code chip sequence number, scrambler chip sequence number, intermediate sequence sign indicating number sign indicating number chip sequence number and modulation chip sequence number at random;
4. digital baseband modulator is under the driving of ascending time slot enable signal, master timer chip timings enable signal, work clock, respectively synchronously to channel code generator, scrambler generator and intermediate sequence generator transmitting channel sign indicating number chip sequence number, scrambler chip sequence number, intermediate sequence chip sequence number at random at random, and corresponding request signal;
5. digital baseband modulator is under the driving of master timer chip timings enable signal, work clock, synchronously receive from channel code generator, scrambler generator at random, the chip of sending with the intermediate sequence generator, and synchronously DSP is authorized the data of coming and send into expander by turn, finish channelizing expansion and scrambler expansion at random, and baseband filtering;
(4) digital baseband modulator stops:
1. when digital baseband modulator stops, DSP nuclear receive last request modulating data, have no progeny in from modulator, DSP nuclear waits for that at least 13 chip period guarantee that baseband filter sends wherein remaining data, and modulator cuts out radio-frequency power amplifier PA;
2. then, DSP nuclear is set to 0 by digital baseband modulator being enabled indication bit MOD_EN, and modulator is not worked;
3. DSP nuclear guarantees to close radio-frequency power amplifier PA simultaneously;
4. after, DSP nuclear notice CPU closes the clock of digital baseband modulator.
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| US8976780B2 (en) * | 2012-09-27 | 2015-03-10 | Blackberry Limited | Uplink timing maintenance upon time alignment timer expiry |
| CN106954250A (en) * | 2017-03-14 | 2017-07-14 | 中国电子科技集团公司第五十四研究所 | It is a kind of to reduce the device of baseband processing chip power consumption |
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