CN101183658A - Method for manufacturing groove and its method for manufacturing image sensor - Google Patents
Method for manufacturing groove and its method for manufacturing image sensor Download PDFInfo
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- CN101183658A CN101183658A CNA200610118301XA CN200610118301A CN101183658A CN 101183658 A CN101183658 A CN 101183658A CN A200610118301X A CNA200610118301X A CN A200610118301XA CN 200610118301 A CN200610118301 A CN 200610118301A CN 101183658 A CN101183658 A CN 101183658A
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Abstract
The invention relates to a groove-forming method in a laminated medium layer, which comprises: a first medium layer is formed on a semiconductor base; a first opening is formed on the first medium layer; a first sacrificial layer is filled in the first opening; at least a second medium layer is formed on the first medium layer, and a second opening is formed on the second medium layer; the second opening is positioned above the first opening, and the depth of the second opening is same with the thickness of the second medium layer; the second sacrificial layer is filled in the second opening; the first sacrificial layer and the second sacrificial layer are removed. The invention has an advantage of capability of forming a better groove contour.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method that in laminated dielectric layer, forms the method for groove and be applied to make MOS image sensor.
Background technology
MOS image sensor (CMOS image sensor, CIS) because its low-power consumption, advantage such as the high speed of response and being widely used on the devices such as digital camera, video camera, palmtop PC, camera mobile phone, its cardinal principle is: become the signal of telecommunication by the photosensitive unit receiving optical signals and by photodiode converts, by metal oxide semiconductor device the described signal of telecommunication is done further processing, and transfer on the storage medium.Along with semiconductor fabrication to the development of high-tech node more and to the requirement of image sensor sensitivity and other aspect of performance, copper replaces the interconnecting metal of aluminium as MOS image sensor gradually.Patent publication No. be US2006/0113622A1 U.S. Patent Publication the manufacture method of a kind of copper as the MOS image sensor of interconnection line.Fig. 1 to Fig. 5 is the generalized section of the CIS manufacture method of the disclosure.As shown in Figure 1, semi-conductive substrate 100 at first is provided, on described Semiconductor substrate 100, form metal oxide semiconductor transistor 104 and photodiode 103, described metal oxide semiconductor transistor 104 and photodiode 103 by shallow trench isolation from 102 isolation of insulating.On described Semiconductor substrate 100, metal oxide semiconductor transistor 104 and photodiode 103, form insulating barrier 108, in described insulating barrier 108, form contact hole 110 and filled conductive material in described contact hole 110.On described insulating barrier 108, form the stack architecture of dielectric layer 112,118,126 and metal carbonyl conducting layer 114,120,130.Pass through to fill in the connecting hole 122 and 128 the metal material electric connection between the described metal conducting layer.Metal carbonyl conducting layer 114,120,130 is a metallic copper, because copper is easy to diffusion and easily oxidized, formation also is formed with barrier layer 116 and 124 on described metal carbonyl conducting layer 114,120 and 130.Described barrier layer 116 and 124 can be a kind of in silicon nitride, carborundum, the carbon nitrogen silicon compound.On described dielectric layer 126 and metal carbonyl conducting layer 130, form a cover layer 132.
As shown in Figure 2, by forming opening 134 in the stack architecture on insulating barrier 108, dielectric layer 112,118,126 and the barrier layer 116,124 of chemical wet etching above described photodiode, the size of described opening 134 bottoms is suitable with the area of photodiode, and described open bottom is exposed described oxide layer 106.
As shown in Figure 3, deposition medium material 134 in described opening 134, described dielectric material 134 can be a silica, the thickness of deposition fills up described opening 134 at least.
As shown in Figure 4, remove the dielectric material 134 of described cover layer 132 tops by photoetching, etching and cmp.Form filter layer (filter) 136, dielectric layer 138 and lenticule 140 in described dielectric material 134 ' top as shown in Figure 5.Structure shown in Figure 5 is a pixel of composing images transducer, light signal is received by photodiode 103 and converts the signal of telecommunication to by lenticule 140, filter layer 136, dielectric material 134 ' back, controls the processing of these signals of telecommunication then by metal oxide semiconductor transistor 104.
There is following defective in the manufacture method of above-mentioned MOS image sensor: opening shown in Figure 2 134 forms by chemical wet etching, yet because the insulating barrier 108 of photodiode 103 tops, dielectric layer 112,118,126 and barrier layer 116,124 stack architecture has bigger thickness, for example its thickness is 2.5 to 3.0um when the three-layer metal conductor layer, thereby cause when etching forms opening 134, being difficult to its profile of control, cause the degree of depth of opening 134 and width to be difficult to the requirement that reaches desirable, to such an extent as to the dielectric material 134 ' of filling has influenced luminous flux or the intensity that arrives photodiode, has reduced the sensitivity of imageing sensor.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of method that in laminated dielectric layer, forms the method for groove and be applied to make MOS image sensor, the unmanageable problem of profile when forming groove in the MOS image sensor that has the manufactured copper interconnection line now to solve.
For achieving the above object, a kind of method that forms groove in laminated dielectric layer provided by the invention comprises: form first dielectric layer in the semiconductor substrate; In described first dielectric layer, form first opening; In described first opening, fill first sacrifice layer; At least form one second dielectric layer on described first dielectric layer, and form second opening in described second dielectric layer, described second opening is positioned at described first opening top, and the degree of depth of described second opening is identical with the thickness of described second dielectric layer; In described second opening, fill second sacrifice layer; Remove described first sacrifice layer and second sacrifice layer.
Described first opening is identical with the live width of second opening.
The method of removing described first sacrifice layer and second sacrifice layer is a wet etching.
Described first sacrifice layer and second sacrifice layer are material of the same race.
Described first sacrifice layer and second sacrifice layer are a kind of or its combination in copper, aluminium, gold, silver, tantalum, titanium, tantalum nitride, titanium nitride, anti-reflecting layer, the photoresist.
Described first dielectric layer and second dielectric layer are a kind of or its combinations in silica, silicon nitride, carborundum, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, carbon nitrogen silicon compound, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, the black diamond.
Accordingly, the present invention also provides a kind of using said method to make the method for MOS image sensor, comprising: the semiconductor substrate is provided, is formed with light-sensitive element in the described semiconductor-based end; On the described semiconductor-based end, form first dielectric layer; Form first irrigation canals and ditches and first opening in described first dielectric layer, wherein said first opening is positioned at described light-sensitive element top, and the degree of depth of this first opening is identical with the thickness of described first dielectric layer; In described first irrigation canals and ditches and first opening, fill first electric conducting material; On described first dielectric layer, form one second dielectric layer at least, and in described second dielectric layer, form second irrigation canals and ditches and second opening, wherein said second opening is positioned at the top of described first opening, and the degree of depth of this second opening is identical with the thickness of described second dielectric layer; In described second irrigation canals and ditches and second opening, fill second electric conducting material; Remove second electric conducting material in described second opening and first electric conducting material in first opening, in described first dielectric layer and second dielectric layer, form groove; Filled media material in described groove; Above described dielectric material, be formed for accepting the lenticule of light signal.
Described first opening is identical with the live width of second opening.
The live width of described first opening and second opening is identical with the live width of described light-sensitive element.
Described first electric conducting material and second electric conducting material are material of the same race.
Described first electric conducting material and second electric conducting material are a kind of or its combination in aluminium, copper, gold, silver, tantalum, titanium, the tantalum nitride.
Remove second electric conducting material in described second opening and first electric conducting material in first opening, the step that forms groove in described first dielectric layer and second dielectric layer comprises: form cover layer on described second dielectric layer; Remove the cover layer of described second electric conducting material top by chemical wet etching; With described cover layer is hard mask, removes second electric conducting material in described second opening and first electric conducting material in first opening by wet etching.
This method further comprises: carry out planarization by cmp behind the filled media material, form a filter before forming lenticule above described dielectric material.
Compared with prior art, the present invention has the following advantages:
The present invention forms groove in laminated dielectric layer method is decomposed into a plurality of etch step with a technology that goes on foot while etching laminated dielectric layer, reduced the degree of depth of each step etching, thereby can be good at controlling the profile of the opening of etching in each step, in the opening of described each step etching, fill the material that has higher etching selection ratio with the respective media layer, it is sacrifice layer, by the sacrifice layer in the step wet etching removal opening, this method can be good at controlling the profile of the groove that etches at last.
The method that forms groove in the laminated dielectric layer of the present invention is applied in the manufacturing process of MOS image sensor, when forming the multiple layer of copper interconnection, form opening in the laminated dielectric layer above light-sensitive element and fill metallic copper, form sacrifice layer, remove sacrifice layer in the opening of dielectric layer of described light-sensitive element top with wet etching then, be scattered in each step copper wiring technique by the technology that etching light-sensitive element top laminated dielectric layer is formed groove, carry out simultaneously with copper wiring technique, not only do not increase extra technology, also reduced the degree of depth of each step etching, reduce the difficulty of etching, more help controlling the profile of the opening that etches; Simultaneously in the opening of each layer dielectric layer, fill metallic copper, and the wet etching by high selectivity removes the copper in the opening of described light-sensitive element top dielectric layer, not only avoided dry etching ionic medium body bombardment damage to the described semiconductor-based end, the technology of more feasible formation groove becomes and is easy to control, and the groove of formation has good profile.Fill single dielectric material in described groove, the imageing sensor of formation has higher sensitivity.
Description of drawings
Fig. 1 to Fig. 5 is the generalized section of existing a kind of each step corresponding structure of MOS image sensor manufacture method;
Fig. 6 to Figure 11 is the generalized section of each step corresponding construction of embodiment that forms the method for groove according to the present invention in laminated dielectric layer;
Figure 12 is the flow chart of the embodiment of the method manufacturing MOS image sensor using the present invention forms groove in laminated dielectric layer;
Figure 13 to Figure 14, Figure 14 a, Figure 15 to Figure 27 make the generalized section of each step corresponding construction of embodiment of MOS image sensor for the method for using the present invention and forming groove.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Below in conjunction with embodiment the method that forms groove in laminated dielectric layer is described in detail.Fig. 6 to Figure 11 is the generalized section of each step corresponding structure of embodiment of the inventive method.
As shown in Figure 6, at first provide semiconductor substrate 300, material of the described semiconductor-based ends 300 can be a kind of in silicon on monocrystalline silicon, polysilicon, amorphous silicon, the insulating barrier, the SiGe composition.On the described semiconductor-based end 300, form first dielectric layer 310.Described first dielectric layer 310 is a kind of in silica, silicon nitride, carborundum, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, carbon nitrogen silicon compound, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, the black diamond.Its formation method is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
As shown in Figure 7, form first opening 320 by chemical wet etching in described first dielectric layer 310, the degree of depth of described first opening 320 is identical with the degree of depth of described first dielectric layer 310.As shown in Figure 8, in described first opening 320, fill the first sacrifice layer 320a.The described first sacrifice layer 320a material is a kind of or its combination in copper, aluminium, gold, silver, tantalum, titanium, tantalum nitride, titanium nitride, anti-reflecting layer, the photoresist.The method of its formation is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), ald, the spin coating.Remove the first sacrifice layer 320a material on described first dielectric layer 310 surfaces by cmp.
As shown in Figure 9, on described first dielectric layer 310, form second dielectric layer 330.Described second dielectric layer 330 is a kind of in silica, silicon nitride, carborundum, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, carbon nitrogen silicon compound, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, the black diamond.Its formation method is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).In described second dielectric layer 330, form second opening 340 by chemical wet etching.The live width of described second opening 340 is identical with the live width of described first opening 320, and the degree of depth is identical with the thickness of described second dielectric layer 330.It is the upper surface that the described first sacrifice layer 320a is all exposed in the bottom of described second opening 340.
As shown in figure 10, in described second opening 340, fill the second sacrifice layer 340a.And remove the second sacrifice layer 340a material on described second dielectric layer 330 surfaces by cmp.The described second sacrifice layer 340a material is identical with the described first sacrifice layer 320a.
As shown in figure 11, remove the second sacrifice layer 340a in described second opening 340 and the first sacrifice layer 320a in described first opening 320, in described second dielectric layer 330 and first dielectric layer 310, form groove 350 by wet etching.Wet etching solution can be selected the described second sacrifice layer 340a and the first sacrifice layer 320a etch rate big and to described second dielectric layer 330 and the less solution of first dielectric layer, 330 etch rates.
The above-mentioned method that forms groove in laminated dielectric layer goes on foot simultaneously with one, and the technology of etching laminated dielectric layer is decomposed into a plurality of etch step, reduced the degree of depth of each step etching, thereby can be good at controlling the profile of the opening of etching in each step, in the opening of described each step etching, fill the material that has high etching selection ratio with the respective media layer, it is sacrifice layer, by the sacrifice layer in the step wet etching removal opening, this method can be good at controlling the profile of the groove that etches at last.Above-mentioned laminated dielectric layer not only can be two-layer, it can be a multilayer, for example three layers, four layers, five layers etc., use the same method and in described multilayer dielectricity layer, form vertically aligned a plurality of opening respectively, and the filling sacrifice layer, remove described sacrifice layer by wet etching at last and just in above-mentioned a plurality of dielectric layers, formed groove.
The above-mentioned method that forms groove in laminated dielectric layer can be applicable to make in the MOS image sensor technology.
Figure 12 is applied to make the process chart of MOS image sensor for the described method that forms groove in laminated dielectric layer.
As shown in figure 12, provide the semiconductor substrate, on described semiconductor, have (S200) of metal oxide semiconductor transistor and light-sensitive element.Described semiconductor-based bottom materials can be a kind of or its combination in silicon on monocrystalline silicon, polysilicon, amorphous silicon, the insulating barrier, the SiGe composition, and described metal oxide semiconductor transistor has source electrode, grid and drain electrode.Described light-sensitive element can be a photodiode.In the described semiconductor-based end, be formed with shallow trench isolation from isolating described metal oxide semiconductor transistor and light-sensitive element with insulation.
On the described semiconductor-based end, form first dielectric layer (S210).Described first dielectric layer is a silica.
In described first dielectric layer, form first irrigation canals and ditches and first opening (S220).Wherein said first opening is positioned at described light-sensitive element top, and the degree of depth of this first opening is identical with the thickness of described first dielectric layer.The width of described first opening is identical with the live width of described light-sensitive element, has enough light signals to arrive described light-sensitive element to guarantee the imageing sensor that forms.Can form interconnection line at the described first irrigation canals and ditches filled conductive material.
In described first irrigation canals and ditches and first opening, fill first electric conducting material (S230).Described first electric conducting material is a kind of or its combination in aluminium, copper, gold, silver, tantalum, titanium, the tantalum nitride.Remove first electric conducting material on described first dielectric layer by cmp.
On described first dielectric layer, form one second dielectric layer at least, and in described second dielectric layer, form second irrigation canals and ditches and second opening (S240).Wherein said second opening is positioned at the top of described first opening, and the degree of depth of this second opening is identical with the thickness of described second dielectric layer, and live width is identical with the described first opening live width.First electric conducting material of filling in described first irrigation canals and ditches is exposed in described second irrigation canals and ditches bottom.
In described second irrigation canals and ditches and second opening, fill second electric conducting material (S250).Carry out planarization by cmp then.Described second electric conducting material and first electric conducting material are material of the same race.First electric conducting material in described first irrigation canals and ditches and second electric conducting material in second irrigation canals and ditches form multilayer interconnect structure.
Remove second electric conducting material in described second opening and first electric conducting material in first opening, in described first dielectric layer and second dielectric layer, form groove (S260).The method of removing can be a wet etching.At first above described second dielectric layer, form cover layer, remove the cover layer of described second opening top by chemical wet etching, the upper surface that exposes second electric conducting material in described second opening, remove photoresist then, remove second electric conducting material in described second opening and first electric conducting material in first opening by wet etching, wet etching can select described first and second electric conducting material and first and second dielectric layer are had the etching solution of high selectivity, for example sulfuric acid.
Filled media material in described groove, the dielectric material of filling are silica, and fill up described groove at least, carry out planarization by cmp then.Above described dielectric material, be formed for the lenticule (S270) of receiving optical signals.Described lenticule is positioned at the top of described light-sensitive element, if will make color image sensor, also need form filter earlier on dielectric material before described manufacturing lenticule, and described filter can be the Red Green Blue filter; And then on described filter, form lenticule.Above-mentioned technology has promptly formed a pixel of imageing sensor, and a plurality of cell arrays aid in peripheral control circuit simultaneously and promptly formed imageing sensor, and the size of pixel has determined the resolution of imageing sensor in the cell array.
In making MOS image sensor technology; owing to introduced barrier layer not oxidized and prevention copper diffusion in dielectric layer in the MOS image sensor of copper-connection with the protection metallic copper; and the barrier layer is compared with dielectric layer and is had bigger refractive index and absorption coefficient, and the stack architecture of described barrier layer and dielectric layer has increased the loss of light signal in the communication process of light-sensitive element that lenticule receives.Thereby need remove the dielectric layer of light-sensitive element top and the stack architecture on barrier layer by etching, and fill single dielectric material, so that higher luminous flux can arrive light-sensitive element.The present invention forms opening and fills metallic copper in the laminated dielectric layer above light-sensitive element when forming the multiple layer of copper interconnection, form sacrifice layer, remove sacrifice layer in the opening of dielectric layer of described light-sensitive element top by wet etching then, be scattered in each step copper wiring technique by the technology that etching light-sensitive element top dielectric layer is formed groove, carry out simultaneously with copper wiring technique, not only do not increase extra technology, also reduced the degree of depth of each step etching, reduce the difficulty of etching, more help controlling the profile of the opening that etches; Simultaneously in the opening of each layer dielectric layer, fill metallic copper, and the wet etching by high selectivity removes the copper in the dielectric layer of described light-sensitive element top, not only avoided dry etching ionic medium body bombardment damage to the described semiconductor-based end, the technology of more feasible formation groove becomes and is easy to control, and the groove of formation has good profile.Fill single dielectric material in described groove, the imageing sensor of formation has higher sensitivity.
Below in conjunction with embodiment the technology that the method that forms groove in the laminated dielectric layer is applied to make MOS image sensor is described in detail.In the present embodiment, interconnection structure is three layers.Figure 13 to Figure 27 is the generalized section according to the structure of the manufacturing process corresponding steps of the embodiment of the invention.
As shown in figure 13, provide the semiconductor-based end 200 with metal oxide semiconductor transistor 204 and light-sensitive element 203.Material of the described semiconductor-based ends 200 can be a kind of or its combination in silicon on monocrystalline silicon, polysilicon, amorphous silicon, the insulating barrier, the SiGe composition, and described metal oxide semiconductor transistor 204 has source electrode, grid and drain electrode.Described light-sensitive element 203 can be a photodiode, has the function that light signal is converted to the signal of telecommunication.In the described semiconductor-based end 200, be formed with shallow trench isolation and isolate described metal oxide semiconductor transistor 204 and light-sensitive element 203 with insulation from 202.Form an oxide layer or nitration case 206 on the described semiconductor-based end 200, described oxide layer or nitration case 206 are used to protect the grid and the light-sensitive element 203 of metal oxide semiconductor transistor 204.
As shown in figure 14, form an insulating barrier 208 on described oxide layer or nitration case 206, described insulating barrier can be a silica, and the mode of its formation can be physical vapour deposition (PVD) or chemical vapour deposition (CVD).In described insulating barrier 208, form contact hole (contact) 210 by chemical wet etching, filled conductive material in described contact hole, for example copper, tungsten, titanium, titanium nitride, aluminium, tantalum etc., described contact hole 210 is formed at the top of described metal oxide semiconductor transistor 204, with source electrode, grid or the drain electrode that connects described metal oxide semiconductor transistor 204, contact hole described in the present embodiment 210 is formed at the top of described metal oxide semiconductor transistor 204 grids.When forming connecting hole 210, also can above light-sensitive element, form an opening simultaneously, and in described opening, fill and contact hole 210 in same electric conducting material, the electric conducting material of the opening 210a filling shown in Figure 14 a.Go on to say follow-up technology with structure shown in Figure 14 in the present embodiment.
As shown in figure 15, on described insulating barrier 208, form first dielectric layer 212, described first dielectric layer 212 can be silica, silicon nitride, carborundum, carbon nitrogen silicon compound, carbon oxygen silicon compound, nitrogen-oxygen-silicon compound, fluorine silex glass (FSG), boron-phosphorosilicate glass, Pyrex, black diamond (BlackDiamond, BD) a kind of in, the mode of its formation can be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.
As shown in figure 16, in described first dielectric layer 212, form first irrigation canals and ditches 213 and the first opening 213a by chemical wet etching, the wherein said first opening 213a is positioned at the top of described light-sensitive element 203, the degree of depth of the described first opening 213a is identical with the thickness of described first dielectric layer 212, the area of the area of the described first opening 213a and described light-sensitive element 203 is identical or roughly the same, after guaranteeing forming imageing sensor, there are enough light signals to arrive photodiode and the photosensitive area that makes full use of photodiode, increase sensitivity.
As shown in figure 17, at first at described first irrigation canals and ditches 213 and the first opening 213a sidewall and bottom deposit metal barrier material, for example a kind of or combination in tantalum, tantalum nitride, titanium, the titanium nitride.In described first irrigation canals and ditches 213 and the first opening 213a, fill first electric conducting material then, form first interconnection layer 214 and the first sacrifice layer 214a, described first interconnection layer 214 and the first sacrifice layer 214a material can be a kind of or its combinations in aluminium, copper, gold, silver, tantalum, titanium, the tantalum nitride, the mode of its formation is plating, physical vapour deposition (PVD) or chemical vapour deposition (CVD), by cmp (CMP) planarization, remove the first unnecessary electric conducting material that is formed at described first dielectric layer 212 tops.Described first interconnection layer 214 and the first sacrifice layer 214a carry out simultaneously, do not increase extra technology.The different figures that just increase by the first opening 213a on the mask plate that forms first irrigation canals and ditches 213 make chemical wet etching also form the first opening 213a when forming described first irrigation canals and ditches 213.
As shown in figure 18, above described first dielectric layer 212, form first barrier layer 216.Described first barrier layer 216 materials can be a kind of in silicon nitride, carborundum, the carbon nitrogen silicon compound, and its thickness is 100 to 800 dusts.The mode that forms can be physical vapour deposition (PVD) or chemical vapour deposition (CVD).On described first barrier layer, form second dielectric layer 218.Described second dielectric layer 218 can be a silica.
As shown in figure 19, in described second dielectric layer 218, form second irrigation canals and ditches 219,221 and the second opening 219a by chemical wet etching.The described second opening 219a is positioned at described first opening 213a top, and the described second opening 219a degree of depth is identical with the thickness of described second dielectric layer 218, and its width is identical with the width of the described first opening 214a.Remove first barrier layer 216 of described second irrigation canals and ditches 221 and second opening 219a bottom by further etching, make second opening 219a bottom expose the described first sacrifice layer 214a, described first interconnection layer 214 is exposed in second irrigation canals and ditches, 221 bottoms.Described second irrigation canals and ditches 219 and 221 formation generally need two step chemical wet etching technologies, and promptly the formation technology of groove in the dual-damascene structure and connecting hole repeats no more here.With forming the second opening 219a that described second irrigation canals and ditches 219 and 221 carry out synchronously is two step chemical wet etching technologies and forming too.
As shown in figure 20, fill second electric conducting material in described second irrigation canals and ditches 219,221 and the second opening 219a, form second interconnection layer 220 and the second sacrifice layer 220a, described line 222 is the lead that is connected of first interconnection layer 214 and second interconnection layer 220.The described second sacrifice layer 220a be positioned at the described first sacrifice layer 214a directly over, and contact fully with the upper surface of the described first sacrifice layer 214a, become one.The material of second interconnection layer 220, the second sacrifice layer 220a and line 222 is a metallic copper described in the present embodiment.
As shown in figure 21, on described second dielectric layer 218, form second barrier layer 224 and the 3rd dielectric layer 226.Described second barrier layer 224 is a kind of in silicon nitride, carborundum, the carbon nitrogen silicon compound.Described the 3rd dielectric layer 226 is a silica.As shown in figure 22, use the same method and form the 3rd interconnection layer 230 and the 3rd sacrifice layer 230a, described line 228 connects described the 3rd interconnection layer 230 and second interconnection layer 220, and described the 3rd sacrifice layer 230a and the described second sacrifice layer 220a, the first sacrifice layer 214a are connected as a single entity.The material of the 3rd interconnection layer 230, the 3rd sacrifice layer 230a and line 228 is a copper described in the present embodiment.
As shown in figure 23, on described the 3rd dielectric layer 231, form the 3rd barrier layer 231 and cover layer 232.Described the 3rd barrier layer 231 is a kind of in silicon nitride, carborundum, the carbon nitrogen silicon compound.Described cover layer 232 is silica and nitrogen-oxygen-silicon combination of compounds.
As shown in figure 24, spin coating photoresist on described cover layer 232, and remove the photoresist of described the 3rd sacrifice layer 230a top by exposure imaging, remove the described cover layer 232 that is not covered by etching by photoresist, form the 3rd opening 234, the 3rd barrier layer by described the 3rd opening of etching 234 bottoms makes described the 3rd opening 234 bottoms expose the upper surface of described the 3rd sacrifice layer 230a, removes described photoresist.
As shown in figure 25, remove described the 3rd sacrifice layer 230a, second by wet etching and sacrifice the 220a and the first sacrifice 214a, form groove 234a.The upper surface of described insulating barrier 208 is exposed in the bottom of described groove 234a.If adopt the structure shown in Figure 14 a, then form the surface that described silica or silicon nitride 206 are exposed in its bottom behind the groove 234a, further need make the upper surface of light-sensitive element 203 expose by etching.
As shown in figure 26, filled media material 234b in described groove 234a.The thickness of filling fills up described groove 234a at least, and removes the unnecessary dielectric material in described cover layer 232 tops by cmp.
As shown in figure 27, on described dielectric material 234b, form filter 237, protective layer 236, above described protective layer 236, form lenticule 238 with described filter 237 corresponding positions.Described filter can be the Red Green Blue filter.Above-mentioned technology has promptly formed a pixel of imageing sensor, and a plurality of cell arrays aid in peripheral control circuit simultaneously and promptly formed imageing sensor, and the size of cell array pixel has determined the resolution of imageing sensor.
In the manufacturing process of above-mentioned MOS image sensor, the present invention forms opening and fills metallic copper in the laminated dielectric layer above light-sensitive element when forming the multiple layer of copper interconnection, form a plurality of sacrifice layers, remove a plurality of sacrifice layers in the laminated dielectric layer of described light-sensitive element top with wet etching then, be scattered in each step copper wiring technique by the technology that etching light-sensitive element top laminated dielectric layer is formed opening, carry out simultaneously with copper wiring technique, not only do not increase extra technology, also reduced the degree of depth of each step etching, reduce the difficulty of etching, more help controlling the profile of the opening that etches; Fill metallic copper in the opening in each layer dielectric layer simultaneously, and the wet etching by high selectivity removes the copper in the opening of described light-sensitive element top dielectric layer, not only avoided dry etching ionic medium body bombardment damage to the described semiconductor-based end, the technology of more feasible formation groove becomes and is easy to control, and the groove of formation has good profile.Fill single dielectric material in described groove, the imageing sensor of formation has higher sensitivity.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1. method that forms groove in laminated dielectric layer comprises:
In the semiconductor substrate, form first dielectric layer;
In described first dielectric layer, form first opening;
In described first opening, fill first sacrifice layer;
At least form one second dielectric layer on described first dielectric layer, and form second opening in described second dielectric layer, described second opening is positioned at described first opening top, and the degree of depth of described second opening is identical with the thickness of described second dielectric layer;
In described second opening, fill second sacrifice layer;
Remove described first sacrifice layer and second sacrifice layer.
2. the method that forms groove in laminated dielectric layer as claimed in claim 1, it is characterized in that: described first opening is identical with the live width of second opening.
3. the method that forms groove in laminated dielectric layer as claimed in claim 1 is characterized in that: remove described first sacrifice layer and second sacrifice layer with wet etching.
4. the method that forms groove in laminated dielectric layer as claimed in claim 1, it is characterized in that: described first sacrifice layer and second sacrifice layer are material of the same race.
5. the method that forms groove in laminated dielectric layer as claimed in claim 4, it is characterized in that: described first sacrifice layer and second sacrifice layer are a kind of or its combination in copper, aluminium, gold, silver, tantalum, titanium, tantalum nitride, titanium nitride, anti-reflecting layer, the photoresist.
6. the method that forms groove in laminated dielectric layer as claimed in claim 1, it is characterized in that: described first dielectric layer and second dielectric layer are a kind of or its combinations in silica, silicon nitride, carborundum, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, carbon nitrogen silicon compound, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, the black diamond.
7. the method for an application rights requirement 1 is made the method for MOS image sensor, comprising:
The semiconductor substrate is provided, in the described semiconductor-based end, is formed with light-sensitive element;
On the described semiconductor-based end, form first dielectric layer;
Form first irrigation canals and ditches and first opening in described first dielectric layer, wherein said first opening is positioned at described light-sensitive element top, and the degree of depth of this first opening is identical with the thickness of described first dielectric layer;
In described first irrigation canals and ditches and first opening, fill first electric conducting material;
On described first dielectric layer, form one second dielectric layer at least, and in described second dielectric layer, form second irrigation canals and ditches and second opening, wherein said second opening is positioned at the top of described first opening, and the degree of depth of this second opening is identical with the thickness of described second dielectric layer;
In described second irrigation canals and ditches and second opening, fill second electric conducting material;
Remove second electric conducting material in described second opening and first electric conducting material in first opening, in described first dielectric layer and second dielectric layer, form groove;
Filled media material in described groove;
Above described dielectric material, be formed for accepting the lenticule of light signal.
8. method as claimed in claim 7 is characterized in that: described first opening is identical with the live width of second opening.
9. method as claimed in claim 8 is characterized in that: the live width of described first opening and second opening is identical with the live width of described light-sensitive element.
10. method as claimed in claim 7 is characterized in that: described first electric conducting material and second electric conducting material are material of the same race.
11. method as claimed in claim 10, its feature in: described first electric conducting material and second electric conducting material are a kind of or its combination in aluminium, copper, gold, silver, tantalum, titanium, the tantalum nitride.
12. method as claimed in claim 7 is characterized in that: remove second electric conducting material in described second opening and first electric conducting material in first opening, the step that forms groove in described first dielectric layer and second dielectric layer comprises:
On described second dielectric layer, form cover layer;
Remove the cover layer of described second electric conducting material top by chemical wet etching;
With described cover layer is hard mask, removes second electric conducting material in described second opening and first electric conducting material in first opening by wet etching.
13. method as claimed in claim 7 is characterized in that, this method further comprises: carry out planarization by cmp behind the filled media material.
14. method as claimed in claim 7 is characterized in that, this method further comprises: form a filter before forming lenticule above described dielectric material.
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| CNB200610118301XA CN100517634C (en) | 2006-11-13 | 2006-11-13 | Method for manufacturing groove and its method for manufacturing image sensor |
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| CNB200610118301XA CN100517634C (en) | 2006-11-13 | 2006-11-13 | Method for manufacturing groove and its method for manufacturing image sensor |
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| CN101183658A true CN101183658A (en) | 2008-05-21 |
| CN100517634C CN100517634C (en) | 2009-07-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101908550A (en) * | 2009-06-04 | 2010-12-08 | 索尼公司 | Solid-state image pickup element, its manufacture method and the electronic equipment that uses it |
| CN102530831A (en) * | 2010-12-27 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| CN102789985A (en) * | 2011-05-20 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof |
| CN106158890A (en) * | 2015-04-09 | 2016-11-23 | 力晶科技股份有限公司 | Image sensor |
| CN109037197A (en) * | 2018-08-03 | 2018-12-18 | 德淮半导体有限公司 | Semiconductor device and its manufacturing method |
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| CN101908550A (en) * | 2009-06-04 | 2010-12-08 | 索尼公司 | Solid-state image pickup element, its manufacture method and the electronic equipment that uses it |
| CN102530831A (en) * | 2010-12-27 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| CN102530831B (en) * | 2010-12-27 | 2014-05-21 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| US8877537B2 (en) | 2010-12-27 | 2014-11-04 | Lexvu Opto Microelectronics Technology (Shanghai) Ltd | Method for manufacturing MEMS device |
| CN102789985A (en) * | 2011-05-20 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof |
| US8877577B2 (en) | 2011-05-20 | 2014-11-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and manufacturing method thereof |
| CN102789985B (en) * | 2011-05-20 | 2015-04-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof |
| CN106158890A (en) * | 2015-04-09 | 2016-11-23 | 力晶科技股份有限公司 | Image sensor |
| CN106158890B (en) * | 2015-04-09 | 2019-07-09 | 力晶科技股份有限公司 | Image sensor |
| CN109037197A (en) * | 2018-08-03 | 2018-12-18 | 德淮半导体有限公司 | Semiconductor device and its manufacturing method |
| CN114772592A (en) * | 2022-06-21 | 2022-07-22 | 成都沃特塞恩电子技术有限公司 | Diamond cultivation equipment adjusting method and device, electronic equipment and storage medium |
| CN114772592B (en) * | 2022-06-21 | 2022-09-16 | 成都沃特塞恩电子技术有限公司 | Diamond cultivation equipment adjusting method and device, electronic equipment and storage medium |
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| CN100517634C (en) | 2009-07-22 |
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