CN101179305B - System and method for electronic dispersion compensation - Google Patents

System and method for electronic dispersion compensation Download PDF

Info

Publication number
CN101179305B
CN101179305B CN2007101482317A CN200710148231A CN101179305B CN 101179305 B CN101179305 B CN 101179305B CN 2007101482317 A CN2007101482317 A CN 2007101482317A CN 200710148231 A CN200710148231 A CN 200710148231A CN 101179305 B CN101179305 B CN 101179305B
Authority
CN
China
Prior art keywords
signal
module
channel
alternating expression
adc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101482317A
Other languages
Chinese (zh)
Other versions
CN101179305A (en
Inventor
维韦克·特兰
瓦苏德万·帕萨瑟拉思
苏迪普·布霍贾
陈宏�
阿弗希·莫太茨
陈春来
阿里·吉亚斯
迈克尔·弗唐
洛伦佐·隆哥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Zyray Wireless Inc
Original Assignee
Zyray Wireless Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/837,278 external-priority patent/US7961781B2/en
Application filed by Zyray Wireless Inc filed Critical Zyray Wireless Inc
Publication of CN101179305A publication Critical patent/CN101179305A/en
Application granted granted Critical
Publication of CN101179305B publication Critical patent/CN101179305B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The present invention relates to a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. The system uses an interleaved analog to digital converter block, wherein the interleaved analog to digital converter block generates a plurality of digitally sampled signals according to the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the analog to digital converter block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Description

System and method to electronic dispersion compensation
Technical field
The present invention relates to digital integrated circuit and signal processing, more particularly, relate to and carry out electronic dispersion compensation (dispersion compensation), adopt the alternating expression framework, and utilize channel identification information to carry out regularly and recover.
Background technology
Radio communications system includes transmitter, is used for information to be launched is encoded to electromagnetic wave; Transmission medium is for electromagnetic transmission provides channel; And receiver, be used to receive and handle the electromagnetic wave of beared information.Radio communications system can utilize waveguide (waveguide) as transmission medium.Waveguide is the structure of the propagation of a kind of guiding or constraint electromagnetic radiation.Waveguide can comprise material boundary (material boundary) system of solid dielectric form.In radio communications system, optical fiber is usually as waveguide.
Owing to multiple reason, people wish to increase the bandwidth or the transmission rate of radio communications system.At first, need bigger bandwidth to support present radio communication equipment, for example,, perhaps be used for the equipment of live video and audio frequency at those equipment that data center uses, and other super bandwidth equipment.Secondly, for the reason of efficient and cost, need to increase the bandwidth of radio communications system.Therefore, the physical condition restriction of solution waveguide is very important concerning transmission high bandwidth electromagnetic signal.
Chromatic dispersion is that the restricted passage communication channel succeeds in sending up the important physical phenomena with the electromagnetic ability of recovering bearing information.The phase velocity of any spectral components all can depend on the refraction coefficient of physical media in the transmission medium.Usually, the refraction coefficient of transmission medium depends on frequency.When the velocity of wave in the waveguide of optical fiber and so on depended on its frequency, waveguide dispersion will take place.The transverse mode (transverse mode) of the ripple that is limited by waveguide has the friction speed that depends on frequency usually.Similar phenomenon has because of have the caused modal dispersion of waveguide (modal dispersion) of a plurality of patterns in given frequency, and each pattern of this waveguide is propagated with different speed.
Waveguide dispersion causes the signal attenuation in the radio communications system, has significantly reduced pulse characteristics by the pulse of waveguide emission because change the delay in the time of advent between the different components of signal.This phenomenon is commonly called intersymbol interference (ISI).The adjacent-symbol that is expressed as pulse is " infiltration " significantly each other, constantly may have energy at the specific assignment sampling of a symbol, and this symbol is actual to include the energy relevant with adjacent-symbol.
Therefore, necessary correction error source, the chromatic dispersion and relevant ISI introduced in the signal that passes through the communication channel emission that for example receives.Usually, receiver can be equipped with signal processing system, the dispersive influence of coming the correction communication channel to introduce.The frequent analyzing communication channel statistic property of these signal processing systems is to eliminate ISI.Signal processing system utilizes one or more equalizer to carry out these corrections usually.A kind of equalizer commonly used is feed forward equalizer (FFE), reaches (pre-cursor) ISI (wherein current sign is subjected to the influence of next symbol) before being used for proofreading and correct.Common and DFF (DFE) combination of FFE, DFF reaches (post-cursor) ISI (wherein current sign is subjected to the influence of previous symbol) after being used for proofreading and correct.
The multiple technologies challenge may occur in the process of structure signal processing system with correction chromatic dispersion and ISI, in the communication system of using high bit rate or symbol rate, it is particularly arduous that these challenges become.At first, need in numeric field, carry out signal processing operations, because it is usually than the higher SNR of the easier realization of equal analogue system.Secondly, digital system has in signal layout and the lower advantage of design aspect complexity, and the chance that can be easy to revise employed signal handler is provided.
Digital information processing system must be digital signal with the analog signal conversion that is received.Generally speaking, making a series of ADC is very difficult and expensive with the baud rate work that surpasses 1.5-2GHz.This is problematic, because often need be configured in the communication system of working about 10GHz at least.Also there is similar problem in equalizer for designing and be configured in High Data Rate work.
Second technical problem is relevant with the time-varying characteristics of communication channel, and this performance to the timing recovery operation of receiver exerts an influence.Transmitter has generally included clock, is used for data-signal is encoded to carrier signal, to pass through Channel Transmission.Transmitter clock will be determined the speed by the traffic channel symbol.
Receiver also needs clock usually, and its phase place preferably locks with transmitter clock, to recover the symbol of transmitter by the communication channel emission exactly.But the transmitter and receiver clock can relative to each other drift about usually, and this causes frequency shift (FS) between the two.Phase place is the part of frequency, so the phase place between the transmitter and receiver clock can be offset.Therefore, the receiver in the communication system has generally included timing recovery circuit, is used to make transmitter clock and receiver clock synchronous.
Digital communication system can be used the method that is called as baud rate or symbol rate sampling, wherein with the signal sampling of baud rate to being received.Owing to needn't in communication system, recover whole analog signals, therefore needn't sample at Nyquist rate (Nyquist rate).But, in receiver, carry out the accuracy that regularly recovery operation makes receiver sample to effective stabilization signal thereby the baud rate sampling has significantly retrained.
As mentioned above, communication system needs physical media to come transmit communications signals.The characteristic of the physical media in the communication system often changes in time.Compare with baud rate, common this time dependence is positioned on the relatively long markers (time scale).When communication channel is approached by its first rank activity, more the effect of high-order is very little, channel characteristics does not change in time and initial conditions is under the known situation, channel can be characterized by impulse response or Green's function (Green ' s function) the influence of the signal of emission, and it has described the response of channel pulse signals.In utilizing the conventional timing recovery system of conventional algorithm, the time-varying characteristics of channel characteristics fail to solve, thereby this has reduced signal processing system and carries out the ability that the ISI influence of not expecting is eliminated in baud rate sampling accurately effectively.
Summary of the invention
According to a total aspect of the present invention, the invention provides a kind of system to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is with the symbol rate beared information.Can use alternating expression analog to digital converter (ADC) module, this alternating expression ADC module is arranged to according to described electromagnetic signal and generates a plurality of digital sampled signal.The alternating expression equalizer module can be arranged to each digital sampled signal that the ADC module is generated and carry out digital processing, to generate a plurality of digital equalising signals.Multiplexer can be arranged to the digital equalising signal gathering is become composite output signal.
According to another total aspect, the invention provides a kind of method to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is with the symbol rate beared information, described method comprises the electromagnetic signal of reception with the symbol rate beared information, upgrade the expectation sampling phase of alternating expression analog to digital converter (ADC), described electromagnetic signal is carried out variable gain amplifies, described electromagnetic signal is carried out the alternating expression analog-to-digital conversion to generate a plurality of staggered digital signals, in described a plurality of staggered digital signals each is carried out equilibrium treatment generating a plurality of decision signals, and described a plurality of decision signals are merged with the generation composite data signal.
According to another total aspect, the invention provides a kind of to carrying out the method for regularly recovering with the signals sampling of intrinsic symbol rate emission by communication channel, comprise: calculate a plurality of channel impulse response estimation signals, each in described a plurality of channel impulse response estimation signals all has specific phase place; From described a plurality of estimation channel response signals, periodically determine best estimate channel response signal, wherein said best estimate channel response signal description be best suited for regularly the impulse response of the communication channel of recovery algorithms; And based on described best estimate channel response Signal Regulation timing recovery algorithms.
According to an aspect of the present invention, the invention provides a kind of system to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is with the symbol rate beared information, and described system comprises:
Alternating expression analog to digital converter (ADC) module, described alternating expression ADC module is used for generating a plurality of digital sampled signal according to described electromagnetic signal;
Alternating expression equalizer module, described alternating expression equalizer module are used for each digital sampled signal that the ADC module generates is carried out digital processing, to generate a plurality of digital equalising signals; And
Multiplexer, described multiplexer are used for the digital equalising signal gathering is become composite output signal.
Preferably, described system also comprises regularly recovers module, and described timing recovers the sampling phase that module is used for determining expectation, and the sampling phase of described expectation is offered the ADC module.
Preferably, described system also comprises channel identification module, and described channel identification module is used for determining the feature of communication channel, and the feature of described communication channel offered regularly recovers module.
Preferably, described timing recovers the algorithm that module also utilizes channel characteristics information to regulate to be used for the sampling phase of determining expectation.
Preferably, described channel identification module is also determined the sampling phase of expectation, and the sampling phase of described expectation is offered described timing recovery module.
Preferably, described channel characteristics comprises channel impulse response, and described channel identification module also is used for:
Reception is from the output of described equalizer module;
Second digital sampled signal that reception generates according to described electromagnetic signal; And
According to the output and described second digital sampled signal of described equalizer module, upgrade at least one coefficient of described channel impulse response.
Preferably, be associated with described second digital sampled signal by the output that makes equalizer module, upgrade at least one coefficient of described channel impulse response, the output of wherein said equalizer module and described channel impulse response be convolution mutually.
Preferably, described alternating expression ADC module is sampled to described electromagnetic signal with described symbol rate.
According to an aspect of the present invention, the invention provides a kind of method to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is with the symbol rate beared information, and described method comprises:
Reception is with the electromagnetic signal of symbol rate beared information;
Upgrade the expectation sampling phase of alternating expression analog to digital converter (ADC);
Electromagnetic signal is carried out variable gain amplifies;
Electromagnetic signal is carried out the alternating expression analog-to-digital conversion to generate a plurality of staggered digital signals;
In a plurality of staggered digital signals each is carried out equilibrium treatment to generate a plurality of decision signals; And
Described a plurality of decision signals are merged to generate composite data signal.
Preferably, described analog-to-digital conversion is carried out with described symbol rate.
Preferably, use from the derive sampling phase of the described expectation of algorithm computation that obtains of Mueller-Muller (Miu Le-bridle) algorithm.
Preferably, by determining that channel characteristics calculates the sampling phase of described expectation.
Preferably, described channel characteristics is a channel impulse response.
Preferably, by selecting one the one group of channel impulse response estimation signal that all has particular phases from each, come the sampling phase of calculation expectation.
Preferably, selected channel impulse response signal minimizes with the digital sample form of electromagnetic signal and by the correlation between the decision signal of selected channel impulse response filtering.
Preferably, described channel impulse response is used to select the specific change form of Mueller-Muller algorithm, recovers to carry out regularly.
Preferably, described symbol rate is 10GHz at least.
According to an aspect of the present invention, the invention provides a kind of method that the signals sampling execution of launching with intrinsic symbol rate by communication channel is regularly recovered, comprising:
Calculate a plurality of channel impulse response estimation signals, each in described a plurality of channel impulse response estimation signals all has specific phase place;
Judge best estimate channel response signal according to described a plurality of estimation channel response signal periods property ground, wherein said best estimate channel response signal description be best suited for the regularly impulse response of the communication channel of recovery algorithms; And
Based on described best estimate channel response Signal Regulation timing recovery algorithms.
Preferably, by the error letter being minimized determine that described best estimate channel impulse response, wherein said error signal are by calculating and being obtained by the difference between the relevant signal of the decision signal of each channel impulse response estimation signal filtering.
Preferably, regulate described timing recovery algorithms and comprise that phase place with the described optimum channel impulse response of correspondence is to signal sampling.
One or more embodiments of the detail are partly providing description below in conjunction with the drawings and specific embodiments.According to the description in embodiment, accompanying drawing and the claim, further feature of the present invention is conspicuous.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the block diagram of radio communications system;
Fig. 2 a-2c is a sequential chart, shows the effect of dispersion by the electromagnetic signal of traffic channel;
Fig. 3 a is the block diagram of signal processing system, and described signal processing system is used for the distorted signals of the receiver received signal of correction communication system;
Fig. 3 b is the detailed maps of signal processing system;
Fig. 4 is the schematic diagram that flows through the signal flow of signal processing system, and described signal processing system is used for the distorted signals that the correction communication channel is introduced;
Fig. 5 a is the work schematic diagram according to the alternating expression ADC of an embodiment;
Fig. 5 b is the more detailed schematic diagram according to the ADC framework of an embodiment;
Fig. 5 c is the overall work schematic diagram according to the alternating expression ADC of an embodiment;
Fig. 6 a is the schematic diagram of the signal path of alternating expression FFE;
Fig. 6 b is the schematic diagram according to the serial D FE unit of an embodiment;
Fig. 7 a is the work schematic diagram according to the channel identification filtering update module of an embodiment;
Fig. 7 b determines the work schematic diagram of channel characteristics information with the auxiliary timing recovery operation according to the channel identification module of an embodiment;
Fig. 7 c is the work schematic diagram according to the optimum phase computing module of an embodiment;
Fig. 8 is the work schematic diagram of baud rate phase detectors;
Fig. 9 is the workflow diagram according to the signal processing system of an embodiment;
Figure 10 is the workflow diagram performed according to the signal processing system of an embodiment;
Figure 11 is the workflow diagram of the starting state machine (start-up state machine) of an embodiment.
Embodiment
Fig. 1 is the block diagram of radio communications system.Communication system 100 comprises the website of any amount, and communication channel 182 that can be by any amount is interactive information therein.Fig. 1 shows two websites 102 (1), 102 (2), and one of them comprises transmitter 108, and as the emission website, another comprises receiver 116 and is used as receiving station.This only is exemplary, is appreciated that this communication system can comprise the website 102 of any amount, and wherein each can provide independent emissivities, independent receiving ability or transmit and receive the combination of ability.
Websites 102 (1), 102 (2) in the radio communications system 100 can be data centers for example.Perhaps, each website 102 can be the special construction in the data center, for example data archival system or mass-memory unit (for example, disk memory array), server or other front end system.In data-center applications, be very important with High Data Rate access and transmission mass data.
Each emission website 102 (1) comprises data source 104, and data source 104 can be to be used for filing or to generate any system of the data that are about to send to receiving station 102 (2).Information transmitted can comprise the data of any kind between emission website 102 (1) and receiving station 102 (2), for example comprises multimedia messages, the text message of Voice ﹠ Video information, can be with any suitable form storage.But data source 104 archive data, described data are used for being transmitted into receiving station 102 (2) from emission website 102 (1).Perhaps, data source 104 can provide in real time or near real-time data is used for transmission.For example, data source 104 can be a multimedia equipment, for example video camera or microphone, and they generate video and audio signal respectively.Perhaps, data source 104 can be the multimedia file that files, for example mpeg file.Data source 104 can comprise the analog-and digital-information of any combination.Data source 104 can comprise the data with any form storage, comprises the data of initial data or compression.
Emission website 102 (1) can be transmitted into receiving station 102 (2) with information from data source 101 by the communication channel 182 of using electromagnetic signal.Can utilize optical wavelength or other necessary wavelength to realize the symbol rate of expecting by the electromagnetic signal of communication channel 182 emissions.Therefore, communication channel 182 can be a fibre optics cable or be suitable for other physical media of optical wavelength transmission electromagnetic signal for example.According to an embodiment, communication channel 182 can be the multi-mode fibre optics cable, can realize the bit rate of 10 gigabit/sec (gbps) by it between emission website 102 (1) and receiving station 102 (2).In example embodiment more specifically, bit rate is 10.3125gbps.
Emission website 102 also can comprise transmitter 108.Transmitter 108 further comprises light emission secondary module (transmitter optical sub assembly is called for short TOSA) 106, and TOSA 106 provides to the interface of optical physics layer (for example, optical communication channel).TOSA 106 can comprise laser (laser, not shown).Especially, but TOSA 106 modulated lasers use the information that data source 104 provides and the electromagnetic carrier wave signal that generates, and this modulation signal is offered communication channel 182.Because emission website 102 (1) and receiving station 102 (2) commutative digital informations, TOSA 106 can carry out the digital modulation of optical carrier.Therefore, TOSA 106 can provide a large amount of electromagnetic signals, to transmit the data that described electromagnetic signal corresponding data source 104 provides by communication channel 180.
Carry out under the situation of digital communication between emission website 102 (1) and receiving station 102 (2), data source 107 can provide a plurality of numerals, and these numerals are about to the information of emission between emission website 102 (1) and receiving station 102 (2).These numerals can be that radix representation is bit stream (0 or 1) with binary system or with 2.For each bit that is about to be launched, transmitter 108 can generate the first pulse electromagnetic signal and represent numeral 1, generates the second pulse electromagnetic signal and represents numeral 0.
Transmitter 108 also can be equipped with transmit clock 110, and transmit clock 110 controls transmitter 108 symbol rates by communication channel 182 emission information.According to an embodiment, transmit clock 110 can be worked with 10Gbps.
Receiving station 102 (2) comprises the network equipment 112 that is connected to communication channel 182, and it provides and has been used for receiving and handling by the system of emission website 102 (1) by the signal of communication channel 182 emissions.Especially, the network equipment 112 can comprise receiver 116, and receiver 116 comprises various functional modules, is used for receiving and handling by the signal of emission website 102 (1) by communication channel 182 emissions.
Receiver 116 can include light-receiving secondary module (receiver optical sub assembly is called for short ROSA).This ROSA comprises photodiode (not shown), and this photodiode is converted to the signal of telecommunication with light signal.Especially, photoelectric diode can be converted to electric current with light signal.Transimpedance amplifier among the ROSA (transimpedance amplifier) (not shown) can be a voltage with current conversion further, and voltage can be further processed.Receiver 116 can include receiver clock 142, receiver clock 142 be designed to transmitter clock 110 with identical frequency work.But receiver clock 142 can (just, will not have drift or phase deviation) fully synchronously with transmitter clock 110 usually, and this must be proofreaied and correct by receiver.For the drift between correct transmission machine clock 110 and the receiver clock 142, receiver 116 is provided with and regularly recovers module 134.
Receiver 116 can comprise that also variable gain amplifier (VGA), analog to digital converter (ADC) 120, equalizer module 132, channel identification module 124, timing recover module 134, state machine 126 and microcontroller 138.Whole operations of receiver 116 are by microcontroller 138 control, mutual between the various functional modules on the microcontroller 138 tunable receivers 116.The startup of state machine 126 receiver control and converge action.Other embodiment of EDC system 410 comprises the operation of above-mentioned each parts, will provide detailed introduction at further part.
Fig. 2 a-2c shows the effect of dispersion by the electromagnetic signal of the traffic channel on the physical media, and described physical media is a multi-mode fibre optics cable for example.Fig. 2 a shows and comprises a plurality of pulses 206 (1)--206 (6) idealized pulse train.Each pulse is all sorted to being characterized as frequency and phase place
Figure G071E8231720070911D000091
Transmitter clock signal 202.Shown in Fig. 2 a, each pulse is all corresponding to a+1 or a-1, and this depends on that pulse is just or negative.Therefore, pulse 206 (1), 206 (3) and 206 (5) corresponding a+1, and pulse 206 (2), 206 (4) and 206 (6) corresponding a-1.+ 1/-1 pulse can be converted into 0 or 1 respectively at the receiver place.
Under the ideal case shown in Fig. 2 a, on frequency and phase place, follow the receiver clock (not shown among Fig. 2 a-2c) of transmitter clock signal 202 fully and can in receiver, realize.In addition, under this ideal case, the pulse train 210 that generates at the transmitter place can be transmitted to receiver, and without any distorted signals or decline.Receiver can utilize 208 pairs of signals sampling that receive from transmitter of receiver clock signal to carry out timing.Especially, receiver can be carried out the baud rate sampling to received signal, to recover the bit at transmitter place coding.
But these ideal states are actual to be inaccessiable.Fig. 2 b shows contingent certain undesirable situation in the process that electromagnetic signal is transmitted between transmitter and receiver.Especially, Fig. 2 b shows and is characterized as frequency and phase place
Figure G071E8231720070911D000092
Receiver clock signal 208.Receiver clock signal 208 can have phase deviation and frequency shift (FS) with respect to transmitter clock signal 210.The generation of this frequency and dependent phase skew can be rooted in the drift between these two clocks.
Second kind of situation of restriction digital communication system work is undesirable relevant with transmission medium itself, comprises effect of dispersion and relevant intersymbol interference.Fig. 2 b also shows the pulse characteristics of receiver by a plurality of pulses of the communication channel emission of fibre optics cable and so on.Especially, the pulse 204 (1)-204 (6) that is received corresponds respectively to the pulse 206 (1)-206 (6) of being launched.Because the feature of communication channel, each pulse of launching 206 (1)-206 (6) all suffers chromatic dispersion.Especially, the refractive index of communication channel and frequency dependence, this causes the different frequency component of each pulse to be propagated with different speed.In communication channel 182 is that chromatic dispersion may take place in the pulse of being launched under the situation of multi-mode optical fiber.Shown in Fig. 2 b, the pulse 204 (1)-204 (6) that is received is scattered on time orientation or hangover is arranged.
Fig. 2 c shows the composite signal of the linear superposition of pulse 204 (1)-204 (6).This composite signal can be represented the practical communication signal that receiver receives.The feature transmission signals of the pulse train of being launched 210 is received by receiver.Because this linear superposition, each independent pulse signal (for example, 206 (1)-206 (6)) all can distortion.This phenomenon is commonly called intersymbol interference (ISI).The signal of launching in order to recover and/or carry out the sampling of effective baud rate must significantly reduce the ISI that communication channel is introduced.
Fig. 3 a is the block diagram of a signal processing system, and described signal processing system is used for the distorted signals of the receiver received signal of correction communication system, for example waveguide dispersion and relevant ISI.At transmitter 108 places production burst signal 206, with digital coding, this baud rate is the function of the transmitter clock 110 that generates transmitter clock signal 202 with baud rate for transmitter 108.This pulse signal offers communication channel by the TOSA 106 at transmitter 108 places.Communication channel can use the multi-mode fibre optics cable to implement.
Transmitter 108 can generate information carrying signal 396, and information carrying signal 396 comprises a plurality of pulses synchronous with transmitter clock 110, and transmitter clock 110 generates transmitter clock signals 202.Transmitter clock signal 202 definable bit rate or symbol rates, bit rate or symbol rate have defined the quantity that unlike signal that per second offers communication channel 182 changes.Transmitter clock can be with any baud rate coded data.For example, according to an embodiment, baud rate is 10Gbps.
The TOSA at transmitter 108 places can cause that communication channel 182 can be a multi-mode fibre optics cable communication channel by communication channel 182 transmission information carrying signals 396.Because the channel characteristics of communication channel 182, information carrying signal 396 may experience various conversion and/or distortion.These distortions are obviously different with the information carrying signal 396 that transmitter 108 places generate with the signal 304 that conversion can cause ROSA 107 places to receive.These distortions comprise ISI and chromatic dispersion.Channel characteristics is the impulse response of communication channel 182.These distortions can cause being difficult to initial information encoded in the recovering information carrying signal 396.
The signal 304 that is received can offer signal processing system 140, with the distorted signals of compensation communication channel 182 introducings.Especially, signal processing system 140 can be carried out Signal Regulation to the signal that is received, with the distorted signals of correction communication channel 182 introducings.Usually, signal processing system 140 can be carried out the processing in analog-and digital-territory to the signal 304 that is received.Handle for combine digital, signal processing system 140 can be carried out analog-to-digital conversion to the signal that obtains from received signal 304.
Because information carrying signal 396 can be with high bit rate coded data, signal processing system 140 can include the one or more alternating expression structures that work independently with the clock rate that is lower than this baud rate.This helps carrying out in numeric field handles.Therefore, shown in Fig. 3 a, signal processing system 140 can comprise alternating expression ADC module 118 and alternating expression equalizer module 132.As will be described in more detail, alternating expression ADC module 118 can comprise a plurality of ADC, and each is all to be lower than the clock rate work of this baud rate.Similarly, alternating expression equalizer module 132 comprises a plurality of equaliser structures, and each is all to be lower than the clock rate work of this baud rate.Alternating expression ADC module 118 can be relative to each other with identical clock rate or different clock rate operations with alternating expression equalizer module 132.
Alternating expression ADC module 118 can be utilized the baud rate sampling, and the feasible work in combination of a plurality of ADC of alternating expression ADC module 118 that comprises can be carried out efficiently sampling to received signal 396 with this baud rate.Receiver can comprise the receiver clock 142 that generates receiver clock signal 208.Ideally, receiver clock 142 can accurately lock on frequency with transmitter clock 110, received signal 396 is accurately sampled in this baud rate with permission.But in fact receiver module 142 can drift about on frequency with respect to transmitter module 110 usually, and this causes the phase deviation between transmitter module 110 and the receiver module 142.In order to compensate this frequency drift, signal processing system 140 can comprise baud rate phase detectors 198.Baud rate phase detectors 198 can be worked to recover the timing information relevant with received signal 396.Effective, the stable symbol situation of the situation that this timing information can be used for forcing making each sampling instant (this moment, alternating expression ADC sampled to received signal 396) when encoding at transmitter 108 places.The timing recovery operation that baud rate phase detectors 198 are carried out helps alternating expression ADC module 118 and uses the baud rate sampling, and assists in ensuring that the sample that obtains in this baud rate is corresponding with valid symbol.According to an embodiment, baud rate phase detectors 198 can utilize the algorithm of deriving and obtaining from the Mueller-Muller algorithm.Alternating expression ADC module 118 can utilize receiver clock signal 208 to trigger sampling operation.
As mentioned above, baud rate phase detectors 198 can be carried out various Mueller-Muller algorithms, to carry out regularly recovery operation.In order to carry out this algorithm, the baud rate phase detectors can suppose that communication channel 182 has specific channel characteristics, and this channel characteristics can be expressed as the impulse response of communication channel 182.But because the physical condition of change, the channel characteristics of communication channel 182 changes in fact in time.Usually, the time-varying rate of channel characteristics is considerably slower than baud rate.For example, in multi-mode optical fiber, because the physical motion or the vibration (with respect to baud rate, rare) of optical fiber become when channel characteristics may take place.
In order to solve the time-varying characteristics of channel characteristics, covert bit detector (TVPD) 196 when signal processing system 140 can comprise.The channel characteristics of flexible letter channel 182 when TVPD 196 can periodically determine.This channel characteristics can be the estimating impulse response of communication channel 182.As described below, the interlock circuit in TVPD 196 or the CID module 102 can be at the estimating impulse response of each the calculating communication channel 182 in a plurality of sampling phases.These a plurality of sampling phases can be used to provide the estimated value of comparing the impulse response of excessively being sampled with baud rate.But the interlock circuit usage degree gage (metric) in TVPD 196 or the CID module 102 periodically calculates the optimum phase in a plurality of phase places.Then, the interlock circuit in TVPD 196 or the CID module 102 can calculate timing information data 372, offers phase-locked loop (PLL) (not shown among Fig. 3 a), is used to control the sampling operation of alternating expression ADC module 118.
With reference to Fig. 3 a, received signal 304 is provided for the data path 712 that includes separator 134, simulation process module, alternating expression ADC module 18, alternating expression equalizer module 132 and multiplexer (MUX) 150 after ROSA 107 receptions that are received on the machine 116.Separator 134 is separated into received signal the Parallel Simulation signal 348 that comprises a plurality of analog signals.Parallel Simulation signal 348 is provided for simulation process module 398 then.398 pairs of Parallel Simulation signals of simulation process module 348 are carried out various Signal Regulation, generate the analog signal 384 after handling.The characteristic of the Signal Regulation that simulation process module 398 is carried out will be described in more detail below.But Signal Regulation comprises gain-adjusted or analog filtering usually.Then, the analog signal 384 that simulation process module 398 generates after handling, this signal can be provided for alternating expression ADC module 118.Alternating expression ADC module 118 can effectively be carried out analog-to-digital conversion to the analog signal after handling 384 with this baud rate.As hereinafter will be in greater detail, alternating expression ADC module 118 can comprise a plurality of ADC, and each is all to be lower than the clock rate work of baud rate, make the combination operation of a plurality of ADC with this baud rate to 384 samplings of the analog signal after handling.
Alternating expression ADC module 118 exportable digital signals 386, next this digital signal 386 is provided for alternating expression equalizer module 132.As hereinafter will be in greater detail, the digital signal 386 that alternating expression ADC module 118 offers alternating expression equalizer module 132 can comprise a plurality of digital signals, independent ADC on each corresponding alternating expression ADC module 118.Alternating expression equalizer module 132 can be to digital signal 386 combine digital equilibrium treatment.Chromatic dispersion and ISI that the balanced recoverable communication channel 182 that alternating expression equalizer module 132 is carried out is introduced are described as hereinafter being about to.Alternating expression equalizer module 132 can comprise feed forward equalizer (FFE), DFF (DFE), order DFE and three's various combinations, will provide introduction follow-up.
Alternating expression equalizer module 132 can generate decision signal 388, offers multiplexer (MUX) 150.MUX 150 can generate the output after the multipath conversion, as shown in the figure.
Decision signal 388 also can be provided for TVPD 196.Analog signal 384 after the processing is provided for auxiliary ADC 394, and auxiliary ADC 394 can sample to the analog signal 384 after handling, and generates digital signal 374, for handling with decision signal 388 of 196 couples of TVPD.Auxiliary ADC 394 can be to be starkly lower than the sample rate work of baud rate.According to an embodiment, auxiliary ADC can work with 10MHz.
As mentioned below, CID module 102 can be calculated the estimating impulse response of communication channel 182 in a plurality of sampling phases each, and the usage degree gage periodically calculates the optimum phase in a plurality of phase places.Therefore TVPD 196 can use the optimum phase information that is calculated, determine regeneration or reference waveform, can (for example carry out based on Error Calculation like this, by the PLL 804 shown in Fig. 7 b) regularly to recover, wherein said Error Calculation is carried out between the actual output 386 of this regeneration or reference waveform and alternating expression ADC module 118.
Fig. 3 b is the detailed maps of signal processing system 140.As shown in Figure 1, signal processing system 140 can comprise microcontroller 138, is used to cooperate the operation and the built-in function of each assembly that comprises signal processing system 140.For example, microcontroller 138 can be in each functional module on the different time point triggering signal treatment systems 140.
For connection with high data rates, signal processing system 140 can be utilized one or more alternating expression assemblies.The alternating expression framework allows specific assembly to be lower than the clock rate work of symbol rate.For example, carry out a part of signal processing with regard to signal processing system in numeric field, signal processing system 140 can comprise alternating expression analog to digital converter (ADC) module 118.According to an embodiment, signal processing system 140 can be utilized the baud rate sampling, wherein with symbol rate received signal is sampled.Therefore, for example, the if symbol rate is 10Gbps, signal processing system 140 can utilize alternating expression ADC module 118 to realize the expectation baud rate sampling of 10Gbps, wherein alternating expression ADC module 118 can be used ADC parallel array (not shown among Fig. 3), and each ADC is with the sample rate work of 1.25Gbps.The bandwidth of each ADC in the ADC parallel array can be set near 5GHz.
In addition, signal processing system 140 can comprise alternating expression equalizer module 132, to correct various distorted signals, comprises chromatic dispersion and ISI.Alternating expression equalizer module 132 and alternating expression ADC 118 utilize the parallel minor structure of identical or different quantity.For example, according to an embodiment, alternating expression ADC118 comprises eight Parallel ADC, and each is all to be about the sample rate work of 1.25GHz.Alternating expression equalizer module 132 can comprise the parallel array that 16 equalizer fragments (slice) are formed, and wherein each equalizer fragment is all to be about the clock rate work of 625MHz.In a word, alternating expression ADC module 118 and alternating expression equalizer module 132 can utilize the parallel minor structure of any amount respectively, and work independently with the clock rate of any appropriate.In addition, above-mentioned value can be adjusted in case of necessity only as exemplary purpose, for example, if actual data rate departs under the situation of 10Gbps (for example, being other desired value of 10.3125Gbps or some), just can adjust.
Signal processing system 140 also can comprise regularly recovers module 105, recovers synchronously or regularly with DO symbol.Receiver clock (not shown among Fig. 3) can be regulated its frequency and phase place continuously, with the sampling instant of optimization received signal 304, and the frequency drift between the oscillator that uses in compensation transmitter clock and the receiver clock circuit (not shown among Fig. 3).Regularly recovering module 105 can offer timing information alternating expression ADC module, accurately carries out its sampling operation to guarantee alternating expression ADC module 118.In fact, for example,, regularly recover module 105 and impel alternating expression ADC module 118 to carry out sampling with symbol rate if signal processing system 1410 is carried out the baud rate sampling.
More specifically, regularly recover module 105 exportable timing informations and give separator 134, be separated into the suitable distance that is separated from each other a plurality of signals of (for example, separating 100ps) from the check-in signal of coarse adjustment PGA 130 to impel separator 134.In addition, regularly recovering module 105 can export alternating expression ADC module to via a plurality of interpolators, and alternating expression ADC can sample to baud with the step (for example, 1.5ps, 10ps baud-spaced, 64 phase interpolators) of very accurate adjustment like this.The following additional detail that recovers the one exemplary embodiment of module 105 about timing that provides with reference to Fig. 5 a.
Regularly recovering module 105 can comprise that coarse adjustment regularly recovers module 142 and accurate adjustment regularly recovers module 144.The purpose of these two structures will be described in detail hereinafter.But, usually coarse adjustment regularly recovers the optimum sampling rate of module 142 may command channels, and accurate adjustment regularly recovers the regularly mispairing of module 144 recoverables, described timing mispairing causes by having a plurality of ADC in the alternating expression ADC module 118, and/or owing in the process that will be separated into a plurality of signals corresponding with these a plurality of alternating expression ADC from the amplifying signal that receives of coarse adjustment PGA 130, occurring and operation separator 134 causes.
Signal processing system 140 can include channel identification (channel id) module 102, and as shown in the figure, channel identification module 102 may be output to the TVPD of Fig. 3 a.The 26S Proteasome Structure and Function of channel id module 102 will be described in more detail below.But usually, channel id module 102 can determine that communication channel characteristics is in difference real-time expression constantly.Channel characteristics for example can comprise, the impulse response of communication channel.Shown in Fig. 3 b, channel id module 102 can offer information regularly recovers module 105, to realize allowing more effective and regularly recovery operation more accurately.Especially, shown in Fig. 3 b, channel id module 102 can offer the parameter 312 that is called the DC skew herein regularly recovers module 105.
Can be for channel id module 102 provides channel id ADC 104 (similar or relevant with the ADC 394 among Fig. 3 a), so that the input signal that offers channel id 102 is sampled.Because the effect of channel id 102 is to be used for definite channel characteristics that changes with the speed that is starkly lower than symbol rate,, so channel id ADC104 is with the sample rate work different with the ADC that comprises alternating expression ADC 11.According to an embodiment, channel id ADC 104 can be with the sample rate work of 10MHz.
As hereinafter will be in greater detail, channel id 102 can be set up the representation of channel characteristics in the different phase of any amount.The expression in each stage can be stored in the channel id module 102, and can periodically determine an optimum phase.According to an embodiment, the best of channel represent to be chosen as after solving chromatic dispersion and ISI with signal energy maximized that.
The data path of signal processing system 140 will be described now.The analog signal 304 that is received is at first received by coarse adjustment programmable gain amplifier (PGA) module 130.PGA can be a variable gain amplifier.Coarse adjustment PGA module 130 can be amplified the signal 304 that is received, with the consistent amplitude level of the expection that realizes received signal 304.Digital control circuit (not shown among Fig. 3) can receive one or more numerical value, is used to control whole gains of rough PGA circuit 130.PGA circuit 130 can utilize passive and combination in any active circuit element realizes gain calibration.
Next, the received signal of handling through PGA module 130 304 can be provided for separator 134, and separator 134 generates the copy of suitable quantity at the signal that receives from PGA module 130.Separator 134 can be used for the input for the essential quantity of alternating expression ADC module 118 preparations.For example, according to an embodiment, alternating expression ADC module 118 comprises eight Parallel ADC.In this case, separator generates eight copies according to the signal that receives from PGA module 130.Because this group signal that the component mismatch in separator 134 circuit, separator 134 generate does not have consistent amplitude.This inconsistent in order to proofread and correct, each signal that separator 134 generates all is delivered to accurate adjustment PGA module 114.Accurate adjustment PGA module 114 can comprise a plurality of accurate adjustment PGA (not shown among Fig. 3), and each each signal that is respectively separator 134 generations provides independent amplitude to amplify.
Then, the set of parallel signal is passed to alternating expression ADC module 118.Especially, each the accurate adjustment PGA that comprises accurate adjustment PGA module 114 passes to each ADC in the alternating expression ADC module 118 with signal separately.The signal that alternating expression ADC module 118 can be used to from this group of received of accurate adjustment PGA 114 is carried out the baud rate sampling.The 26S Proteasome Structure and Function of alternating expression ADC module 118 will be described in more detail below.Usually, ADC module 118 can comprise a plurality of ADC, and each ADC is with the sample rate work of total symbol rate of being starkly lower than radio communications system.For example, according to an embodiment, the symbol rate of channel can be 10Gbps, and alternating expression ADC 118 comprises 8 parallel ADC, and each is all with the sample rate work of 1.25Gbps.
As mentioned and will be hereinafter more detailed introduction, CID module 102 can use the output of decision signal 310 and CID ADC 104 to determine the information relevant with the optimum angle information of communication channel.Next, for example, the rough TVPD 196 that regularly recovers in the module 142 provides regeneration or reference waveform according to this optimum angle information, coarse adjustment regularly recovers module 142 reference waveform is compared with the actual output of alternating expression ADC module 118, to determine the control information between them, control the sampling that is exaggerated received signal at separator 134 places and alternating expression ADC 118 places by for example (in a conventional manner) output for the phase signal that phase-locked loop uses then, recover thereby be used for auxiliary the execution regularly.
Fig. 4 is the schematic diagram that flows through the signal flow of signal processing system, and described signal processing system is used for the distorted signals that the correction communication channel is introduced.Received signal 304 is provided for coarse adjustment programmable gain amplifier (PGA) 130.Coarse adjustment PGA 130 regulates for the signal 304 that is received provides entire gain.Then, the output with coarse adjustment PGA 130 offers splitter circuit 134.Splitter circuit 134 can generate a plurality of copies through the signal of gain-adjusted, and each copy offers accurate adjustment PGA module 114 respectively.Especially, each output of separator module 134 offers parallel accurate adjustment PGA circuit 116 (1)-116 (N) respectively.For example under the control of accurate adjustment PGA controller 134, each parallel smart PGA circuit 116 (1)-116 (N) all can be carried out independent gain-adjusted to received signal 304 at digital control circuit.Parallel accurate adjustment PGA circuit 116 (1)-116 (N) is realized gain-adjusted, and described gain-adjusted comprises that to correction the inconsistent signal level in the alternating expression structure of signal processing system 140 is necessary.
Each parallel accurate adjustment PGA circuit 116 (1)-116 (N) can provide output to each ADC 120 (1)-120 (N) that comprises alternating expression ADC 118.The analog signal conversion that each ADC 120 (1)-120 (N) can provide the accurate adjustment PGA circuit 116 (1)-116 (N) of correspondence is a digital signal.The 26S Proteasome Structure and Function of alternating expression ADC 118 will be described in more detail below.But, usually, each ADC 120 (1)-120 (N) can with than the low clock rate of baud rate to sampling from the input signal of accurate adjustment PGA module 14.Like this, the efficiently sampling rate of combination ADC 120 (1)-120 (N) is a baud rate.As mentioned below, this can realize by each ADC 120 (1)-120 (N) is introduced phase deviation relative to each other.For example, according to an embodiment, baud rate is 10Gbps, and alternating expression ADC module 118 comprises 8 ADC, and all with the sample rate work of 1.25Gbps, this obtains the efficiently sampling rate of 10Gbps for each.Each ADC 120 (1)-120 (N) also can be with specific bit resolution work.According to an embodiment, each ADC 120 (1)-120 (N) provides 6 bit resolutions.
The output of alternating expression ADC module 118 can offer alternating expression equalizer module 132, and alternating expression equalizer module 132 comprises alternating expression FFE 424, alternating expression parallel judgment feedback equalizer 428 (1), 428 (2) and order DFE module 142.Alternating expression FFE module 424 can be carried out signal processing operations, reaches ISI with before proofreading and correct.Alternating expression FFE module 424 can comprise a plurality of FFE unit 124 (1)-124 (M).The quantity of FFE unit (M) is corresponding to the quantity of Parallel ADC 120 (1)-120 (N) or different with it.Therefore, each alternating expression FFE unit 124 (1)-124 (M) can be with the clock rate work different with the clock rate of each ADC 120 (1)-120 (N).Buffer circuit (not shown among Fig. 4) can be realized N output stream of alternating expression ADC module 118 (120 (1)-120 (N)) and offer M of alternating expression FFE module 424 (124 (1)-124 (the M)) coordination between the input.According to an embodiment, alternating expression FFE module 424 comprises 16 FFE unit 124 (1)-124 (M), and each all moves with the clock rate of 625MHz.The 26S Proteasome Structure and Function of each FFE unit 124 (1)-124 (M) will be in following detailed description.
Alternating expression PDFE module 428 (1) and 428 (2) can be worked and be reached ISI with before proofreading and correct.Each PDFE module 428 (1) and 428 (2) can comprise a plurality of summation modules, and each summation module calculates the summation of the output of the output signal of each alternating expression FFE unit 124 (1)-124 (M) and PDFE unit 128 (1)-128 (M) and 132 (1)-132 (M) respectively.
The output of each summation module can offer each amplitude limiter (slicer) 142 (1)-142 (M), 144 (1)-144 (M) in the order DFE module 144.Each amplitude limiter (slicer) 142 (1)-142 (M), 144 (1)-144 (M) can receive the input signal from each PDFE unit 128 (1)-128 (M) and 132 (1)-132 (M), with this input signal and threshold, and the output decision signal Whether the index signal value is below or above threshold value.According to an embodiment, each decision signal
Figure G071E8231720070911D000182
It can be the signal of a bit of expression+1 or-1 value.Each decision signal Can be routed back each PDEF unit 128 (1)-128 (M), 132 (1)-132 (M).Each PDFE unit 128 (1)-128 (M), 132 (1)-132 (M) can receive the decision signal from each amplitude limiter 142 (1)-142 (M), 144 (1)-144 (M)
Figure G071E8231720070911D000184
And to each summation module output valve.According to an embodiment, the output valve of each PDFE unit 128 (1)-128 (M), 132 (1)-132 (M) can be 16 bit values.
Decision logic module 480 in the order DFE module 142 can be selected a current effective PDFE from PDFE 428 (1) and 428 (2), as the effective and correct data that provide.More specifically, for example, when the output of FFE 424 falls in the uncertain scope, alternating expression PDFE 428 (1) and 428 (2) is forced to (for example give different values, 1 and-1), the decision logic module can be compiled each PDFE 428 (1) and 428 (2), and next (for example, the error measuring value in the bit period subsequently) is chosen in the PDFE that has low error in these a plurality of bit periods then a plurality of.
A plurality of decision signals from any amount of each amplitude limiter of current effective PDFE (for example, 142 (1)-142 (M) or 144 (1)-144 (M)) all can be routed to CID module 102 and/or regularly recover module 105.As described in reference Fig. 3 b, CID module 102 can provide optimum phase information to be used for the TVPD function, and regularly recovering module 105 also can provide baud rate phase place monitor function.
The CID module can comprise CID ADC 104, and CID ADC 104 can be to received signals 304 samplings (after being handled by coarse adjustment PGA 130).Because channel characteristics changes with the speed lower than baud rate, CIDADC 104 is with the clock rate work far below baud rate.According to an embodiment, for example, CID ADC 104 can work with 10MHz.Because CID module 102 significantly to be lower than the speed work of baud rate, according to an embodiment, has only the decision signal of a subclass
Figure G071E8231720070911D000191
Be routed to CID module 102 and regularly recover module 105.This can use multiplexer or buffer 497 to finish, and multiplexer or buffer 497 are selected one or more decision signals And be routed to CID module 102 and/or regularly recover module 105.
CID module 102 also can comprise CID filtering update module 106, CID filter 701, refresh circuit 729, high-speed cache 474 and CID optimum phase computing module 108.CID filter update module 106 can receive decision signal from current effective PDFE
Figure G071E8231720070911D000193
Subclass, based on this information and sampling received signal 304, the current channel characteristics of CD filter 701 renewable channels, this channel characteristics parameter turns to phase place, describes in detail hereinafter with reference to Fig. 7 a and 7b.Usually, as mentioned above, CID module 102 can be calculated the channel characteristics of a plurality of phase places.According to an embodiment, the CID module is calculated the channel characteristics of 16 outs of phase.Regularly recovering module 105 can send to CID ADC 104 with CID phase place update signal 112, to control the sampling phase of a plurality of channel characteristics phase calculation operations.According to an embodiment, but CID phase place update signal 112 regular updates, to impel the CID module to begin to generate the channel characteristics of new phase place.
Can use high-speed cache 474 that the channel characteristics of each phase place is cached in the CID module 102.CID optimum phase computing module 108 can regularly calculate the optimum phase in a plurality of different channels features that are stored in the high-speed cache, and this channel characteristics offered refresh circuit 729 (describing in more detail hereinafter with reference to Fig. 7 c), so the optimum phase information that refresh circuit 729 will be relevant with this channel characteristics offers TVPD module 196.The channel characteristics that TVPD module 196 can utilize CID optimum phase computing module 108 to provide is carried out the TVPD operation.TVPD module 196 also can receive a plurality of decision signals 310, and (and optimum phase information/channel characteristics) (for example generates reference waveform in view of the above, utilize the reference waveform maker 703 of Fig. 7 b), reference waveform is compared with the output of alternating expression ADC 118, thereby obtain the control information between them, be used for determining the phase signal of control PLL (for example, the PLL 804 among Fig. 7 b).
Accurate adjustment regularly recovers the output that module 138 can receive alternating expression ADC 120 (1)-120 (N).Owing to exist to handle deviation, a plurality of ADC 120 (1)-120 (N) and the circuit relevant with driving ADC and/or separator 134 may run into timing differential.Based on the input that alternating expression ADC 120 (1)-120 (N) provides, accurate adjustment regularly recovers a plurality of output signals can be provided, to proofread and correct the time change of ADC 120 (1)-120 (N).
In Fig. 4, show signal to noise ratio (snr) monitor 498 at last, its expression is used to detect the performance class of EDC system 140 or any suitable technique of feature.For example, can require EDC system 140 to maintain certain other error rate of level or other performance characteristic, to remain on the steady state operator scheme, if exceeded certain error threshold, then EDC system 140 can return starting state, to recalibrate the various settings of EDC system, (for example, with reference to starting state machine 126 with reference to Figure 11) as described in more detail in this.
Though Fig. 4 shows the specific function operation relevant with special construction, this only is exemplary, and those skilled in the art person will be understood that the tissue of special operational and function and execution can be implemented by the combination in any of structure among Fig. 4.For example, though Fig. 4 shows the TVPD relevant with regularly recovering module 105, TVPD operates or in fact a part wherein can be implemented in CID module 102.
Fig. 5 a is the work schematic diagram according to the alternating expression ADC of an embodiment.As described in reference Fig. 3 a, 3b and 4, can alternating expression ADC be set in data path 172, be used to proofread and correct waveguide dispersion and ISI.This data path can include in the assembly of coarse adjustment PGA 130, separator 134, accurate adjustment PGA 114, alternating expression ADC 118 and DEMUX circuit 512 and other and so on.
Alternating expression ADC 118 can be used for realizing baud rate or the suitable sample rate of symbol rate with received signal 304.For example, according to an embodiment, the baud rate of received signal 304 can be 10Gbps.As described in reference Fig. 4, alternating expression ADC 118 can comprise a plurality of ADC120 (1)-120 (n).Each ADC 120 (1)-120 (n) can be driven by common sampled clock signal, this sampled clock signal can be regulated by regularly recovering module 105, to proofread and correct the clock drift between the Receiver And Transmitter clock, make ADC120 (1)-120 (n) that the sampling clock of oneself be arranged.
Especially, regularly recovering module 105 can generate phase signal p (n), and as described in reference Fig. 7 a-7c, phase signal p (n) is provided for PLL 804.PLL 804 can generate output signal, to control the sampling phase of a plurality of ADC 120 (1)-120 (n).According to an embodiment, the single clock phase of PLL 804 controls, according to an embodiment, this single clock phase can be worked with 2.5GHz.By reproducible this single clock of a plurality of phase interpolators 514 (1)-514 (n).Each phase interpolator can generate the interpolation form of this single clock signal, and can control specific ADC 120 (1)-120 (n) respectively.In addition, as shown in the figure, (for example, circuit is managed in sampling to the corresponding circuits in each phase interpolator 514 (1)-514 (n) may command separator 134, as shown in Figure 5).Between each phase interpolator 514 (1)-514 (n), corresponding drive circuit 530 (1)-530 (n) can be used for driving or operation separator 134.For example, this drive circuit can comprise buffering, amplification or the timing circuit (for example, clock) that is used by separator 134 and/or ADC 118.In addition, because separator 134 includes digital circuit, this drive circuit will include analog to digital converter.In addition, on the chip between interpolator and the separator 134/ADC 118, has relatively long signal path.Therefore, factor that these are mentioned or other factors can cause the operation of separator 134 undesirable, therefore cause the operation of alternating expression ADC 118 undesirable.Regularly recovering accurate adjustment in the module 105 regularly recovers module 144 and can be used for regulating separately each phase interpolator 514 (1)-514 (n), to solve and these undesirable change problems when relevant, like this, because special purpose, alternating expression ADC 118 can be used as single ADC with baud rate work.For example, can select first phase interpolator/ADC to as a reference, remaining phase interpolator/ADC to all with respect to this with reference to regulating.Therefore, first phase interpolator/ADC can work based on p (n) to 514 (1)/120 (1), remove with reference to other external each phase interpolator/ADC working with corresponding difference or Delta (just, [p Δ (n)] (2)-[p Δ (n)] (N)) between the required phase place of the relative timing that is used to keep every pair based on p (n).
Fig. 5 b is the more detailed schematic diagram according to the ADC framework of an embodiment.In Fig. 5 b, separator 134 comprises a plurality of sampling hold circuits 522 (1)-522 (N), these circuit individual drive PGA 116 (1)-116 (N), as shown in the figure.Circuit 532 provides the example of gain circuitry, wherein uses variableimpedance to change the entire gain of PGA 116 (N).Simultaneously, circuit 534 provides the example that uses the adc circuit of quickflashing ADC.Circuit 532 and 534 only is exemplary, also can use other suitable circuit.Shown in Fig. 5 b, sampling hold circuit 522 (1)-522 (N) is designed to receive the clock signal (for example, sampling hold circuit can receive 2 non-stack clock signals) of 1.25GHz, thereby with the interval of 100ps input signal is sampled.As mentioned above, accurate adjustment regularly recovers module 144 and regulates the timing information that offers the phase interpolator among Fig. 5 a, the interval that can keep 100ps like this, no matter whether undesirable relatively situation (for example, because other mismatches in temperature, technology or its design and the manufacture process) is arranged in each drive circuit 530 (1)-530 (N).
Fig. 5 c is the overall work schematic diagram according to the alternating expression ADC of an embodiment.As mentioned above, alternating expression ADC 118 can comprise a plurality of ADC 120 (1)-120 (n).Each ADC 120 (1)-120 (n) can be triggered by the receiver clock on the specific period 208.The efficient of receiver clock 208 is the baud rate that is transmitted.But the clock rate of specific ADC 120 (1)-120 (n) can significantly be lower than baud rate.
Fig. 6 a is the schematic diagram of the signal path of alternating expression FFE.According to an embodiment, alternating expression FFE utilizes parallel organization to receive 16 input signal X (n)-X (n+15), and generates 16 output signal Y (n)-Y (n+15).This only is exemplary, and alternating expression ADC can comprise the input signal of any amount and the output signal of any amount.For example, the serial FFE with 8 taps (tap) can be embodied as the convolution of input signal and FIR.
y ( n ) = Σ i = 0 7 c ( i ) x ( n - i )
According to an embodiment, alternating expression FFE 118 generates 16 output y (n)-y (n+15), and this output is the function of 16 input x (n)-x (n+15), has following relation:
y(n)＝c(0)x(n)+c(1)x(n-2)+c(2)x(n-2)+c3x(n-3)+...+c(7)x(n-7)
y(n+1)＝c(0)x(n+1)+c(1)x(n)+c2x(n-1)+c3x(n-2)+...+c(6)x(n-6)
·
·
·
y(n+15)＝c(0)x(n+15)+c(1)x(n+14)+c2x(n+13)+c3x(n+12)+...+c(7)x(n+8)
With reference to Fig. 6 a, alternating expression FFE 424 can receive a plurality of input x (the n)-x (n+15) on a plurality of independent incoming lines 615 (1)-615 (16).FFE 424 can go up at a plurality of output lines 617 (1)-617 (16) and generate a plurality of output y (n)-y (n+15).Each incoming line 615 (1)-615 (16) can comprise a plurality of multiplication and (MAC) module 623 (1)-623 (n) that adds up.Each MAC module 623 (1)-623 (n) can comprise multiplier module 533 and summation module 534 separately.Each MAC module 623 (1)-623 (n) is connected to separately incoming line 615 (1)-615 (16) by its multiplier module 533, and multiplier module 533 provides input port for the MAC module.Each MAC module 623 all can be connected to different output line 617 (1)-617 (16) by summation module 534 separately, and summation module 534 is as the output port of MAC module 623.
The input of specific incoming line 615 (1)-615 (16) (x (n)-x (n+15)) can be provided for a plurality of MAC modules that are connected to incoming line by its multiplier module 533, wherein coefficient CX is multiply by in this input respectively, is provided for this MAC module 623 summation module 534 separately then.The output of each summation module 534 merges with the output of other MAC module 623 that is connected to different incoming lines.
Fig. 6 b is the schematic diagram according to the serial D FE unit of an embodiment.A channel in the parallel array that expression alternating expression PDEF 428 (1), 428 (2) is set shown in Figure 6.Input signal x (n) is provided for summation module 542, merges with the output addition of PDFE unit 128 at this input signal x (n).Next the output of summation module 542 is provided for amplitude limiter 142.Amplitude limiter 142 is less than or greater than zero according to the input of giving it, generates binary signal (for example ,+1 ,-1).The output of amplitude limiter 142 is provided for a plurality of delay units, and for example 548 (1)-548 (4), delay unit generates time delayed signal y (n)-y (n-4) separately.Time-delay output signal y (n)-y (n-4) is provided for PDFE unit 128, and PDFE unit 128 generates output signal F (y (n), y (n-1), y (n-2), y (n-3), y (n-4)).Output signal F (y (n), y (n-1), y (n-2), y (n-3), y (n-4)) can be the linear combination of inhibit signal y (n)-y (n-4).According to an embodiment, each binary signal y (n)-y (n-4) can multiply by the coefficient of 16 bits, to generate the numerical value of 16 bits.The value of these 16 bits is carried out the linearity merging by PDFE unit 128 then.
Fig. 7 a is the part work schematic diagram according to the CID filtering update module 106 of an embodiment.Regularly the more detailed example of recovery and channel identification operation provides with reference to Fig. 7 b and 7c following.In Fig. 7 a, CID filtering update module 106 can be included in TVPD 196 or the CID 102, the estimation channel characteristics of renewable communication channel 182.As mentioned above, channel characteristics can be the impulse response of communication channel 182.CID filtering update module 106 can be calculated a plurality of channel characteristics of a plurality of different sampling phases of communication channel 182.Therefore, for example, be under the situation of impulse response at channel characteristics, CID filter update module 106 can be calculated a plurality of channel impulse response estimations, and these a plurality of channel impulse response estimations are expressed as h by phase parameter (p) and iterative parameter (n) parametrization n p(k).As mentioned below, CID optimum phase computing module 108 can be according to a plurality of channel characteristics calculating optimum phase channel features, this optimum phase channel characteristics is used to recover module 105 to timing provides timing to recover auxiliary signal, recovers (not shown among Fig. 7) with auxiliary timing.
CID filtering update module 106 can be upgraded to phase bit h by error signal e (n) N+1 pThe next iteration of channel impulse response estimation (k).By getting the decision signal after being sampled received signal 304 and being handled by CID filter 701 Between difference, can calculate error signal e (n).For example, CID filtering update module 106 can be with each phase place h N+1 p(k) coefficient " h " offers CID filter 701, is used for generating thus the waveform of comparing with the time-delay output of CID ADC 104, as shown in the figure, and next determines e (n).
Refer again to Fig. 7 a, the signal 304 that is received is provided for data path 172 (above with reference to Fig. 3 a, 3b and 4 described).After data path 172 is handled, can generate decision signal
Figure G071E8231720070911D000241
As described above with reference to Figure 4, data path 172 can generate (render) a plurality of decision signals, wherein has only the subclass of decision signal to be selected to route to CID module 102 by multiplexer or router.This is very likely, because the CID module can be to be lower than the clock rate work of baud rate.Decision signal 310 is provided for the CID filter update module 106 at CID module 102 places then.
Shown in Fig. 7 a, received signal 304 also is provided for CID ADC 104, and 104 pairs of received signals of CID ADC are carried out analog-to-digital conversion.CID ADC 104 can be with the clock rate work of the time-varying characteristics of enough tracking channel characteristics.According to an embodiment, for example, CID ADC 104 can work at 10MHz.Regularly recovering module 105 can offer CID ADC 104 with CID phase place update signal 112, with the sampling phase of control CIDADC 104.But regularly recover module 105 regular update CID phase place update signal 112.According to an embodiment, CID module 102 can be calculated 16 out of phase h N+1 p(k) channel impulse response estimation.
After CID ADC 104 samplings, the sampled form of received signal is provided for time delay module 502.Time delay module is essential for the time-delay that compensates the signal 304 that is received by data path 172.The delayed version of the sampled form of received signal 304 is provided for summation module 702 then, and the difference between the output of summation module 702 calculating samplings and time-delay received signal 304 and CID filter 701 is with generated error signal e (n).Error signal e (n) is provided for CID filtering update module 106, to handle the next iteration of channel impulse response estimation.
According to an embodiment, CID filtering update module 106 can be utilized decision signal Error signal e (n), channel impulse response estimation h n p(k) the next iteration h that a preceding iteration and parameter μ calculate channel impulse response estimation N+1 p(k).According to an embodiment, CID filter update module 106 can utilize following relational expression to calculate the next iteration of channel impulse response estimation:
h n + 1 p ( k ) = h n p ( k ) + μe ( k ) a ^ ( n - k )
Fig. 7 b determines the work schematic diagram of channel characteristics information with the auxiliary timing recovery operation according to the CID module of an embodiment.Usually, best estimate impulse response h Opt(n) and decision signal can be used for the estimated value of regenerative reception signal y (n) by reference waveform maker 703, as regularly recovering auxiliary signal Regularly recover auxiliary signal
Figure G071E8231720070911D000245
312 can be provided for the auxiliary timing recovery operation.Especially, regularly recovering coarse adjustment in the module 105 regularly recovers module 142 and can receive and regularly recover auxiliary signal
Figure G071E8231720070911D000246
312, and in the Mueller-Muller algorithm, utilize timing to recover auxiliary signal 312 and carry out regularly recovery operation, phase signal p (n) can be generated like this, to drive the sampling phase of PLL 804 control alternating expression ADC 118.
Though Fig. 7 b has described the certain functional modules of carrying out some function and/or operation, those skilled in the art person will be understood that this only is exemplary.Utilize channel characteristics (for example, the estimating impulse response of communication channel) to come the timing recovery operation of auxiliary and/or executive communication system also can carry out by individual feature unit or a plurality of functional unit.In addition, the operation that belongs to TVPD 196 in fact also can rather than regularly recover module 105 and carry out by CID module 102.As another example, CID filter 701 can be by carrying out with reference waveform maker 703 identical or similar modules.
According to exemplary embodiment, CID module 102 can comprise CID ADC 104, time delay module 502, summation module 702, CID filter update module 106, high-speed cache 474 and refresh circuit 729.Received signal 304 is provided for data path 172, and data path 172 comprises AFE (analog front end) 739, alternating expression ADC 118, FFE424, DFE 428 and the sequence D FE 142 in the signal processing system.AFE (analog front end) 739 can be carried out simulation process to received signal 304, comprises the amplitude adjustment to received signal.The output of AFE (analog front end) 739 can be provided for the CID ADC 104 among the CID 102.CID ADC 104 can carry out analog-to-digital conversion to the output of AFE (analog front end) 739.CID ADC 104 can be significantly to be lower than the data transfer rate work of baud rate.
The output of AFE (analog front end) 739 also can be provided for alternating expression ADC 118, is alternating expression FFE 424, alternating expression DFE 428 and order DFE 142 after the alternating expression ADC 118.Order DFE 142 exportable decision signals 310 offer CID filtering update module 106 and reference waveform maker 703 among the CID 102.The operation of CID filtering update module 106 is described with reference to Fig. 7 a.Just, after CID ADC 104 finished analog-to-digital conversion, the output of CID ADC 104 was provided for time delay module 502.The output of time delay module 502 offers summation module 702, at this output calculated difference signal (e (n)) that uses CID filtering update module 106, then difference signal (e (n)) is returned to CID filtering update module 106, thereby offers CID filter 701.
CID 102 also can include high-speed cache 474.The channel impulse response estimation of the renewal that CID filtering update module 106 calculates is provided and is stored in the high-speed cache 474.As will be described in more detail, the estimation channel response parameterisable of high-speed cache is phase parameter (p), by optimum phase computing module 108 it is carried out periodic analysis, optimum phase computing module 108 utilizes predetermined tolerance chi to calculate best estimate channel impulse response (optimum phase just).
The best estimate channel impulse response (h ' Opt(n)) can offer refresh circuit 729 (following with reference to Fig. 7 c describe in detail), and and then offer reference waveform maker among the TVPD 196, as shown in the figure.Therefore TVPD 196 can utilize best estimate channel impulse response h Opt(n) carry out the TVPD operation, regularly recover auxiliary signal to generate
Figure G071E8231720070911D000261
312, regularly recover auxiliary signal
Figure G071E8231720070911D000262
312 can be used for the auxiliary timing recovery operation.Especially, TVPD 196 also can receive decision signal 310, and adopts decision signal 310, utilizes the optimum pulse response h of current estimation Opt(n) generate re-constructing or reconstituted form of received signal y (n).The reconstituted form of received signal y (n) Can be used as regularly and recover auxiliary signal, offer regularly and recover module 105, be used for regularly recovery operation.According to an embodiment,, regularly recover auxiliary signal according to following formula
Figure G071E8231720070911D000264
The 312nd, current best estimate impulse response h Opt(n) and the convolution of decision signal 310: (assignment of following equation is
Figure G071E8231720070911D000265
Rather than h (n))
y ^ ( n ) = Σ j h opt ( j ) a ^ ( n - j )
Regularly recover auxiliary signal 310 in case receive, regularly recover module 105 and can utilize the Mueller-Muller algorithm to carry out regularly recovery operation.Especially, regularly recovery operation 105 can be calculated reproduction waveform
Figure G071E8231720070911D000267
Slope (slope), and this slope be multiply by real data and the reproduction waveform that audio data AD C y (n) is received
Figure G071E8231720070911D000268
Between error.In order to carry out this operation, regularly recovering module can comprise a plurality of delay units, to arrange actual data signal and regenerated signal.With reference to Fig. 7 b, regularly recovering module 105 can comprise that coarse adjustment regularly recovers module 142.Coarse adjustment regularly recovers module 142 and generates phase signal p (n), comprises whole sampling phases of each ADC of alternating expression ADC 118 (following will the detailed description in detail) with control.
Coarse adjustment regularly recovers module can comprise time delay module 502, summation module 711, first delay unit 715, second delay unit 717 and multiplier module 719.At least one output that comprises a plurality of ADC of alternating expression ADC 118 is provided for coarse adjustment and regularly recovers time delay module 502 in the module 140, makes it and rebuilds signal
Figure G071E8231720070911D000269
In conjunction with.The output of time delay module 502 offers summation module 711, recovers auxiliary signal in this this output and timing 312 merge, and generate difference signal e ' (n).Difference signal e ' (n) available following formula calculates:
e , ( n ) = y ( n - k ) - y ^ ( n )
Difference signal e ' (n) is provided for delay unit 715, delay unit 715 generated error signals sampling delayed version e (n-1), and this sampling delayed version is provided for multiplier module 719.Regularly recover auxiliary signal
Figure G071E8231720070911D0002612
312 also can offer 717 generations of second delay unit, 717, the second delay units regularly recovers auxiliary signal Copy and the timing of being delayed time by double sampling recover auxiliary signal 312 delayed version.First and second delay units 715 and 717 output offer multiplier module 719, and multiplier module 719 generates phase signal p (n) as output with two signal multiplications.Therefore, phase signal p (n) is an error signal e ' (n) with the product of the slope of (regeneration) waveform:
Figure G071E8231720070911D000273
In other words, can know from above explanation,
Figure G071E8231720070911D000274
Therefore the convolution of the impulse response of the DFE that expression is calculated (or order DFE) judgement supposes that the desired value y (n) of impulse response is effective.Therefore error signal e ' (n) multiply by reproduction waveform
Figure G071E8231720070911D000275
Slope (be expressed as
Figure G071E8231720070911D000276
), and, obtain phase signal p (n) according to the Mueller-Muller algorithm.Phase signal p (n) offers PLL 804, is used to control the sampling phase of the alternating expression ADC that comprises alternating expression ADC module 118.
Fig. 7 c is the work schematic diagram according to the optimum phase computing module of an embodiment.Optimum phase computing module 108 can be included in the CID module 102, can determine that parameter turns to the best estimate pusing channel feature h ' of a plurality of channel characteristics of phase place Opt(n) 312.As mentioned above, CID filtering update module 106 can be stored a plurality of estimating impulse response h in high-speed cache 474 0[0:I]-h i[0:I], wherein each all parameter turns to out of phase from 0-i.According to an embodiment, be stored in each the estimating impulse response h in the high-speed cache 0[0:I]-h i[0:I] is all relevant with a plurality of taps (tap), and for example i can be 6.
CID optimum phase computing module 108 can be from a plurality of impulse response h 0[0:I]-h iRegularly determine optimum pulse response h ' in [0:I] Opt(n), each estimating impulse response h wherein 0[0:I]-h i[0:I] is all relevant with each phase place and be stored in the high-speed cache 474.CID optimum phase computing module 108 can be attempted specific tolerance chi is minimized or maximizes, to determine h ' Opt(n).Just, CID optimum phase computing module 108 regularly will be measured chi and be applied to be stored in a plurality of impulse response signal h in the high-speed cache 474 0[0:I]-h i[0:I].For example, CID can comprise timer 798.According to the operation of timer 798, send signal to CID optimum phase computing module 108, with according to h 0[0:I]-h i[0:I] determines h ' Opt(n).In case determined h ' Opt(n), the timer of just resetting, this process reinitializes.According to an embodiment, CID optimum phase computing module 108 availability gages will be with respect to the ISI energy minimization of the channel impulse response estimation signal of principal tapping (main tap).For example, according to an embodiment, the tolerance chi that is maximized is: (wherein first h (3) is at principal tapping, and other is the ISI item):
[h p(3)] 2-[h p(2)] 2-[h p(1)] 2-[h p(0)] 2-[h p(4)] 2-[h p(5)] 2
Determined h ' in case utilize above-mentioned minimum ISI energy metric chi Opt(n) 312, h ' Opt(n) just can offer TVPD 196, be used for and regularly recover module 105 and combine and carry out timing and recover auxiliary operation (generation phase signal p (n) just).But, according to an embodiment, with h ' Opt(n) offer before the TVPD 196, by 729 couples of h of refresh circuit Opt(n) handle.This needs, because tracking error can not upgraded the phase place of TVPD 196 too soon.Refresh circuit 729 impels slow renewal to offer the h of TVPD 196 Opt(n), the undated parameter that is wherein provided is expressed as h at this Opt(n).
Refresh circuit 729 can comprise high-speed cache 752, ramp circuit 754, multiplexer 756 and multiplier module 758.H ' Opt(n) can be provided for high-speed cache 752, provide a plurality of h ' at CID optimum phase computing module 108 Opt(n) time, high-speed cache 752 these a plurality of h ' of storage Opt(n).Threshold circuit 756 can be judged current optimum phase h ' constantly at each clock Opt(n) with the h that is stored in the high-speed cache 752 Opt(n) difference between.Especially, only at h ' OptWhen variation (n) surpassed certain programmable threshold, refresh circuit just can work, to upgrade high-speed cache.This error can slowly be upgraded the h ' that offers TVPD 196 by the value that obtains after removing divided by a bigger value Opt(n).
Fig. 8 has described the operation of baud rate phase detectors.Before CID 102 determines channel impulse response estimation (just, when signal processing system 140 is in start-up mode), signal path shown in Figure 8 can be in the work.As shown in Figure 8, regularly recovering module 105 can comprise that coarse adjustment regularly recovers module 142 and accurate adjustment regularly recovers module 138.Coarse adjustment regularly recovers module 142 can comprise baud rate phase detectors 198.The baud rate phase detectors comprise time delay module 802, first multiplier module 804, second multiplier module 806, delay unit 810 and summation module 808 again.
Received signal 304 can offer data path 172, and data path 172 comprises AFE (analog front end) 739, alternating expression ADC 118, alternating expression FFE 424, alternating expression DFE 428 and order DFE 142.The signal 304 that is received can offer AFE (analog front end) 739, and AFE (analog front end) 739 can be carried out analog to received signal.The output that simulated after front end 739 is handled offers alternating expression ADC 118, and ADC 118 can carry out analog-to-digital conversion to the analog signal after handling.The output of alternating expression ADC 118 offers alternating expression FFE424.The output of alternating expression FFE 424 offers alternating expression DFE 428.The output of alternating expression DFE 428 offers order DFE 142.Order DFE 142 generates decision signal
Figure G071E8231720070911D000281
310.Decision signal
Figure G071E8231720070911D000282
310 also can offer channel id module 102, and channel id module 102 can generate regularly recovers auxiliary signal 312, is called as dc_offset signal (just, the auxiliary signal 312 under the start-up mode comprises the dc_offset value at least) herein.
At least one numeral output of alternating expression ADC 118 is provided for the time delay module 802 in the baud rate phase detectors 198.The decision signal that order DFE 140 generates
Figure G071E8231720070911D000291
310 are provided for the delay unit 810 in first multiplier module 804 and the baud rate phase detectors 198.The output of time delay module 802 also is provided for first multiplication unit 804, and in first multiplication unit 804, decision signal is multiply by in this output
Figure G071E8231720070911D000292
310.Delay unit 810 can generate decision signal
Figure G071E8231720070911D000293
Two kinds of sampling delayed versions of 310, and offer second multiplier module 806, the decision signal of time-delay in second multiplier module 806
Figure G071E8231720070911D000294
310 with the output multiplication of time delay module 802.Next the output of second multiplier module is provided for summation module 806, and the timing that this output and channel id module 102 provide in summation module 806 recovers auxiliary signal 312 (dc_offset) and merges.
Summation module 808 can utilize following relational expression that the output of first multiplier module 804 and the output of second multiplier module 806 are merged, and generates phase signal p (n), wherein A﹠amp; B is a scalar constant, and this relational expression can be called as dc phase detectors relation at this:
p ( n ) = [ A a ^ ( n ) - B a ^ ( n - 2 ) ] * delay [ x ( n ) ] + dc _ offset
Fig. 9 is the workflow diagram according to the signal processing system of an embodiment.This process is from step 902.At step 909 receiving electromagnetic signals.This electromagnetic signal can be received by communication channel 182 by receiver.In step 904, upgrade the sampling phase of alternating expression ADC.As said, alternating expression ADC can be controlled by the performed timing recovery operation of baud rate phase detectors, TVPD or both combinations.As previously mentioned, phase detectors (TVPD or baud rate) can generate phase signal p (n), offer PLL, with the sampling clock of control alternating expression ADC.Though Fig. 9 shows this step and occurs in sequence that the renewal of ADC sampling phase 904 can be carried out with other steps described in Fig. 9 are parallel.
In step 906, received signal is carried out analog.According to an embodiment, analog can comprise variable gain amplification or other processing.In step 907, the analog signal after handling is carried out analog-to-digital conversion.According to an embodiment, can use alternating expression ADC to carry out analog-to-digital conversion in staggered mode.In step 908, to the output combine digital equalization of ADC.According to an embodiment, can use the alternating expression equalizer module to carry out equilibrium treatment in staggered mode.According to an embodiment, the alternating expression equalizer can comprise alternating expression FFE, alternating expression DFE and order DFE.In step 910, the alternating expression signal that alternating expression structure (ADC and equalizer) is provided merges, and generates composite signal.This process finishes in step 912.
Figure 10 is the workflow diagram performed according to the signal processing system of an embodiment.Can in the steady state operation of signal processing system, (just, after start-up operation is finished) carry out process shown in Figure 10.Therefore, suppose that h_opt (n) determines, system is stable (just, filter converges).This flow process begins in step 1002.In step 1007, the initialization timer.In step 1004, test, to judge that whether timer is in operation.If there be not (the "No" branch road of step 1004), in step 1010, carry out filter update.Filter update can be the program of the impulse response of estimation of communication channels.
In step 1012, received signal 304 is offered the data path and the CID module of signal processing system 140.In step 1014, data path can be handled the EM signal, generates decision signal 310.In step 1016, use decision signal 310 to generate regenerated signal
Figure G071E8231720070911D000301
To determine the optimum pulse response h_opt (n) of communication channel.According to an embodiment, can generate regenerated signal by TVPD.In step 1018, can use regenerated signal
Figure G071E8231720070911D000302
Carry out regularly recovery operation.According to an embodiment, regularly recovery operation can be used the deformation algorithm of Mueller-Muller algorithm.Flow process proceeds to step 1004 then.
If timer moves (the "Yes" branch road in the step 1004), in step 1006, carry out the optimum phase calculating operation.The optimum phase calculating operation can use predetermined tolerance chi to determine the best estimate impulse response of communication channel.In step 1011, best estimate impulse response is offered TVPD.Next flow process proceeds to step 1012.
Figure 11 is the workflow diagram of the starting state machine of an embodiment, for example the starting state machine among Fig. 1.Generally speaking, Figure 11 has described startup, execution or other management of EDC system 140 states among Fig. 1.Equally, Figure 11 is used for describing Fig. 1 starting state machine 126, but is not limit or comprehensively description.For example, the conventional func of the starting state machine that can be carried out by starting state machine 126 or technology be not in this detailed description.For example, can adopt a plurality of registers or timer (not going out among Figure 11), be used to store and control the various states of EDC system 140 to clearly showing or description.In addition, starting state machine 126 can be finished some or all function of describing with reference to Fig. 1-10, or suitable function, though do not describe all these functions among Figure 11 fully.
In Figure 11, starting state machine 126 is sought the best setting of each module usually, comprises ADC 120, equalizer 132, coarse adjustment and fine tuning PGA 132/134, CID 102 and regularly recovers module 105.Like this, starting state machine 126 can be implemented many known settings, selects only value from these are provided with, to obtain the expected performance of EDC system 140.In case reach the performance level of expectation, next starting state machine 126 is responsible for monitoring this performance class, and in the time must keeping and recover this performance class, starting state machine 126 is responsible for recalibrating and restarting.
Therefore, in Figure 11,, can use acquiescence initial value (for example, 1) to converge PLL 804 from the dc_offset value of baud rate phase detectors 198 (step 1102) in initial condition.Next, coarse adjustment PGA 130 stable (step 1104) for example is stable at the preset value in the available gain ranging.Dropout (LOS) module (not shown) can be activated (step 1106), is used for losing or lacking (for example, by monitoring the situation of ADC signal with respect to reference threshold) of detection signal.
Next, select dc_off (step 1108), and carry out dc_off (step 1110) at three available phases detectors.For example, with reference to Fig. 8, can select some initial value of dc_off, baud rate phase detectors 198 can be embodied as the dc phase detectors, for example, as reach before one or more phase detectors, after reach phase detectors and/or symmetrical phase detector.Just, can make setting, and determine channel impulse response in view of the above channel characteristics.Next selective channel impulse response, when regularly recovering to compile, this channel impulse response is relatively near actual channel impulse response.
In an example, baud rate phase detectors 198 can set the dc_off value be positioned at some scope (for example ,-5---5), can be with predetermined increment through these values.For each increment size, some or all dc phase detectors can be performed, and converge and/or arrive some performance threshold until regularly recovery takes place, and/or all used up (those values of therefrom selecting optimum value) until all values.For example, in aforesaid phase detectors relation, some setting about channel characteristics (for example, reach before having, then reach or symmetrical ISI) allows one or multinomial for known or set, and can calculate phase signal in view of the above.
In the example of Figure 11, some is similar, can be by select the tap value from available numerical value storehouse, with equalizer 132 initialization (step 1112).Suitably use selected value, coarse adjustment TR 142, FFE 124 (1)-124 (n) and DFE 128 (1)-128 (M) can be unlocked, and keep stable state according to default timer value, and coarse adjustment PGA also can (again) keep stable state (1114).These operations (step 1112,1114) can repeat until having determined acceptable tap value, and according to this tap value, fine tuning TR and fine tuning PGA loop are unlocked, and allow to keep stable state (step 1116).
In Figure 11, external loop-around can continue the next one value (step 1118) of dc_off, and perhaps, if determined suitable dc_off, channel id and regularly recover beginning (step 1120) next is for example as described in reference Figure 10.If SNR monitor 498 determines that current SNR value is unacceptable (step 1122) in this operation, then opening sequence DFE 142, are used for the additional performance gain.In other embodiments, order DFE 142 sustainable unlatchings.If performance gain is not enough to SNR is remained on acceptable level, then reinitialize dc phase detectors, equalizer and other assembly (step 1108-1118).Certainly, also can be in addition or optionally monitoring other except that SNR measure chis, reinitialize determining whether.As long as obtain acceptable SNR level, clock and data recovery (CDR) will lock, and CID and timing recover to continue (step 1120).
The embodiment of various technology described here can implement with digital circuit, perhaps implements with computer hardware, firmware, software and combination thereof.Embodiment can be used as computer program and implements, just, (for example can be embedded in the information carrier, in the signal of machine readable storage device or propagation), be used for being carried out or the operation of control data treatment facility by data processing equipment, described data processing equipment is for example programmable processor, computer or a plurality of computer.Computer program, aforesaid computer program can be write by programming language in any form, comprise compiling or interpretative code, and can use in any form, comprise for example stand-alone program, perhaps module, assembly, subprogram or other unit of being suitable in computing environment, using.Computer program is used on a computer or a plurality of computer and moves, and described a plurality of computers can be positioned at same place or be distributed in a plurality of places and pass through communication network mutual.
Method step can be carried out by one or more programmable processors, this programmable processor operation computer program, to carry out function by dateout is operated and generated to the input data. method step also can be carried out by dedicated logic circuit, equipment also can be embodied as dedicated logic circuit, for example FPGA (field programmable gate array) or ASIC (application-specific integrated circuit (ASIC)).
The processor that is suitable for computer program comprises, for example general and special microprocessor, and any one or a plurality of processor of the digital computer of any kind of.Usually, processor can receive instruction and data from read-only memory or random access memory or both.The element of computer comprises at least one processor that is used to execute instruction and is used for store instruction and one or more memory devices of data.Usually, computer also can comprise one or more mass-memory units that are used to store data, perhaps be operably connected to one or more mass-memory units that are used to store data, therefrom to receive data or to launch data to it, described mass-memory unit for example is, disk, magneto optical disk or CD.The information carrier that is suitable for comprising computer program instructions and data comprises the nonvolatile storage of form of ownership, comprise for example semiconductor memory apparatus of EPROM, EEPROM and flash memory and so on, the disk of internal hard drive or moveable magnetic disc and so on, magneto optical disk, and CD-ROM and DVD-ROM CD.Processor and memory can be implemented by dedicated logic circuit, perhaps are attached in the dedicated logic circuit.
Though described some feature of described embodiment at this, those skilled in the art person can make a lot of modifications, replacement, changes and be equal to.Therefore, be appreciated that claim is used to cover all such modifications and the change in the essential scope that falls into embodiments of the invention.

Claims (9)

1. system to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is characterized in that with the symbol rate beared information described system comprises:
Alternating expression analog to digital converter module, described alternating expression analog to digital converter module is used for generating a plurality of digital sampled signal according to described electromagnetic signal;
Alternating expression equalizer module, described alternating expression equalizer module are used for each digital sampled signal that described analog to digital converter module generates is carried out digital processing, to generate a plurality of digital equalising signals; And
Multiplexer, described multiplexer are used for the digital equalising signal gathering is become composite output signal;
Regularly recover module, described timing recovers the sampling phase that module is used for determining expectation, and the sampling phase of described expectation is offered described alternating expression analog to digital converter module; Wherein said timing recovers module based on best estimate channel response Signal Regulation timing recovery algorithms;
A plurality of phase interpolators, wherein each phase interpolator provides corresponding clock signals based on the sampling phase of described expectation to described alternating expression analog to digital converter module, and described alternating expression analog to digital converter module further uses each corresponding clock signals to generate one or more in described a plurality of digital sampled signal.
2. system according to claim 1 is characterized in that described system also comprises channel identification module, and described channel identification module is used for determining the feature of communication channel, and the feature of described communication channel offered regularly recovers module.
3. system according to claim 2 is characterized in that, described timing recovers the algorithm that module also utilizes channel characteristics information to regulate to be used for the sampling phase of determining expectation.
4. system according to claim 2 is characterized in that, described channel identification module is also determined the sampling phase of expectation, and the sampling phase of described expectation is offered described timing recovery module.
5. system according to claim 4 is characterized in that described channel characteristics comprises channel impulse response, and described channel identification module also is used for:
Reception is from the output of described equalizer module;
Second digital sampled signal that reception generates according to described electromagnetic signal; And
According to the output and described second digital sampled signal of described equalizer module, upgrade at least one coefficient of described channel impulse response.
6. method to the electronic dispersion compensation that receives by communication channel, described electromagnetic signal is characterized in that with the symbol rate beared information described method comprises:
Reception is with the electromagnetic signal of symbol rate beared information;
Upgrade the expectation sampling phase of alternating expression analog to digital converter, comprising calculating described expectation sampling phase by selecting one the one group of channel impulse response estimation signal that all has particular phases from each;
Electromagnetic signal is carried out variable gain amplifies;
Electromagnetic signal is carried out the alternating expression analog-to-digital conversion to generate a plurality of staggered digital signals;
In a plurality of staggered digital signals each is carried out equilibrium treatment to generate a plurality of decision signals; And
Described a plurality of decision signals are merged to generate composite data signal.
7. method according to claim 6 is characterized in that described analog-to-digital conversion is carried out with described symbol rate.
8. the method that the signals sampling execution of launching with intrinsic symbol rate by communication channel is regularly recovered is characterized in that, comprising:
Calculate a plurality of channel impulse response estimation signals, each in described a plurality of channel impulse response estimation signals all has specific phase place;
Judge best estimate channel response signal according to described a plurality of estimation channel response signal periods property ground, wherein said best estimate channel response signal description be best suited for the regularly impulse response of the communication channel of recovery algorithms; And
Based on described best estimate channel response Signal Regulation timing recovery algorithms.
9. method according to claim 8, it is characterized in that, described method also comprises by error signal being minimized determine that described best estimate channel impulse response, wherein said error signal are by calculating and being obtained by the difference between the relevant signal of the decision signal of each channel impulse response estimation signal filtering.
CN2007101482317A 2006-08-25 2007-08-24 System and method for electronic dispersion compensation Expired - Fee Related CN101179305B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US84012306P 2006-08-25 2006-08-25
US60/840,123 2006-08-25
US11/837,278 US7961781B2 (en) 2006-08-25 2007-08-10 Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery
US11/837,278 2007-08-10

Publications (2)

Publication Number Publication Date
CN101179305A CN101179305A (en) 2008-05-14
CN101179305B true CN101179305B (en) 2011-09-07

Family

ID=39405417

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2007101482285A Expired - Fee Related CN101179341B (en) 2006-08-25 2007-08-24 Channel identification system and electronic dispersion compensation system
CN2007101482317A Expired - Fee Related CN101179305B (en) 2006-08-25 2007-08-24 System and method for electronic dispersion compensation

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2007101482285A Expired - Fee Related CN101179341B (en) 2006-08-25 2007-08-24 Channel identification system and electronic dispersion compensation system

Country Status (1)

Country Link
CN (2) CN101179341B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8693897B2 (en) * 2011-01-22 2014-04-08 Viasat, Inc. Digital demodulator architecture
US20160365868A1 (en) * 2015-06-12 2016-12-15 Tektronix, Inc. Circulating Resampling Digitizer
CN111786669B (en) * 2019-04-04 2023-09-12 智原微电子(苏州)有限公司 Apparatus for adaptive control of decision feedback equalizer
CN110955179B (en) * 2019-11-28 2022-09-06 电子科技大学 Dual-channel shared clock trigger delay adjusting device based on PCI bus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1006697A2 (en) * 1998-12-02 2000-06-07 Lucent Technologies Inc. Parellel signal processing for equalisation on fibre channels

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707868B1 (en) * 1999-04-12 2004-03-16 Intel Corporation Apparatus for recovering timing of a digital signal for a transceiver
JP2005518111A (en) * 2001-08-10 2005-06-16 エクストリームスペクトラム，インコーポレイテッド Mode controller for signal acquisition and tracking in ultra-wideband communication systems

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1006697A2 (en) * 1998-12-02 2000-06-07 Lucent Technologies Inc. Parellel signal processing for equalisation on fibre channels

Also Published As

Publication number Publication date
CN101179341A (en) 2008-05-14
CN101179305A (en) 2008-05-14
CN101179341B (en) 2011-05-18

Similar Documents

Publication Publication Date Title
KR100912046B1 (en) Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery
US7525462B2 (en) Gain control for interleaved analog-to-digital conversion for electronic dispersion compensation
KR100964940B1 (en) Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery
US8300685B2 (en) Non-linear decision feedback equalizer
US7525470B2 (en) Phase control for interleaved analog-to-digital conversion for electronic dispersion compensation
US20080049825A1 (en) Equalizer with reorder
US8503519B2 (en) Detecting residual ISI components using two data patterns
US9143367B2 (en) Clock and data recovery architecture with adaptive digital phase skew
US8891607B2 (en) Feed forward equalizer tap weight adaptation based on channel estimation
US8767811B2 (en) Back channel adaptation using channel pulse response
US9166774B2 (en) Decoupling bang-bang CDR and DFE
CN103516647A (en) Low-complexity, highly-spectrally-efficient communications
KR101418046B1 (en) Apparatus and method for correcting duty cycle, and receiver employing the same
US20100054318A1 (en) Timing Error Detector and Method Thereof
CN101179305B (en) System and method for electronic dispersion compensation
US20040086275A1 (en) System and method for reducing interference in an optical data stream
US8885699B2 (en) Compensation factor reduction in an unrolled decision feedback equalizer
US9112661B1 (en) Method and apparatus for data reception in high-speed applications
US8149977B2 (en) Recovering data samples
KR20200021300A (en) Receiving device and operation method thereof
CN100382190C (en) Partial response maximum likelihood system possessing branch estimating equipment

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1118974

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1118974

Country of ref document: HK

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110907

Termination date: 20140824

EXPY Termination of patent right or utility model