CN101174590A - Method for manufacturing multi-level non-volatile memory body - Google Patents
Method for manufacturing multi-level non-volatile memory body Download PDFInfo
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- CN101174590A CN101174590A CNA2006101432629A CN200610143262A CN101174590A CN 101174590 A CN101174590 A CN 101174590A CN A2006101432629 A CNA2006101432629 A CN A2006101432629A CN 200610143262 A CN200610143262 A CN 200610143262A CN 101174590 A CN101174590 A CN 101174590A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 149
- 239000004020 conductor Substances 0.000 claims abstract description 147
- 238000007667 floating Methods 0.000 claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000010410 layer Substances 0.000 claims description 332
- 230000003647 oxidation Effects 0.000 claims description 21
- 238000007254 oxidation reaction Methods 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 15
- 230000005641 tunneling Effects 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
- 239000000463 material Substances 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 20
- 239000002184 metal Substances 0.000 description 17
- 229910021332 silicide Inorganic materials 0.000 description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 17
- 239000000377 silicon dioxide Substances 0.000 description 13
- 230000001808 coupling effect Effects 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
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- 239000003795 chemical substances by application Substances 0.000 description 2
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- 238000005260 corrosion Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N hydrogen peroxide Substances OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention relates to a manufacturing method for a multi-step nonvolatile memory, which comprises the following steps: first, a tunnel dielectric layer, a first conductor layer, an inter-gate dielectric layer, a second conductor layer and a top cover layer are formed on a substrate in order. Second, the top cover layer and the second conductor layer are patterned, the inter-gate dielectric layer is exposed, and the patterned second conductor layer forms a plurality of control gates. Third, after a first dielectric layer is formed on the side walls of the control gates, the top cover layer is used as a mask, and the inter-gate dielectric layer and the first conductor layer are partly removed to form a plurality of floating gates. Finally, parts of the floating gates are removed to widen the space between every two adjacent floating gates.
Description
Technical field
The present invention relates to a kind of semiconductor element, and particularly relate to a kind of manufacture method of multi-level non-volatile memory body.
Background technology
Non-volatile memory component can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Typical non-volatile memory component generally is (Stacked-Gate) structure that is designed to have stacked gate, comprising floating grid made from doped polycrystalline silicon (Floating Gate) and control grid (Control Gate).Floating grid is between control grid and substrate, and be in floating state, be not connected with any circuit, control grid then join with word line (Word Line), comprise in addition dielectric layer between tunnel oxide (Tunneling Oxide) and grid (Inter-Gate Dielectric Layer) lay respectively between substrate and the floating grid and floating grid and control grid between.
On the other hand, at present the flash array that more often uses of industry comprises NOR gate (NOR) type array structure and NAND gate (NAND) type array structure.Because the non-volatile memory structure of NAND gate (NAND) type array is that each memory cell is serially connected, its integration and area utilization are good than the non-volatility memorizer of NOR gate (NOR) type array, have been widely used in the multiple electronic product.
Yet, when the memory cell in the NAND type non-volatility memorizer is used as multi-level cell memory, in order to make NAND type non-volatility memorizer have preferred element reliability, what then need to make memory cell is used to that to differentiate the start voltage distribution of each data mode less.Yet start voltage distribution (threshold voltage distribution) can be subjected to coupling effect (coupling effect) influence of the memory cell in the non-volatility memorizer.For instance, in NAND type non-volatility memorizer, on bit line direction, the coupling effect between floating grid-floating grid; On word-line direction, the coupling effect between floating grid-floating grid; On bit line diagonal angle direction, the coupling effect between floating grid-floating grid; And on bit line direction, the coupling effect between control grid-floating grid etc. all can have influence on start voltage and distribute.
For fear of the influence that reduces above-mentioned coupling effect (coupling effect), can use advanced low-k materials to replace silicon nitride and make the clearance wall of memory cell, to be reduced on the bit line direction coupling effect between floating grid-floating grid.Perhaps on component isolation structure, form depression, the some of control grid is inserted between the adjacent floating grid, to reduce on the word-line direction coupling effect between floating grid-floating grid.And how industry still reduces the method for above-mentioned coupling effect in research at present, reaches the purpose of the reliability that promotes multi-level cell memory.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of multi-level non-volatile memory body is being provided, and can improve the reliability of element.
A further object of the present invention provides a kind of manufacture method of multi-level non-volatile memory body, and its technology is simple, and can be reduced on the bit line direction coupling effect between floating grid-floating grid.
The invention provides a kind of manufacture method of multi-level non-volatile memory body, comprise the following steps.At first, in forming dielectric layer, second conductor layer and cap layer between tunneling dielectric layer, first conductor layer, grid in the substrate in regular turn.The patterning cap layer and second conductor layer, and expose dielectric layer between grid, the second patterned conductor layer forms a plurality of control grids.After the sidewall of control grid forms first dielectric layer, be mask with the cap layer, remove dielectric layer between the part grid, first conductor layer, to form a plurality of floating grids.Then, remove the part floating grid, make the spacing between adjacent two floating grids become big.After the sidewall of control grid and floating grid forms insulating gap wall, in substrate, form source/drain regions.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms first dielectric layer in the sidewall of control grid comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the method that wherein removes the part floating grid comprises wet etching.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the sidewall that also is included in floating grid forms second dielectric layer.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms second dielectric layer in the sidewall of floating grid comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in and form interlayer insulating film in the substrate.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein have a plurality of air gaps (air gap) in the interlayer insulating film, between adjacent two floating grids.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the sidewall that also is included in control grid and floating grid forms insulating gap wall.
The invention provides a kind of manufacture method of multi-level non-volatile memory body, comprise the following steps.At first, provide substrate, this substrate can be divided into memory cell areas and periphery circuit region, be formed with tunneling dielectric layer on the memory cell areas, and periphery circuit region is formed with gate dielectric layer.In forming in regular turn in the substrate between first conductor layer and grid behind the dielectric layer, remove dielectric layer between the grid on the periphery circuit region.Then, form second conductor layer and cap layer in substrate, second conductor layer on periphery circuit region is electrically connected with first conductor layer.Then, the cap layer of patterning memory cell areas and second conductor layer, forming a plurality of control grids in memory cell areas, and the cap layer of patterning periphery circuit region, second conductor layer and first conductor layer are to form grid structure.Afterwards, form first dielectric layer in the sidewall of control grid and the sidewall of grid structure.With the cap layer in the memory cell areas is mask, removes dielectric layer between the part grid, first conductor layer, to form a plurality of floating grids.Then, remove the part floating grid, make the spacing between adjacent two floating grids become big.Form first insulating gap wall in the control grid of memory cell areas and the sidewall of floating grid, and form second insulating gap wall in the sidewall of the grid structure of periphery circuit region.In the substrate of memory cell areas, form first source/drain regions, and in the substrate of periphery circuit region, form second source/drain regions.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms first dielectric layer in the sidewall of control grid comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the method that wherein removes the part floating grid comprises wet etching.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the sidewall that also is included in floating grid forms second dielectric layer.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms second dielectric layer in the sidewall of floating grid comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in and form interlayer insulating film in the substrate.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein have a plurality of air gaps (air gap) in the interlayer insulating film, between adjacent two floating grids.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in the sidewall of the stack architecture that constitutes by control grid and floating grid and the sidewall of grid structure and form insulating gap wall.
The invention provides a kind of manufacture method of multi-level non-volatile memory body, comprise the following steps.At first, provide substrate, this substrate can be divided into memory cell areas and periphery circuit region, be formed with tunneling dielectric layer on the memory cell areas, and periphery circuit region is formed with gate dielectric layer.In forming dielectric layer between first conductor layer and grid in the substrate in regular turn, and dielectric layer forms opening between the grid on the periphery circuit region.Form second conductor layer and cap layer in substrate, second conductor layer on periphery circuit region is electrically connected with first conductor layer via opening.Then, the patterning cap layer and second conductor layer forming a plurality of control grids in memory cell areas, and form stack architecture in periphery circuit region, and opening are positioned at stack architecture at least.Form first dielectric layer in the sidewall of control grid and the sidewall of stack architecture.With the cap layer is mask, removes dielectric layer between the part grid, first conductor layer, forming a plurality of floating grids in memory cell areas, and forms the grid structure that comprises stack architecture in periphery circuit region.Afterwards, remove the part floating grid, make the spacing between adjacent two floating grids become big.Form first insulating gap wall in the control grid of memory cell areas and the sidewall of floating grid, and form second insulating gap wall in the sidewall of the grid structure of periphery circuit region.In the substrate of memory cell areas, form first source/drain regions, and in the substrate of periphery circuit region, form second source/drain regions.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms first dielectric layer in the sidewall of control sidewall of grid and stack architecture comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the method that wherein removes the part floating grid comprises wet etching.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the sidewall that also is included in floating grid forms second dielectric layer.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the method that forms second dielectric layer in the sidewall of floating grid comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in and form interlayer insulating film in the substrate.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein have a plurality of air gaps (air gap) in the interlayer insulating film, between adjacent two floating grids.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in the sidewall of the stack architecture that constitutes by control grid and floating grid and the sidewall of grid structure and form insulating gap wall.
The manufacture method of multi-level non-volatile memory body of the present invention owing to form dielectric layer at the control gate lateral wall, is therefore removing the part floating grid so that the spacing between the adjacent floating grid when becoming big, can be avoided controlling grid and be removed.So, can under the situation of keeping the control grid length, dwindle floating grid length, so that the spacing d between adjacent two floating grids becomes big.By making the spacing d between adjacent two floating grids become big, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
And, the manufacture method of multi-level non-volatile memory body of the present invention, because grid structure sidewall in periphery circuit region forms dielectric layer, therefore removing the part floating grid so that the spacing of adjacent floating grid when becoming big, can avoid the grid structure in the periphery circuit region to be removed.So, under the situation of the length of grid structure that can be in keeping periphery circuit region, dwindle floating grid length, so that the spacing d between adjacent two floating grids becomes big.By making the spacing d between adjacent two floating grids become big, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
In addition, the manufacture method of multi-level non-volatile memory body of the present invention forms the air gap in the interlayer insulating film between floating grid.By forming the air gap, can further dwindle the interference of the floating grid of adjacent memory unit on the bit line direction.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 F is the flow process generalized section according to the manufacture method of the multi-level non-volatile memory body that one embodiment of the invention illustrated.
Fig. 2 is the flow process generalized section according to the manufacture method of the multi-level non-volatile memory body that another embodiment of the present invention illustrated.
Fig. 3 A to Fig. 3 F is the flow process generalized section according to the manufacture method of the multi-level non-volatile memory body that another embodiment of the present invention illustrated.
Fig. 4 is the flow process generalized section of the manufacture method of the multi-level non-volatile memory body that illustrated according to an embodiment more of the present invention.
The simple symbol explanation
100: substrate
102: memory cell areas
104: periphery circuit region
106: tunneling dielectric layer
108: gate dielectric layer
110,110a, 110b, 110c, 110d, 118,118a, 118b: conductor layer
112: dielectric layer between grid
114,114a: mask layer
112a, 116: opening
120,120a, 120b: metal silicide layer
122,122a, 122b: cap layer
124: stack architecture
125,125a: grid structure
126,126a, 128: dielectric layer
130: insulating gap wall
132,134: doped region
136: interlayer insulating film
138: the air gap
Embodiment
Figure 1A to Fig. 1 F is the manufacturing process profile according to a kind of multi-level non-volatile memory body of one embodiment of the present invention.
Please refer to Figure 1A, substrate 100 at first is provided, substrate 100 for example is a silicon base.This substrate 100 for example can be divided into memory cell areas 102 and periphery circuit region 104.
Then, in the substrate 100 of memory cell areas 102, form one deck tunneling dielectric layer 106.In the substrate 100 of periphery circuit region 104, form one deck gate dielectric layer 108.The material of tunneling dielectric layer 106, gate dielectric layer 108 for example is a silica.And according to the characteristic of element, the thickness of tunneling dielectric layer 106, gate dielectric layer 108 is also inequality.Wherein, can adopt any existing method in memory cell areas 102 tunneling dielectric layer 106 different, the method for gate dielectric layer 108 with formation thickness in the periphery circuit region 104.
In whole substrate 100, form one deck conductor layer 110, the material of conductor layer 110 for example is a doped polycrystalline silicon, the formation method of this conductor layer 110 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it; Perhaps adopt the mode of injecting alloy when participating in the cintest to utilize chemical vapour deposition technique and form it.
Please refer to Figure 1B, the conductor layer 110 on the patterning memory cell areas 102, and form the conductor layer 110a that is the strip layout.The method of patterning conductor layer 110 for example is the photoengraving carving technology.
Then, in forming dielectric layer 112 between grid in the substrate 100, the material of dielectric layer 112 for example is silica/silicon nitride/silicon nitride between these grid, the formation method of dielectric layer 112 for example is earlier with silicon oxide layer at the bottom of thermal oxidation method formation one deck between these grid, then, utilize chemical vapour deposition technique to form one deck silicon nitride layer again, on silicon nitride layer, form the top silicon oxide layer thereafter again.Certainly, the material of dielectric layer 112 also can be silica, silica/silicon nitride or other dielectric material between grid.
Then, form one deck patterned mask layer 114 in substrate 100, this patterned mask layer 114 has opening 116 on periphery circuit region 104.The position at these opening 116 places is the zone of follow-up formation grid structure.The material of patterned mask layer 114 for example is a photo anti-corrosion agent material, and its formation method for example is prior to after forming one deck photoresist layer in the substrate, and this photoresist layer is exposed, develops and forms it.
Please refer to Fig. 1 C, afterwards, remove dielectric layer 112 between the grid that are not patterned mask layer 114 coverings, to form opening 112a in the dielectric layer between grid 112.The method that removes dielectric layer 112 between grid comprises the dry-etching method, for example is reactive ion-etching.
Remove patterned mask layer 114.The method that removes patterned mask layer 114 for example is first with after the oxygen plasma ashing patterned mask layer 114, carries out wet-cleaned technology again.After removing patterned mask layer 114, in substrate 100, form another layer conductor layer 118.The material of conductor layer 118 for example is a doped polycrystalline silicon.The formation method of conductor layer 118 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it; Perhaps adopt the mode of injecting alloy when participating in the cintest to utilize chemical vapour deposition technique and form it.Certainly, the material of conductor layer 118 also can be other conductor material.Then, on conductor layer 118, form layer of metal silicide layer 120.The formation method of metal silicide layer 120 for example is a chemical vapour deposition technique.Conductor layer 118 is electrically connected with conductor layer 110 via opening 112a in periphery circuit region 104.Afterwards, form one deck cap layer 122 in substrate 100, the material of cap layer 122 for example is a silica, and its formation method for example is a chemical vapour deposition technique.
Please refer to Fig. 1 D, patterning cap layer 122, metal silicide layer 120, conductor layer 118, forming cap layer 122a, metal silicide layer 120a, conductor layer 118a, and form the stack architecture 124 that constitutes by cap layer 122b, metal silicide layer 120b, conductor layer 118b in periphery circuit region 104 in memory cell areas 102.In memory cell areas 102, after conductor layer 118 is patterned, form a plurality of strip conductor layer 118a that are arranged in parallel, this conductor layer 118a is the control grid as memory cell.In periphery circuit region 104, opening 112a is positioned at stack architecture 124 at least.
Then, on the sidewall of conductor layer 118a and conductor layer 118b, form dielectric layer 126.The material of dielectric layer 126 for example is a silica, and its formation method comprises thermal oxidation method, for example rapid thermal oxidation method (Rapid thermal oxide).
Please refer to Fig. 1 E, with cap layer 122a and cap layer 122b is mask, remove dielectric layer 112 between the part grid, conductor layer 110, conductor layer 110a, and form the conductor layer 110b that is isolated from each other and form conductor layer 110c in periphery circuit region 104 in memory cell areas 102.Conductor layer 110b in memory cell areas 102 is the floating grid as memory cell.Conductor layer 110c in periphery circuit region 104 then is as transistorized grid with conductor layer 118b, 120b.Conductor layer 110c, conductor layer 118b, metal silicide layer 120b and cap layer 122b constitute grid structure 125.Dielectric layer 112, conductor layer 118a (control grid), metal silicide layer 120a and cap layer 122a constitute memory cell between conductor layer 110b (floating grid), grid.
Then, remove segment conductor layer 110b (floating grid), make the spacing d between the adjacent two conductor layer 110b become big.The method that removes segment conductor layer 110b (floating grid) for example is a wet etching, for example is the aqueous solution (APM, NH with the ammoniacal liquor-hydrogen peroxide of high temperature (about 65 ℃)
4OH/H
2O
2/ H
2O) as etchant.In this step, the segment conductor layer 110c in periphery circuit region 104 also can be removed.
Please refer to Fig. 1 F, on the sidewall of conductor layer 110b and conductor layer 110c, form dielectric layer 128.The material of dielectric layer 128 for example is a silica, and its formation method comprises thermal oxidation method, for example rapid thermal oxidation method (Rapid thermal oxide).Then, form insulating gap wall 130 in cap layer 122a, metal silicide layer 120a, conductor layer 118a (control grid) with the stack layer of conductor layer 110b (floating grid) formation and the sidewall of grid structure 125.The material of insulating gap wall 130 for example is a silicon nitride.The formation method of insulating gap wall 130 for example is after earlier forming one deck insulation material layer with chemical vapour deposition technique, carries out anisotropic etching process and forms it.
Afterwards, form doped region 132 (source/drain regions), form doped region 134 (source/drain regions) in periphery circuit region 104 in memory cell areas 102.In memory cell areas 102, doped region 132 (source/drain regions) is arranged in memory cell (stack layer) substrate on two sides 100.In periphery circuit region 104, doped region 134 (source/drain regions) is arranged in grid structure 125 substrate on two sides 100.The formation method of doped region 132 (source/drain regions) and doped region 134 (source/drain regions) for example is an ion implantation.The follow-up technology of finishing non-volatility memorizer is known by those skilled in the art, does not repeat them here.
In the manufacture method of multi-level non-volatile memory body of the present invention; owing to form dielectric layer 126 at conductor layer 118a (control grid) sidewall; with protection conductor layer 118a (control grid); remove segment conductor layer 110b (floating grid) then; therefore; can keep the length of conductor layer 118a (control grid), dwindle the length of conductor layer 110b (floating grid), and make the spacing d between the adjacent two conductor layer 110b (floating grid) become big.So, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
And, the manufacture method of multi-level non-volatile memory body of the present invention, can with general CMOS (Complementary Metal Oxide Semiconductor) process integration together.
Fig. 2 illustrate is the manufacturing process profile of a kind of multi-level non-volatile memory body of another embodiment of the present invention.Fig. 2 is connected in Fig. 1 E, and member identical person with Figure 1A to 1E give identical symbol, and omits its explanation.
As shown in Figure 2, after forming dielectric layer 128 on the sidewall of conductor layer 110b and conductor layer 110c, form doped region 132 (source/drain regions), form doped region 134 (source/drain regions) in periphery circuit region 104 in memory cell areas 102.Then, in substrate 100, form interlayer insulating film 136.The material of interlayer insulating film 136 for example is phosphorosilicate glass, boron-phosphorosilicate glass etc.The formation method of interlayer insulating film 136 for example is a chemical vapour deposition technique.Because it is big that the spacing d between the adjacent two conductor layer 110b (floating grid) becomes, can form air gap 138 in the interlayer insulating film 136 between two conductor layer 110b (floating grid).This air gap 138 can further dwindle the interference of the floating grid of adjacent memory unit on the bit line direction.
Fig. 3 A to Fig. 3 F is the manufacturing process profile according to a kind of multi-level non-volatile memory body of the another preferred embodiment of the present invention.In Fig. 3 A to Fig. 3 F, the identical person with Figure 1A to Fig. 1 F of member gives identical label, and omits its explanation.
Please refer to Fig. 3 A, substrate 100 at first is provided.This substrate 100 for example can be divided into memory cell areas 102 and periphery circuit region 104.
Then, in the substrate 100 of memory cell areas 102, form one deck tunneling dielectric layer 106.In the substrate 100 of periphery circuit region 104, form one deck gate dielectric layer 108.Form one deck conductor layer 110 in whole substrate 100, the material of conductor layer 110 for example is a doped polycrystalline silicon.
Please refer to Fig. 3 B, the conductor layer 110 on the patterning memory cell areas 102 makes its layout and form conductor layer 110a into strips.The method of patterning conductor layer 110 for example is the photoengraving carving technology.
Then, in forming dielectric layer 112 between grid in the substrate 100, the material of dielectric layer 112 for example is silica/silicon nitride/silicon nitride between these grid.Certainly, the material of dielectric layer 112 also can be silica, silica/silicon nitride or other dielectric material between grid.
Then, form one deck patterned mask layer 114a in substrate 100, this patterned mask layer 114a covers memory cell areas 102 and exposes whole periphery circuit region 104.The material of patterned mask layer 114a for example is a photo anti-corrosion agent material.
Please refer to Fig. 3 C, remove dielectric layer 112 between the grid that are not patterned mask layer 114a covering, with the conductor layer 110 of exposed perimeter circuit region 104.
Then, remove patterned mask layer 114a, and in substrate 100, form another layer conductor layer 118.The material of conductor layer 118 for example is a doped polycrystalline silicon.Certainly, the material of conductor layer 118 also can be other conductor material.Then, on conductor layer 118, form layer of metal silicide layer 120.The formation method of metal silicide layer 120 for example is a chemical vapour deposition technique.Conductor layer 118 is electrically connected with conductor layer 110 fully in periphery circuit region 104.Afterwards, form one deck cap layer 122 in substrate 100, the material of cap layer 122 for example is a silica.
Please refer to Fig. 3 D, the cap layer 122 of patterning memory cell areas 102, metal silicide layer 120, conductor layer 118 are to form cap layer 122a, metal silicide layer 120a, conductor layer 118a; And the cap layer 122 of patterning periphery circuit region 104, metal silicide layer 120, conductor layer 118, conductor layer 110, form the grid structure 125a that constitutes by cap layer 122b, metal silicide layer 120b, conductor layer 118b, conductor layer 110d.In memory cell areas 102, after conductor layer 118 is patterned, form a plurality of strip conductor layer 118a that are arranged in parallel, this conductor layer 118a is the control grid as memory cell.
Then, on the sidewall of conductor layer 118a, form dielectric layer 126, and form dielectric layer 126a in the sidewall of conductor layer 110d and conductor layer 118b.The material of dielectric layer 126, dielectric layer 126a for example is a silica, and its formation method comprises thermal oxidation method, for example rapid thermal oxidation method (Rapid thermal oxide).
Please refer to Fig. 3 E, is mask with cap layer 122a, removes dielectric layer 112 between the part grid, conductor layer 110a, and forms the conductor layer 110b that is isolated from each other in memory cell areas 102.Conductor layer 110b in memory cell areas 102 is the floating grid as memory cell.Dielectric layer 112, conductor layer 118a (control grid), metal silicide layer 120a and cap layer 122a constitute memory cell between conductor layer 110b (floating grid), grid.
Then, remove segment conductor layer 110b (floating grid), make the spacing d between the adjacent two conductor layer 110b become big.The method that removes segment conductor layer 110b (floating grid) for example is a wet etching, for example is the aqueous solution (APM, NH with the ammoniacal liquor-hydrogen peroxide of high temperature (about 65 ℃)
4OH/H
2O
2/ H
2O) as etchant.In this step,, therefore can not be removed because conductor layer 110d in periphery circuit region 104 and conductor layer 118b are covered by dielectric layer 126a.So, just can keep the length of the grid structure 125a of periphery circuit region.
Please refer to Fig. 3 F, on the sidewall of conductor layer 110b, form dielectric layer 128a.The material of dielectric layer 128a for example is a silica, and its formation method comprises thermal oxidation method, for example rapid thermal oxidation method (Rapidthermal oxide).Then, form insulating gap wall 125 in cap layer 122a, metal silicide layer 120a, conductor layer 118a (control grid) with the stack layer of conductor layer 110b (floating grid) formation and the sidewall of grid structure 125a.
Afterwards, form doped region 132 (source/drain regions), form doped region 134 (source/drain regions) in periphery circuit region 104 in memory cell areas 102.In memory cell areas 102, doped region 132 (source/drain regions) is arranged in memory cell (stack layer) substrate on two sides 100.Doped region 134 (source/drain regions) is arranged in grid structure 125 substrate on two sides 100 in periphery circuit region 104.The formation method of doped region 132 (source/drain regions) and doped region 134 (source/drain regions) for example is an ion implantation.The follow-up technology of finishing non-volatility memorizer is known by those skilled in the art, does not repeat them here.
In the manufacture method of multi-level non-volatile memory body of the present invention; owing to form dielectric layer 126 at conductor layer 118a (control grid) sidewall; with protection conductor layer 118a (control grid); remove segment conductor layer 110b (floating grid) then; therefore; can keep the length of conductor layer 118a (control grid), dwindle the length of conductor layer 110b (floating grid) so that the spacing d between the adjacent two conductor layer 110b (floating grid) becomes big.So, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
And, the manufacture method of multi-level non-volatile memory body of the present invention, because conductor layer 110d and conductor layer 118b in the periphery circuit region 104 are covered by dielectric layer 126a, therefore spacing d between the adjacent two conductor layer 110b (floating grid) is become in the big step, conductor layer 110d and conductor layer 118b can not be removed.So, just can keep the length of the grid structure 125a of periphery circuit region.
In addition, the manufacture method of multi-level non-volatile memory body of the present invention, can with general CMOS (Complementary Metal Oxide Semiconductor) process integration together.
Fig. 4 illustrate is the manufacturing process profile of a kind of multi-level non-volatile memory body of another embodiment of the present invention.Fig. 4 is connected in Fig. 3 E, and member identical person with Fig. 3 A to 3E give identical symbol, and omits its explanation.
As shown in Figure 4, after forming dielectric layer 128a on the sidewall of conductor layer 110b, form doped region 132, form doped region 134 in periphery circuit region 104 in memory cell areas 102.Then, in substrate 100, form interlayer insulating film 136.Because it is big that the spacing d between the adjacent two conductor layer 110b (floating grid) becomes, can form air gap 138 in the interlayer insulating film 136 between two conductor layer 110b (floating grid).This air gap 138 can further dwindle the interference of the floating grid of adjacent memory unit on the bit line direction.
In sum, the manufacture method of multi-level non-volatile memory body of the present invention owing to form dielectric layer at the control gate lateral wall, is therefore removing the part floating grid so that the spacing between the adjacent floating grid when becoming big, can be avoided controlling grid and be removed.So, can under the situation of keeping the control grid length, dwindle floating grid length, so that the spacing d between adjacent two floating grids becomes big.By making the spacing d between adjacent two floating grids become big, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
And, the manufacture method of multi-level non-volatile memory body of the present invention, because grid structure sidewall in periphery circuit region forms dielectric layer, therefore removing the part floating grid so that the spacing of adjacent floating grid when becoming big, can avoid the grid structure in the periphery circuit region to be removed.So, under the situation of the length of grid structure that can be in keeping periphery circuit region, dwindle floating grid length, so that the spacing d between adjacent two floating grids becomes big.By making the spacing d between adjacent two floating grids become big, just can avoid the interference of the floating grid of adjacent memory unit on the bit line direction, and can improve the reliability of multi-level non-volatile memory body of the present invention.
In addition, the manufacture method of multi-level non-volatile memory body of the present invention forms the air gap in the interlayer insulating film between floating grid.By this air gap, can further dwindle the interference of the floating grid of adjacent memory unit on the bit line direction.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (24)
1. the manufacture method of a multi-level non-volatile memory body comprises:
In forming dielectric layer between tunneling dielectric layer, first conductor layer and grid, second conductor layer and cap layer in the substrate in regular turn;
This cap layer of patterning and this second conductor layer, and expose dielectric layer between these grid, patterned this second conductor layer forms a plurality of control grids;
Sidewall in those control grids forms first dielectric layer;
With this cap layer is mask, removes dielectric layer, this first conductor layer between these grid of part, to form a plurality of floating grids;
Remove those floating grids of part, make the spacing between adjacent two those floating grids become big;
Sidewall in those control grids and those floating grids forms insulating gap wall; And
In this substrate, form source/drain regions.
2. the manufacture method of multi-level non-volatile memory body as claimed in claim 1 wherein comprises thermal oxidation method in the method that sidewalls of those control grids form this first dielectric layer.
3. the manufacture method of multi-level non-volatile memory body as claimed in claim 1, the method that wherein removes those floating grids of part comprises wet etching.
4. the manufacture method of multi-level non-volatile memory body as claimed in claim 1, the sidewall that also is included in those floating grids forms second dielectric layer.
5. the manufacture method of multi-level non-volatile memory body as claimed in claim 1 wherein comprises thermal oxidation method in the method that the sidewall of those floating grids forms this second dielectric layer.
6. the manufacture method of multi-level non-volatile memory body as claimed in claim 1 also is included in this substrate and forms interlayer insulating film.
7. the manufacture method of multi-level non-volatile memory body as claimed in claim 6 wherein has a plurality of air gaps in this interlayer insulating film, between adjacent two those floating grids.
8. the manufacture method of multi-level non-volatile memory body as claimed in claim 1 also is included in those sidewalls of controlling grids and those floating grids and forms insulating gap wall.
9. the manufacture method of a multi-level non-volatile memory body comprises:
Substrate is provided, and this substrate can be divided into memory cell areas and periphery circuit region, is formed with tunneling dielectric layer on this memory cell areas and this periphery circuit region is formed with gate dielectric layer;
In forming dielectric layer between first conductor layer and grid in this substrate in regular turn;
Remove dielectric layer between these grid on this periphery circuit region;
Form second conductor layer and cap layer in this substrate, this second conductor layer on this periphery circuit region is electrically connected with this first conductor layer;
This cap layer of this memory cell areas of patterning and this second conductor layer, forming a plurality of control grids in this memory cell areas, and this cap layer of this periphery circuit region of patterning, this second conductor layer and this first conductor layer are to form grid structure;
Form first dielectric layer in the sidewall of those control grids and the sidewall of this grid structure;
With this cap layer in this memory cell areas is mask, removes dielectric layer, this first conductor layer between these grid of part, to form a plurality of floating grids;
Remove those floating grids of part, make the spacing between adjacent two those floating grids become big;
Sidewalls in those control grids and those floating grids of this memory cell areas form first insulating gap wall, and form second insulating gap wall in the sidewall of this grid structure of this periphery circuit region; And
In this substrate of this memory cell areas, form first source/drain regions, and in this substrate of this periphery circuit region, form second source/drain regions.
10. the manufacture method of multi-level non-volatile memory body as claimed in claim 9 wherein comprises thermal oxidation method in the method that sidewalls of those control grids form this first dielectric layer.
11. the manufacture method of multi-level non-volatile memory body as claimed in claim 9, the method that wherein removes those floating grids of part comprises wet etching.
12. the manufacture method of multi-level non-volatile memory body as claimed in claim 9, the sidewall that also is included in those floating grids forms second dielectric layer.
13. the manufacture method of multi-level non-volatile memory body as claimed in claim 9 wherein comprises thermal oxidation method in the method that the sidewall of those floating grids forms this second dielectric layer.
14. the manufacture method of multi-level non-volatile memory body as claimed in claim 9 also is included in this substrate and forms interlayer insulating film.
15. the manufacture method of multi-level non-volatile memory body as claimed in claim 14 wherein has a plurality of air gaps in this interlayer insulating film, between adjacent two those floating grids.
16. the manufacture method of multi-level non-volatile memory body as claimed in claim 9 also is included in the sidewall of the stack architecture that is made of those control grids and those floating grids and the sidewall of this grid structure and forms insulating gap wall.
17. the manufacture method of a multi-level non-volatile memory body comprises:
Substrate is provided, and this substrate can be divided into memory cell areas and periphery circuit region, is formed with tunneling dielectric layer on this memory cell areas and this periphery circuit region is formed with gate dielectric layer;
In forming dielectric layer between first conductor layer and grid in this substrate in regular turn;
Dielectric layer forms opening between these grid on this periphery circuit region;
Form second conductor layer and a cap layer in this substrate, this second conductor layer on this periphery circuit region is electrically connected with this first conductor layer via this opening;
This cap layer of patterning and this second conductor layer forming a plurality of control grids in this memory cell areas, and form stack architecture in this periphery circuit region, and this opening are positioned at this stack architecture at least;
Form first dielectric layer in the sidewall of those control grids and the sidewall of this stack architecture;
With this cap layer is mask, removes dielectric layer, this first conductor layer between these grid of part, forming a plurality of floating grids in this memory cell areas, and forms the grid structure that comprises this stack architecture in this periphery circuit region;
Remove those floating grids of part, make the spacing between adjacent two those floating grids become big;
Sidewalls in those control grids and those floating grids of this memory cell areas form first insulating gap wall, and form second insulating gap wall in the sidewall of this stack architecture of this periphery circuit region; And
In this substrate of this memory cell areas, form first source/drain regions, and in this substrate of this periphery circuit region, form second source/drain regions.
18. the manufacture method of multi-level non-volatile memory body as claimed in claim 17 wherein comprises thermal oxidation method in the sidewall of those control grids and the method that this stack architecture sidewall forms this first dielectric layer.
19. the manufacture method of multi-level non-volatile memory body as claimed in claim 17, the method that wherein removes those floating grids of part comprises wet etching.
20. the manufacture method of multi-level non-volatile memory body as claimed in claim 17, the sidewall that also is included in those floating grids forms second dielectric layer.
21. the manufacture method of multi-level non-volatile memory body as claimed in claim 20 wherein comprises thermal oxidation method in the method that the sidewall of those floating grids forms this second dielectric layer.
22. the manufacture method of multi-level non-volatile memory body as claimed in claim 17 also is included in this substrate and forms interbedded insulating layer.
23. the manufacture method of multi-level non-volatile memory body as claimed in claim 22 wherein has a plurality of air gaps in this interlayer insulating film, between adjacent two those floating grids.
24. the manufacture method of multi-level non-volatile memory body as claimed in claim 17 also is included in the sidewall of the stack architecture that is made of those control grids and those floating grids and the sidewall of this grid structure and forms insulating gap wall.
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| CNA2006101432629A CN101174590A (en) | 2006-11-01 | 2006-11-01 | Method for manufacturing multi-level non-volatile memory body |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102544015A (en) * | 2010-12-22 | 2012-07-04 | 力晶科技股份有限公司 | Nonvolatile memory and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102544015A (en) * | 2010-12-22 | 2012-07-04 | 力晶科技股份有限公司 | Nonvolatile memory and method of manufacturing the same |
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