CN101162958B

CN101162958B - Method of sampling signal of locating frame head in SDH transmission system

Info

Publication number: CN101162958B
Application number: CN200610141143XA
Authority: CN
Inventors: 尚军辉
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2006-10-11
Filing date: 2006-10-11
Publication date: 2012-04-18
Anticipated expiration: 2026-10-11
Also published as: CN101162958A

Abstract

The invention discloses a sampling method of aligning frame header signals in SDH transmission system. The method comprises: step 1, the system reference frame header signals sent by clock board are received and the reference frame header signals are processed with two divided-frequency processing. Step 2, the signals processed with the two divided-frequency processing are sampled by system clock. Step 3, the signals obtained from the step 2 are processed with twice clock cycle delay sampling. Step 4, the signals obtained from the twice delay sampling of the step 3 are processed with exclusive or processing and then the amended aligning frame header signals are obtained. In addition to stability, the invention realizes the alignment of the reference frame header signals and the clock. By the mode of the frame header processed by chip on cross board, the invention lightens the pressure of the strict condition for sending out system frame header on the clock board in the SDH system, solving the problems of the cost brought by originally adding the reference frame header of hardware circuit correction system on the clock board and bad effects, etc. effectively, thereby reducing the condition restriction from the SDH system to the system frame header sent out by the clock board.

Description

The method of sampling of signal of locating frame head in a kind of SDH transmission system

Technical field

The present invention relates in the communication field method of sampling of locating frame head in the SDH transmission system, be specifically related to a kind of long and cause that the method for sampling of distortion takes place locating frame head in transmission range.

Background technology

In the SDH transmission system; Clock board is responsible for seeing periodic system reference header signal and clock signal of system off to cross board; Cross board utilizes system clock to catch and this system's frame head of sampling; Be used as the alignment mark that frame data stream in the cross board is handled, cross board receives alignment situation and the working stability quality that has determined the output of cross board data flow with reference to the frame head signal quality, if the system reference header signal that cross board receives problem such as disturb to distort (broaden or narrow down) between long or plate because of transmission range can not the periodicity steady change; So just possibly cause that data can't be alignd on the cross board; Thereby make the data confusion reigned, system data produces mistake, and whole system just need reset again.Therefore in the SDH system works, the header signal that system receives cross board has very strict requirement.

Yet in real work; System receives the living distortion of system-frame hair because factors such as the fluctuation of ambient temperature, voltage and transmission range make usually; Thereby cause that clock can't sample this header signal on the cross board, data can't positioned in alignment, final result data cross mistake.

Number of patent application be " CN200310103578.1's " " method of SDH data transmission system frame head dithering process "; This application mainly is to surpass the situation of a clock cycle to shake before and after system's frame head to handle; Can not distortion take place for frame head itself handles; If on clock board, header signal is adopted hardware handles by force; Then need comparatively strict specification requirement be arranged, increase system cost so undoubtedly, also increase the complexity of whole system design simultaneously clock board.

Summary of the invention

In order to overcome the problem that exists in the prior art, the present invention in the design of cross chips with regard to the problem of resolution system with reference to the frame head distortion, thereby reduce the condition restriction of system's frame head that the SDH system sees off clock board.

Particularly; The present invention is the problem that distorts because of the influence of transmission range and operational environment with reference to header signal in order to solve in the prior art; To revising with reference to frame head; To guarantee that alignment of data is effectively handled on the cross board, eliminate situation about receiving on the cross board with reference to the frame head signal distortion.

In order to realize the foregoing invention purpose, the present invention specifically is achieved in that

The method of sampling of signal of locating frame head is characterized in that in a kind of SDH transmission system, comprises the steps:

The system reference header signal that step 1, receive clock plate are sent here is handled carry out two divided-frequency with reference to header signal;

Step 2, the signal after two divided-frequency is handled is sampled with system clock;

Step 3, the signal that step 2 is obtained carry out 2 clock cycle delay samplings;

Step 4, the signal that twice delay sampling of step 3 obtained carry out the XOR processing, obtain revised signal of locating frame head.

Said step 1,

Utilize the rising edge sampling of system reference header signal, carry out two divided-frequency and handle.

Said step 2,

Signal after the rising edge that utilizes system clock is handled two divided-frequency is sampled, and obtains the signal stable with clock synchronization.

The present invention has realized a kind of sampling processing to the navigation system frame head; Through frequency division processing and system clock double sampling with reference to header signal are postponed; The reference header signal that obtains can align with clock and have stability; Solution can't be caused the situation of cisco unity malfunction by the correct sampling of system clock because of deterioration with reference to header signal; Through in the processing aspect the chip; Can make the SDH transmission system at work, not need the width of system's frame head to be provided strict requirement, realize the low-cost purpose of revising locating frame head effectively at the clock board place; Alleviate the pressure of seeing system's frame head stringent condition in the SDH system on the clock board off through the mode of handling frame head at the intersection chip on board simultaneously, solved original problems such as next cost of hardware circuit update the system reference frame headband and weak effect of on clock board, adding effectively.

Description of drawings

Fig. 1 is a header signal sampling processing flow chart;

Fig. 2 is a header signal sampling sketch map.

Embodiment

Below in conjunction with accompanying drawing the practical implementation of the method for the invention is done further to describe in detail:

Shown in accompanying drawing 2; Clock board has periodic system reference header signal (FP_IN) and clock signal of system (SYS_CLK) giving cross board; Clock signal of system has good stability to cross board; The system reference header signal (FP_IN) that cross board receive clock plate is sent here; Because this frame head maybe narrower (system clock SYS_CLK can't successfully sample) or too wide (the double successfully sampling of system clock), does not therefore have direct using system clock that header signal is sampled, and uses the rising edge sampling of this system reference frame head; Carry out two divided-frequency and handle, can guarantee to sample smoothly the 2 fractional frequency signal FP_2P that header signal obtains the system reference frame head like this.

Utilizing the signal FP_2P of system reference frame head rising edge sampling is that the homologous ray header signal itself has phase synchronism; There is not definite phase relation with the system clock that will sample; The header signal that obtains must keep synchronism with clock; Therefore utilize the system clock rising edge that signal FP_2P is sampled again and obtain the FP_S signal stable, guarantee that this signal has stationary phase and carries out the clock sampling processing with clock synchronization.

The signal FP_S of the first sampling of clock is because itself result from the edge sampling of system's frame head; Instability possibly appear in the FP_S that sampling obtains to system clock; Be in the metastable state state; So direct processing just possibly cause the instability of last header signal, therefore postpones a clock cycle sampling FP_S signal and obtains the metastable state that FP_SD eliminates FP_S, in order periodically to be had the header signal of clock width; FP_SD signal after the elimination metastable state is postponed a clock cycle sampling again obtain FP_SDD, obtain exporting header signal so that descend the step to handle.

It is a clock cycle width and periodically stable signal that the data processing of intersecting need obtain with reference to header signal; The FP_SDD and the FP_SD signal that obtain after handling now are periodic signals with frame length width; Therefore stable FP_SDD signal and FP_SD signal are carried out XOR; Obtain the FP_OUT signal; The FP_OUT signal is exactly a clock cycle width and has stable periodic signal, and the intersection alignment of data used after the header signal of locating after the correction that needs exactly, signal can supply cross chips.

Claims

1. the method for sampling of signal of locating frame head in the SDH transmission system is characterized in that, comprises the steps:

The system reference header signal that step 1, cross board receive clock plate are sent here utilizes the rising edge sampling of system reference header signal, handles carry out two divided-frequency with reference to header signal;

Step 2, the signal after two divided-frequency is handled is obtained the signal (FP_S) with said system clock synchronism stability with the system clock sampling; Be specially: the signal after the rising edge that utilizes system clock is handled two divided-frequency is sampled, and obtains the signal (FP_S) with said system clock synchronism stability;

Step 3, the signal (FP_S) that postpones a clock cycle sampling and the said system clock synchronism stability signal (FP_SD) after the metastable state that is eliminated postpones a clock cycle sampling again and obtains another signal (FP_SDD) eliminating signal (FP_SD) after the metastable state;

Step 4, the signal (FP_SDD) that the signal (FP_SD) after a clock cycle of signal (FP_SD) after the elimination metastable state and the delay sampling elimination metastable state is obtained carry out XOR, obtain revised signal of locating frame head (FP_OUT).