CN101154945A

CN101154945A - Programmable frequency divider with 50 percent of work period

Info

Publication number: CN101154945A
Application number: CNA2006101412220A
Authority: CN
Inventors: 严敏男
Original assignee: SHENGDA SEMICONDUCTOR CO Ltd
Current assignee: SHENGDA SEMICONDUCTOR CO Ltd
Priority date: 2006-09-28
Filing date: 2006-09-28
Publication date: 2008-04-02

Abstract

A programmable frequency divider comprises an inverse choosing device, two triggers, an AND gate and a counter. When one frequency dividing value is odd number and one transient of one triggering signal is received, the inverse choosing device is used to adjust one input clock signal which is transmitted after the transient of the triggering signal and reverse the phase relative to the input clock signal that is transmitted before the transient of the triggering signal, to generate a modified clock signal, and the modified clock signal and the clock conducting signal generated by the first trigger pass the AND gate to generate a delayed clock signal. The counter activates the second trigger by the delayed clock signal and the setting value of the frequency dividing value, the negative output end of the second trigger is coupled to the data input end and forms a 2-eliminated circuit thereby obtaining an output clock signal with 50% working period.

Description

Programmable frequency divider with 50% work period

Technical field

The present invention relates to a kind of frequency divider, particularly relate to a kind of programmable frequency divider with 50% work period.

Background technology

Please refer to Fig. 1, Fig. 1 is the schematic diagram of existing frequency divider 10.Frequency divider 10 comprises a counter 12, one comparators 14 and a toggle flip-flop 16.Counter 12 is exported a sequence count according to the rising edge of a reference frequency Fref.Comparator 14 can compare the counting of a numerical value n and counter 12, when numerical value n equates with the counting of counter 12, comparator 14 can be exported a high level square wave, counter 12 is compared the high level square wave triggering of device 14 outputs and resets to the beginning state that opens, again according to the rising edge of reference frequency Fref, export a sequence count Scn.The high level square wave that toggle flip-flop 16 is subjected to comparator 14 outputs triggers, and its output signal will be anti-phase, and therefore, frequency divider 10 mat counters 12 and comparator 14 formed loop circuits and a toggle flip-flop 16 are the exportable one frequency Fc2n divided by 2n.

Please refer to Fig. 2, Fig. 2 is the schematic diagram of existing frequency divider 10 outputs 1/4 frequency multiplication Fc4 waveform correlation.When frequency divider 10 needed output 1/4 frequency multiplication Fc4, the comparand n of comparator 14 can be set as 2.Counter 12 is according to the rising edge output sequence counting of reference frequency Frer, when the counting of counter 12 is 2, comparator 14 can be exported the high level signal, counter 12 is compared the high level square wave triggering of device 14 outputs and resets to the beginning state that opens, again begin counting by 0, so the sequence count Scn of counter 12 is that per 2 countings are circulation primary.Toggle flip-flop 16 is triggered by the high level signal of comparator 14 outputs, and its output signal will be anti-phase, so can be 50% 1/4 frequency multiplication Fc4 by toggle flip-flop 16 output output duty cycles.

For the frequency division of odd-multiple, then comparand n must switch between n+1 and n, could export a frequency Fc2n+1 divided by 2n+1.Please refer to Fig. 3, Fig. 3 is the schematic diagram of existing frequency divider 10 output 1/3 octave component Fc 3 waveform correlations.Counter 12 is according to the rising edge output sequence counting of reference frequency Fref, at the beginning when the counting of counter 12 is 2, comparator 14 just can be exported a high level square wave, counter 12 is compared the high level square wave triggering of device 14 outputs and resets to the beginning state that opens, again begin counting by 0, then when the counting of counter 12 is 1, comparator 14 will be exported a high level square wave, unison counter 12 is reset to opening the beginning state, again begin counting by 0, when the counting of counter 12 was 2, comparator 14 just can be exported a high level square wave afterwards, and so circulation is gone down.Toggle flip-flop 16 is triggered by the high level signal of comparator 14 outputs, its output signal will be anti-phase, work period by the 1/3 octave component Fc3 of toggle flip-flop 16 output is about 33%, therefore when divider ratio is odd number, the asymmetric problem of work period that frequency divider 10 will occurrence frequency Fc2n+1.

Summary of the invention

The invention provides a kind of programmable frequency divider with 50% work period, comprise an anti-phase choice device, being used in a divider ratio is odd number and when receiving the transition of a triggering signal, it is anti-phase to adjust this input clock signal that transmits before the transition of an input clock signal with respect to this triggering signal of transmitting after the transition of this triggering signal, to produce a clock signal of revising; One first trigger comprises a clock input, is used for importing the complementary signal of a shutdown signal, and a data input pin is used for importing the complementary signal of the clock signal of this modification and a positive output end; One with door, comprise two inputs, couple the output of this anti-phase device and the positive output end of this first trigger respectively, and an output, be used for exporting a clock signal that postpones; One counter, be coupled to this with the door output, be used for producing this triggering signal according to clock signal and this divider ratio of this delay; And one second trigger, comprise a clock input, be coupled to the output of this counter, a data input pin, a negative output terminal is coupled to this data input pin, and a positive output end, is used for exporting a clock signal.

Description of drawings

Fig. 1 is the schematic diagram of existing frequency divider.

Fig. 2 exports the schematic diagram of 1/4 frequency multiplication Fc4 waveform correlation for the frequency divider of Fig. 1.

Fig. 3 is the schematic diagram of the frequency divider output 1/3 octave component Fc3 waveform correlation of Fig. 1.

Fig. 4 is the schematic diagram of programmable frequency divider of the present invention.

Fig. 5 is the schematic diagram of the anti-phase choice device of Fig. 4.

Fig. 6 is the schematic diagram of the NAND gate combinational circuit of Fig. 5.

Fig. 7 is the schematic diagram of the counter of Fig. 4.

Fig. 8 is the schematic diagram that the programmable frequency divider of Fig. 4 is exported the correlation timing of 1/5 times of clock signal.

Fig. 9 is the schematic diagram that the programmable frequency divider of Fig. 4 is exported the correlation timing of 1/6 times of clock signal.

The reference numeral explanation

10 existing frequency divider 12 counters

14 comparator 16T D-flip flops

20 programmable frequency dividers, 22 anti-phase choice devices

24 first triggers, 26 counters

28 second triggers 30 or door

32 first NOR gate 34 first and door

36 the 3rd triggers, 38 first NAND gate combinational circuits

40 first NAND gate combinational circuit 41-43, first to the 3rd inverter

46-48 first to the 3rd NAND gate 51-53 the 4th to the 6th trigger

55 second with the door 56 the 3rd with the door

57 the 4th NAND gate, 58 second NOR gate

61-64 fellow disciple (biconditional gate)

Embodiment

Please refer to Fig. 4, Fig. 4 is the schematic diagram of programmable frequency divider 20 of the present invention.Programmable frequency divider 20 comprise an anti-phase choice device 22, one first trigger 24, a counter 26, one second trigger 28, one or

door

30,1 first NOR gate 32 and one first with door 34.The input signal of programmable frequency divider 20 comprises the set point N that a reset signal RST, closes (power down) signal PD, an input clock signal CKIN and a divider ratio.Set point N adds 1 and equals divider ratio, thus if divider ratio is an odd number, then the set point N least significant bit that is (least significant bit, LSB) C1 is 0, if divider ratio is an even number, then the set point N least significant bit C1 that is is 1.Reset signal RST and shutdown signal PD input or door 30 produce a power supply reset signal PR, and power supply reset signal PR produces triggering signal RB1 with the output signal RBC input NOR gate 32 of counter 26 again.Anti-phase choice device 22 receives position C1 and the triggering signal RB1 of input clock signal CKIN, set point N.Anti-phase choice device 22 is an odd number and when receiving the transition of triggering signal RB1 in divider ratio, it is anti-phase to adjust the input clock signal CKIN that transmits before the transition of input clock signal CKIN with respect to triggering signal RB1 of transmitting after the transition of triggering signal RB1, to produce a clock signal C KINA who revises.The data input pin of first trigger 24 receives the complementary signal CKINAB of the clock signal of revising, the input end of clock of first trigger 24 receives the complementary signal PDB of shutdown signal, so the positive output end of first trigger 24 is exported clock conducting (clock-on) signal CKON.Clock signal C KINA that revises and clock Continuity signal CKON input produce a clock signal C KINA1 who postpones with door 34.Counter 26 produces output signal RBC according to the clock signal C KINA1 of set point N and delay, the output signal RBC of counter 26 is by the input end of clock input of second trigger 28, because the negative output terminal of second trigger 28 is coupled to the data input pin of second trigger 28, so when the input end of clock of second trigger 28 is triggered, the signal that the positive output end of second trigger 28 is exported will be anti-phase, forms the clock signal FOUT of 50% work period.

Please refer to Fig. 5, Fig. 5 is the schematic diagram of the anti-phase choice device 22 of Fig. 4.Anti-phase choice device 22 comprises one the 3rd trigger 36, the first NAND gate combinational circuit 38, one second NAND gate combinational circuit 40 and first to the 3rd inverter 41-43, and wherein first and second has a first input end CK1, one second input CONT1, one the 3rd input CK2, a four-input terminal CONT2 and an output CKS respectively with door combinational circuit 38,40.Anti-phase choice device 22 receives position C1 and the triggering signal RB1 of input clock signal CKIN, set point N, to produce the input signal CKINA that revises.Clock signal C KIN also imports the first input end CK1 of the first NAND gate combinational circuit 38 by the 3rd input CK2 input of the first NAND gate combinational circuit 38 via first inverter 41.The position C1 of set point N also imports the second input CONT1 of the first NAND gate combinational circuit 38 by the four-input terminal CONT2 input of the first NAND gate combinational circuit 38 via second inverter 42.Triggering signal RB1 is by the input end of clock input of the 3rd trigger 36, the negative output terminal of the 3rd trigger 36 is coupled to the data input pin of the 3rd trigger 36, the positive output end of the 3rd trigger 36 is coupled to the second input CONT1 of the second NAND gate combinational circuit 40, also is coupled to the four-input terminal CONT2 of the second NAND gate combinational circuit 40 via the 3rd inverter 43.The 3rd input CK2 of the second NAND gate combinational circuit 40 is coupled to the first input end CK1 of the first NAND gate combinational circuit 38, and the first input end CK1 of the second NAND gate combinational circuit 40 is coupled to the output of the first NAND gate combinational circuit 38.The input signal CKINA of the output output modifications of the second NAND gate combinational circuit 40.

Please refer to Fig. 6, Fig. 6 is the schematic diagram of the first NAND gate combinational circuit 38 of Fig. 5.The structure of the second NAND gate combinational circuit 40 is identical with the first NAND gate combinational circuit 38.The first NAND gate combinational circuit 38 comprises three NAND gate 46-48, and each NAND gate has two inputs and an output.The output of the output of first NAND gate 46 and second NAND gate 47 is respectively coupled to two inputs of the 3rd NAND gate 48.Two inputs of first NAND gate 46 correspond respectively to the first input end CK1 and the second input CONT1 of the first NAND gate combinational circuit 38, two inputs of second NAND gate 47 correspond respectively to the 3rd input CK2 and four-input terminal CONT2 of the first NAND gate combinational circuit 38, and the output of the 3rd NAND gate 48 is corresponding to the output CKS of the first NAND gate combinational circuit 38.

Please refer to Fig. 7, Fig. 7 is the schematic diagram of the counter 26 of Fig. 4.Counter 26 comprises the 4th trigger 51, the 5th trigger 52, the 6th trigger 53, four fellow disciple 61-64, second and door the 55, the 3rd and

door

56,1 the 4th NAND gate 57 and one second NOR gate 58, each above-mentioned gate all has two inputs and an output, and the negative input of each above-mentioned trigger all is coupled to the data input pin of itself.The input signal of counter 26 comprises the clock signal C KINA1 and the set point N of delay, and wherein set point N is made up of four position C8, C4, C2, C1, and position C8 is Must Significant Bit (MSB), and position C1 is least significant bit (LSB).The clock signal C KINA1 that postpones is input to the input end of clock of the 4th trigger 51 and first fellow disciple's 61 first input end, and first fellow disciple's 61 second input is used for importing the position C1 of set point N.The positive output end of the 4th trigger 51 is coupled to the input end of clock of the 5th trigger 52 and second fellow disciple's 62 first input end, and second fellow disciple's 62 second input is used for importing the position C2 of set point N.The positive output end of the 5th trigger 52 is coupled to the input end of clock of the 6th trigger 53 and the 3rd fellow disciple's 63 first input end, and the 3rd fellow disciple's 63 second input is used for importing the position C4 of set point N.The positive output end of the 6th trigger 53 is coupled to the 4th fellow disciple's 64 first input end, and the 4th fellow disciple's 64 second input is used for importing the position C8 of set point N.First fellow disciple 61 and the 3rd fellow disciple's 63 output be respectively coupled to second with door 55 two inputs, second fellow disciple 62 and the 4th fellow disciple's 64 output be respectively coupled to the 3rd with two inputs of door 56.Second is respectively coupled to two inputs of the 4th NAND gate 57 with door the 55 and the 3rd and door 56 output, the output of the 4th NAND gate 57 is coupled to two inputs of second NOR gate 58, the output signal RBC of the output output counter 26 of second NOR gate 58.

Please refer to Fig. 8, Fig. 8 is the schematic diagram that the programmable frequency divider 20 of Fig. 4 is exported the correlation timing of 1/5 times of clock signal FOUT, anti-phase choice device 22 receives position C1 and the triggering signal RB1 of input clock signal CKIN, set point N, in the present embodiment, divider ratio is 5, so position C8, C4, C2, the C1 of set point N are respectively 0,1,0,0.When the C1 of set point N is 0 and anti-phase choice device 22 when receiving the transition of triggering signal RB1, the input clock signal CKIN that transmits before the transition of input clock signal CKIN with respect to triggering signal RB1 that anti-phase choice device 22 can will transmit after the transition of triggering signal RB1 is anti-phase, produce the clock signal C KINA that revises, shown in the clock signal C KINA of the modification among Fig. 8, the signal of t2 period is with respect to the signal inversion of the t1 period before the transition of triggering signal RB1.Clock Continuity signal CKON is that the complementary signal PDB of the complementary signal CKINAB of clock signal that utilize to revise and shutdown signal is input to first trigger 24 and produces, and the clock signal C KINA1 of delay then is the clock signal C KINA of modification and the result that clock Continuity signal CKON does the logical computing.Counter 26 is done counting according to the clock signal C KINA1 and the set point N that postpone, produce output signal RBC, the output signal RBC of counter makes the computing generation triggering signal RB1 of logic nondisjunction on the one hand with power supply reset signal PR, also be used on the other hand triggering second trigger 28, form the clock signal FOUT of 50% work period.

Please refer to Fig. 9, Fig. 9 is the schematic diagram that the programmable frequency divider 20 of Fig. 4 is exported the correlation timing of 1/6 times of clock signal FOUT, and divider ratio is 6 o'clock, and position C8, the C4 of set point N, C2, C1 are respectively 0,1,0,1.When the C1 of set point N was 1, the clock signal C KINA of the modification that anti-phase choice device 22 produces was identical with input clock signal CKIN, utilized the clock signal C KINA that revises to produce the clock signal C KINA1 that postpones again.Then, counter 26 is done counting according to the clock signal C KINA1 and the set point N that postpone, produces output signal RBC and triggers second trigger 28, has the clock signal FOUT of 50% work period with output.From the above, maximum different were exactly the clock signal C KINA of the modification that produces of anti-phase choice device 22 when programmable frequency divider 20 was odd number with divider ratio when divider ratio is even number, no matter yet divider ratio is odd number or even number, all exportable clock signal FOUT of programmable frequency divider 22 with 50% work period.

In sum, programmable frequency divider of the present invention comprises an anti-phase choice device, one first trigger, one and door, a counter and one second trigger.It is odd number and when receiving the transition of a triggering signal that this anti-phase choice device is used in a divider ratio, it is anti-phase to adjust this input clock signal that transmits before the transition of an input clock signal with respect to this triggering signal of transmitting after the transition of this triggering signal, to produce a clock signal of revising, utilize this first trigger to produce a clock Continuity signal again, the clock signal of this modification and this clock Continuity signal produce a clock signal that postpones through this and door.This counter triggers this second trigger according to the clock signal of this delay and the set point of this divider ratio, and the negative output terminal of second trigger is coupled to its data input pin and forms one except that 2 circuit, therefore obtains the tool clock signal of 50% work period.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. programmable frequency divider with 50% work period comprises:

One anti-phase choice device, being used in a divider ratio is odd number and when receiving the transition of a triggering signal, it is anti-phase to adjust this input clock signal that transmits before the transition of an input clock signal with respect to this triggering signal of transmitting after the transition of this triggering signal, to produce a clock signal of revising;

One first trigger comprises a clock input, is used for importing the complementary signal of a shutdown signal, and a data input pin is used for importing the complementary signal of the clock signal of this modification and a positive output end;

One with door, comprise two inputs, couple the output of this anti-phase device and the positive output end of this first trigger respectively, and an output, be used for exporting a clock signal that postpones;

One counter, be coupled to this with the door output, be used for producing this triggering signal according to clock signal and this divider ratio of this delay; And

One second trigger comprises a clock input, is coupled to the output of this counter, a data input pin, and a negative output terminal is coupled to this data input pin, and a positive output end, is used for exporting a clock signal.

2. programmable frequency divider as claimed in claim 1, wherein this first trigger and this second trigger are D flip-flop.

3. programmable frequency divider as claimed in claim 1, wherein this anti-phase choice device comprises:

One the 3rd trigger comprises a clock input, is used for importing this triggering signal, a data input pin, and a negative output terminal is coupled to this data input pin, and a positive output end;

One first NAND gate combinational circuit, comprise a first input end, be used for importing the complementary signal of this input clock signal, one second input is used for importing the complementary of the set point of this divider ratio, one the 3rd input, be used for importing this input clock signal, one four-input terminal is used for importing the set point of this divider ratio and an output; And

One second NAND gate combinational circuit, comprise a first input end, be coupled to the output of this second NAND gate combinational circuit, one second input is coupled to the positive output end of the 3rd trigger, one the 3rd input, be coupled to the first input end of this second NAND gate combinational circuit, a four-input terminal is coupled to the positive output end of the 3rd trigger via an inverter, and an output, be used for exporting the clock signal of this modification.

4. programmable frequency divider as claimed in claim 3, wherein the 3rd trigger is a D flip-flop.

5. programmable frequency divider as claimed in claim 3, wherein this first NAND gate combinational circuit and this second NAND gate combinational circuit comprise respectively:

One first NAND gate comprises two inputs and an output;

One second NAND gate comprises two inputs and an output; And

One the 3rd NAND gate comprises two inputs, is respectively coupled to the output of this first NAND gate and second NAND gate, and an input.

6. programmable frequency divider as claimed in claim 1, wherein this counter comprises:

One the 4th trigger comprises a clock input, is used for importing the clock signal of this delay, a data input pin, and a negative output terminal is coupled to this data input pin, and a positive output end;

One the 5th trigger comprises a clock input, is coupled to the positive output end of the 4th trigger, a data input pin, and a negative output terminal is coupled to this data input pin, and a positive output end;

One the 6th trigger comprises a clock input, is coupled to the positive output end of the 5th trigger, a data input pin, and a negative output terminal is coupled to this data input pin, and a positive output end;

One first fellow disciple comprises a first input end, is used for importing first of set point of this divider ratio, and one second input is coupled to the input end of clock of the 4th trigger and an output;

One second fellow disciple comprises a first input end, is used for importing second of set point of this divider ratio, and one second input is coupled to the positive output end of the 4th trigger and an output;

One the 3rd fellow disciple comprises a first input end, is used for importing the 3rd of set point of this divider ratio, and one second input is coupled to the positive output end of the 5th trigger and an output;

One the 4th fellow disciple comprises a first input end, is used for importing the 3rd of set point of this divider ratio, and one second input is coupled to the positive output end of the 6th trigger and an output;

One the secondth with door, comprise two inputs, be respectively coupled to this first and the 3rd fellow disciple's output, and an output;

One the 3rd with door, comprise two inputs, be respectively coupled to this second and the 4th fellow disciple's output, and an output;

One the 4th NAND gate comprises two inputs, be respectively coupled to this second and the 3rd with the output of door, an and output; And

One second NOR gate comprises two inputs, is respectively coupled to the output of the 4th NAND gate, and an output.

7. programmable frequency divider as claimed in claim 1, wherein the 4th trigger, the 5th trigger and the 6th trigger are D flip-flop.

8. programmable frequency divider as claimed in claim 1 also comprises:

One or door, comprise two inputs, be used for importing a reset signal and a shutdown signal, and an output; And

One NOR gate comprises a first input end, is coupled to the output of this counter, and one second input is coupled to the output of this or door, and an output, is coupled to this anti-phase choice device.