CN101150875B - A device and method for switching mapping modes - Google Patents
A device and method for switching mapping modes Download PDFInfo
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- CN101150875B CN101150875B CN 200610113254 CN200610113254A CN101150875B CN 101150875 B CN101150875 B CN 101150875B CN 200610113254 CN200610113254 CN 200610113254 CN 200610113254 A CN200610113254 A CN 200610113254A CN 101150875 B CN101150875 B CN 101150875B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
Abstract
The invention relates to a device for switching by a mapping mode, including a receiving module, a local clock source module, a two-channel switch, a sending locked loop module, a control module; the receiving moduel is used for receiving the upriver signal, and recovers the clock from the service; the local clock source module is used to offer the referrence clock for the receiving module and offer the local referrence clock for the two-channel switch; the two-channel switch is used to receive the clock recovered from the service and offer the local referrence clock, and send the locked loop prior clock; the locked loop module is used to send the referrence clock; the control module is used to control other modules. By using the method and the device, the advance of simplifying the hardware structure is got, the effect of supporting the synchronous mapping, the asynchronous mopping and various services are reached, the hardware units are saved, the reliability of the clock unit is improved.
Description
Technical field
The present invention relates to a kind of realization mapping mode and different business device for switching, relate in particular in the field of optical networks wavelength division multiplexing transmission equipment, use the part of synchronization map mode and asynchronous mapping mode.
Background technology
In Synchronous Optical Network, the clock frequency of all switching nodes and phase place all should be controlled in certain range of tolerable variance in the overall optical network, to guarantee that whole digital streams of each switching node are realized correct effectively exchange in the network.Yet G.975/G.709 a lot of node places are with outer FEC owing to having increased in the standard such as ITU-T, and cause the increase of service rate because application need can carry out the speed conversion of clock.In this case, just need carry out the synchronous/asynchronous conversion to the clock of business.
According to standard G.709, two kinds of mapping modes are arranged: synchronization map mode (Bit Synchronous Maping) and asynchronous mapping mode (Asynchronous Mapping) when payload information being mapped to light path Payload Unit (OPUk) frame.
The synchronization map mode, light repeat plate (OTU) is received the reference clock signal that upstream node or reference clock source provide, the phase locking that makes OTU internal clock and tranmitting data register by phase-locked loop in the OTU (PLL) is to the timing base of receiving, thereby the clock of OTU and reference clock signal are synchronous.
The asynchronous mapping mode, if occur bigger frequency departure in the optical-fiber network, OTU uses local reference clock as reference clock signal, make by phase-locked loop in the OTU on the local reference clock of phase locking of OTU internal clock and tranmitting data register, local reference clock should guarantee frequency deviation with standard speed in certain limit, with guarantee the overall optical network synchronously.According to standard G.709, the maximum frequency deviation of payload and OPUk must be less than 20ppm under the asynchronous mapping mode.
The reality of clock unit is only supported the synchronization map mode at present, perhaps only supports the asynchronous mapping mode, can not support two kinds of mapping modes simultaneously, can not support the switching of dual mode.Common realization asynchronous mapping method is: according to the service rate that OTU handles, using independently, clock generator provides reference clock as local clock as phase-locked loop in the OTU.For different service rates, need hardware to increase different clock generators, hardware configuration is comparatively complicated.
Summary of the invention
In order to solve above-mentioned technical problem, a kind of realization mapping mode and professional device for switching are provided, its purpose is, makes OTU support synchronization map mode and asynchronous mapping mode simultaneously, and supports the multiple business type.
The invention provides a kind of realization mapping mode device for switching, it is characterized in that, comprise receiver module, local clock source module, either-or switch, transmission phase-locked loop module, control module;
Described receiver module is used to receive the signal from the upstream, and from business recovered clock;
Described local clock source module is used to described receiver module to provide to receive reference clock and provides local reference clock for described either-or switch; If in the asynchronous mapping mode, then described either-or switch is selected described local reference clock; If in the synchronization map mode, then described either-or switch select described from business clock recovered;
Described either-or switch is used for receiving described from business clock recovered and described local reference clock, and sends phase-locked loop prime clock; Described transmission phase-locked loop module is used to send reference clock; Described control module is used to control described all the other modules,
Described control module is made up of CPU and FPGA, if the OTU rate variation of managing business, then adjusts the value of corresponding control register among the FPGA.
Described receiver module is an Optical Receivers, comprises optical-electrical converter, clock recovery unit.Described Optical Receivers also comprises phase-locked loop and/or frequency divider.Described optical-electrical converter is a 10G pin module, and described clock recovery unit is clock and data recovery unit.
Described local clock source module comprises the local clock source and receives phase-locked loop that described reception phase-locked loop is a programmable phase-locked loop.
Described transmission phase-locked loop module comprises frequency divider 1, phase discriminator, filter, voltage controlled oscillator, frequency divider 2; Described frequency divider 1 is used for giving described phase discriminator with output signal; Described phase discriminator is used for giving described filter with output signal, and receives the feedback of described frequency divider 2; Described filter is used for giving described voltage controlled oscillator with output signal; Described voltage controlled oscillator is used for output and sends reference clock and phase-locked loop feedback clock; Described frequency divider 2 after being used for described phase-locked loop feedback clock carried out frequency division, is sent into described phase discriminator as feedback signal.
The ratio of the coefficient of described frequency divider 1 and frequency divider 2 meets Read-Solomon (255,237) encoding scheme.
Described control module is made up of CPU and FPGA.
The invention provides a kind of method that realizes that mapping mode switches, comprise following concrete steps:
The reception reference clock that step 101, reception local clock source are provided, and reception is from the signal of upstream, recovered clock from business; Described local clock source provides local reference clock for either-or switch;
If step 102 light repeat plate is operated in the asynchronous mapping mode, then described either-or switch is selected described local reference clock; If light repeat plate is operated in the synchronization map mode, then described either-or switch select described from business clock recovered;
The output signal of step 103, the described either-or switch of reception also sends reference clock;
Described step is accepted the control of control module, and described control module is made up of CPU and FPGA, if the OTU rate variation of managing business, then adjusts the value of corresponding control register among the FPGA.
Adopt the method for the invention and device, compared with prior art, owing to taked the local clock source module that the two-way clock is provided, provide the technical measures of reference clock with recovered clock alternative in the business for installing interior phase-locked loop, the simplification hardware configuration progress that has obtained, reached and supported synchronization map and asynchronous mapping and multiple business type effect simultaneously, saved hardware cell, improved the reliability of clock unit.The present invention makes OTU support synchronization map mode and asynchronous mapping mode simultaneously, and supports the multiple business type.This device can be applicable to OTU clock internal unit.
Description of drawings
Fig. 1 is that device provided by the invention is formed;
Fig. 2 is that local clock source module provided by the invention is formed;
Fig. 3 is that Optical Receivers provided by the invention is formed;
Fig. 4 is that transmission phase-locked loop module provided by the invention is formed;
Fig. 5 is a device example provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The technical problem to be solved in the present invention is to realize a covering device with low cost, less hardware, is used for the asynchronous mapping mode and creates the OPUk signal, and can realize switching with the synchronization map mode, supports the multiple business type.
A kind of realization mapping mode of the present invention and professional device for switching are made up of Optical Receivers 101, local clock source module 102, control module 103, either-or switch 104, transmission phase-locked loop module 105, and each module is formed as shown in Figure 1.
Local clock source module 102 is formed as shown in Figure 2 in detail among Fig. 1.It act as provides high-quality " local reference clock b " and " the reference clock a of Optical Receivers "." the reference clock a of Optical Receivers " provides reference clock for Optical Receivers 101.The frequency deviation and the temperature stability in local clock source 201 are fine, and high accuracy clock is provided.Receiving phase-locked loop 202 can be according to the local clock source, output and the suitable clock of service rate.
Transmission phase-locked loop module 105 among Fig. 1 is formed as shown in Figure 4 in detail.Frequency divider 1 401 is given phase discriminator 402 with output signal, phase discriminator 402 is given filter 403 with output signal, filter 403 is given voltage controlled oscillator 404 with output signal, voltage controlled oscillator 404 outputs send reference clock h, will send phase-locked loop feedback clock c simultaneously and send into phase discriminator 402 as feedback signal through frequency divider 2 405.
The selection of either-or switch 104 can be controlled among Fig. 1, selects " clock recovered d from business " or " local reference clock b " that " sending phase-locked loop prime clock g " is provided for sending phase-locked loop module 105.Select A can realize the asynchronous mapping mode, select B can realize the synchronization map mode.
This device can be applied on the dense wave division multipurpose OTU that supports STM64 business, 10GE business.The device example is formed as shown in Figure 5: the professional light from the upstream enters Optical Receivers, and Optical Receivers extracts business clock and data; The Business Processing part can be carried out some overhead processing, and then by optical repeater business datum is sent.Clock unit partly is made up of reception phase-locked loop, local reference clock, supports asynchronous simultaneously and establishment synchronization map mode OPUk signal.
Clock net input clock or high precision temperature compensation crystal oscillator (TCXO) etc. are selected in local clock source 102 among Fig. 5, and described CPU or FPGA control receive the output frequency of phase-locked loop.Receive phase-locked loop and select programmable phase-locked loop for use, the output clock that frequency deviation is less, precision is higher.
Either-or switch 104 among Fig. 5 can be by CPU or FPGA control.Optical Receivers is selected standard compliant 10G transmitting-receiving unification optical module for use.
Transmission phase-locked loop module 105 among Fig. 5 uses discrete component to form.Be STM64 or 10GE if manage business, and (frequency divider 1 401 Coefficient m among Fig. 4, frequency divider 2 405 coefficient n get analog value for Reed-Solomon, RS) encoding scheme to use Read-Solomon (255,237).Satisfy m: n=237: 255.M is 79 among Fig. 5, and n is 85.
Realize one-to-two by hardware, one tunnel reference clock wherein as Optical Receivers, either-or switch 104 is delivered on another road, sends the prime clock of phase-locked loop part during as asynchronous mapping.Synchronous from recovered clock and reference clock signal that Optical Receivers obtains, also deliver to either-or switch 104, send the prime clock of phase-locked loop module during as synchronization map.By CPU or FPGA control " either-or switch ", decision sends the prime clock of phase-locked loop module, promptly sends the reference clock signal that phase-locked loop module obtains, thereby decision OTU works in synchronization map mode or asynchronous mapping mode.The speed of programmable phase-locked loop is also all controlled by control module in the divide ratio of the clock rate of Optical Receivers, discrete transmission phase-locked loop module, the local clock source module.
1) realization and the switching of asynchronous mapping mode and synchronization map mode
The selection of either-or switch 104 is controlled by CPU or FPGA, thereby need not to change hardware, can support asynchronous mapping mode and synchronization map and switching thereof.
If require OTU to be operated in the asynchronous mapping mode, the either-or switch 104 among Fig. 5 is selected A.At this moment, send phase-locked loop module and be locked in " local reference clock b "." local reference clock b " has less frequency deviation, higher quality, and VCO exports clock stable, frequency deviation is very little, shake is little, is suitable for the asynchronous mapping mode and creates the OPUk signal, and the maximum frequency deviation of payload and OPUk meets G.709 standard less than 20ppm.Thereby guaranteed the quality of " sending reference clock h ".
If require OTU to be operated in the synchronization map mode, when the optical-fiber network operate as normal at OTU place, the either-or switch 104 among Fig. 5 is selected B.Send phase-locked loop module and be locked in " the clock recovered d from business " that Optical Receivers provides, from " clock recovered d from business " and " from upstream light signal e " service synchronization.
2) different business of OTU processing is realized and is switched
Local clock source module 102 among Fig. 5 provides " the reference clock a of Optical Receivers ", reference clock signal when the asynchronous mapping mode is provided again " local reference clock b ", the frequency of its output clock is variable, can adjust the frequency of output clock by FPGA.The rate variation if OTU manages business, only need are adjusted the value of corresponding control register among the FPGA and be need not to change hardware.The fixed frequency clock generator provides reference clock as local clock as phase-locked loop in the OTU thereby avoided using independently, need dispose the shortcoming of corresponding clock generator for different business.
If " from upstream light signal e " poor quality or no signal among Fig. 5 can not influence the transmission phase-locked loop module yet and be locked in " local reference clock b ", thereby guarantee the clock quality of " to downstream light signal k ".
The process of controlling this device is as follows:
When 1) OTU powers on, read default configuration, according to default configuration, by CPU or FPGA, the clock stream of selecting either-or switch 104 among Fig. 5 to.Also can be by the mapping mode of network management configuration OTU.
2), the output clock of local clock source module 102 among Fig. 5 is set by FPGA according to the type of service of network management configuration.If type of service is STM64, output 155.52MHz, if type of service is 10GE, output 161.133MHz.
3) according to type of service, Optical Receivers 101, transmission phase-locked loop module 105 are done the control corresponding adjustment to adapt to corresponding speed among Fig. 5.The clock rate of Optical Receivers 101 is adjusted into the speed of STM64, i.e. the speed of 9.953GHz or 10GE, i.e. 10.312GHz; The clock rate of transmission phase-locked loop module 105 is adjusted into speed G.709, i.e. 10.709GHz or 11.095GHz.
4) according to mapping mode and type of service, relative set is done in the related FPGA register of each module, control etc. among Fig. 5.The divide ratio m that CPU will send phase-locked loop module 105 is configured to 79, n is configured to 85.CPU makes each module be in opening by the FPGA register is set.
By above step, can be used for the asynchronous mapping mode and create the OPUk signal producing clock by this locality, clock stable is reliable, and with the mapping of OPUk signal Synchronization create switch easy.The method is with low cost, does not need to use clock devices extra or that specific (special) requirements is arranged.And need not hardware and change,, just can realize the switching of synchronization map mode and asynchronous mapping only by software control.The OTU speed of managing business changes, and also need not to change hardware.
In sum, adopt the method for the invention and device, compared with prior art, owing to taked the local clock source module that the two-way clock is provided, provide the technical measures of reference clock with recovered clock alternative in the business for phase-locked loop in installing, the simplification hardware configuration progress that has obtained has reached and has supported synchronization map and asynchronous mapping and multiple business type effect simultaneously, save hardware cell, improved the reliability of clock unit.The present invention makes OTU support synchronization map mode and asynchronous mapping mode simultaneously, and supports the multiple business type.This device can be applicable to OTU clock internal unit.
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (8)
1. realize the mapping mode device for switching for one kind, it is characterized in that, comprise receiver module, local clock source module, either-or switch, transmission phase-locked loop module, control module;
Described receiver module is used to receive the signal from the upstream, and from business recovered clock;
Described local clock source module is used to described receiver module to provide to receive reference clock and provides local reference clock for described either-or switch;
Described either-or switch is used for receiving described from business clock recovered and described local reference clock, and sends phase-locked loop prime clock; If in the asynchronous mapping mode, then described either-or switch is selected described local reference clock; If in the synchronization map mode, then described either-or switch select described from business clock recovered;
Described transmission phase-locked loop module is used to send reference clock;
Described control module is used to control described all the other modules;
Described control module is made up of CPU and FPGA, if the OTU rate variation of managing business, then adjusts the value of corresponding control register among the FPGA.
2. realization mapping mode device for switching as claimed in claim 1 is characterized in that described receiver module is an Optical Receivers, comprises optical-electrical converter, clock recovery unit.
3. realization mapping mode device for switching as claimed in claim 2 is characterized in that described Optical Receivers also comprises phase-locked loop and/or frequency divider.
4. realization mapping mode device for switching as claimed in claim 2 is characterized in that, described optical-electrical converter is a 10G pin module, and described clock recovery unit is clock and data recovery unit.
5. realization mapping mode device for switching as claimed in claim 1 is characterized in that, described local clock source module comprises the local clock source and receive phase-locked loop that described reception phase-locked loop is a programmable phase-locked loop.
6. realization mapping mode device for switching as claimed in claim 1 is characterized in that described transmission phase-locked loop module comprises frequency divider 1, phase discriminator, filter, voltage controlled oscillator, frequency divider 2;
Described frequency divider 1 is used for giving described phase discriminator with output signal;
Described phase discriminator is used for giving described filter with output signal, and receives the feedback of described frequency divider 2;
Described filter is used for giving described voltage controlled oscillator with output signal;
Described voltage controlled oscillator is used for output and sends reference clock and phase-locked loop feedback clock;
Described frequency divider 2 after being used for described phase-locked loop feedback clock carried out frequency division, is sent into described phase discriminator as feedback signal.
7. realization mapping mode device for switching as claimed in claim 6 is characterized in that, the ratio of the coefficient of described frequency divider 1 and frequency divider 2 meets Read-Solomon (255,237) encoding scheme.
8. method that realizes that mapping mode switches is characterized in that having following concrete steps:
Step 91, control module control receive the reception reference clock that the local clock source is provided, and receive the signal from the upstream, recovered clock from business; Described local clock source provides local reference clock for either-or switch;
If step 92 light repeat plate is operated in the asynchronous mapping mode, then described either-or switch is selected described local reference clock; If light repeat plate is operated in the synchronization map mode, then described either-or switch select described from business clock recovered;
The output signal of step 93, the described either-or switch of reception also sends reference clock;
Wherein, described step is accepted the control of control module, and described control module is made up of CPU and FPGA, if the OTU rate variation of managing business, then adjusts the value of corresponding control register among the FPGA.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610113254 CN101150875B (en) | 2006-09-20 | 2006-09-20 | A device and method for switching mapping modes |
| PCT/CN2006/003776 WO2008034310A1 (en) | 2006-09-20 | 2006-12-30 | A device and method for realizing the switching of the mapping mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610113254 CN101150875B (en) | 2006-09-20 | 2006-09-20 | A device and method for switching mapping modes |
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| Publication Number | Publication Date |
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| CN101150875A CN101150875A (en) | 2008-03-26 |
| CN101150875B true CN101150875B (en) | 2010-09-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200610113254 Expired - Fee Related CN101150875B (en) | 2006-09-20 | 2006-09-20 | A device and method for switching mapping modes |
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| WO (1) | WO2008034310A1 (en) |
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| CN106550289B (en) * | 2015-09-17 | 2019-12-31 | 深圳市中兴微电子技术有限公司 | Method, device and client for providing reference clock for serial-parallel converter |
| CN109639358B (en) * | 2018-12-28 | 2023-09-01 | 杭州飞畅科技有限公司 | Node optical transceiver and large-scale telephone transmission system and method based on same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1248841A (en) * | 1998-08-26 | 2000-03-29 | 富士通株式会社 | Clock management method and transmission equipment for synchronous network system |
| CN1344077A (en) * | 2000-09-08 | 2002-04-10 | 朗迅科技公司 | Timing circuit of multiplex/demultiplex optical communicating signal |
| EP1376915A2 (en) * | 2002-06-27 | 2004-01-02 | Alcatel | Clock synchronization system and method for use in a scalable access node |
| US6839858B1 (en) * | 2001-05-14 | 2005-01-04 | Ciena Corporation | System for clock synchronization |
-
2006
- 2006-09-20 CN CN 200610113254 patent/CN101150875B/en not_active Expired - Fee Related
- 2006-12-30 WO PCT/CN2006/003776 patent/WO2008034310A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1248841A (en) * | 1998-08-26 | 2000-03-29 | 富士通株式会社 | Clock management method and transmission equipment for synchronous network system |
| CN1344077A (en) * | 2000-09-08 | 2002-04-10 | 朗迅科技公司 | Timing circuit of multiplex/demultiplex optical communicating signal |
| US6839858B1 (en) * | 2001-05-14 | 2005-01-04 | Ciena Corporation | System for clock synchronization |
| EP1376915A2 (en) * | 2002-06-27 | 2004-01-02 | Alcatel | Clock synchronization system and method for use in a scalable access node |
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| Publication number | Publication date |
|---|---|
| WO2008034310A1 (en) | 2008-03-27 |
| CN101150875A (en) | 2008-03-26 |
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