CN101150123A - Semiconductor encapsulation structure with electromagnetic shielding cover - Google Patents
Semiconductor encapsulation structure with electromagnetic shielding cover Download PDFInfo
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- CN101150123A CN101150123A CNA2007101672773A CN200710167277A CN101150123A CN 101150123 A CN101150123 A CN 101150123A CN A2007101672773 A CNA2007101672773 A CN A2007101672773A CN 200710167277 A CN200710167277 A CN 200710167277A CN 101150123 A CN101150123 A CN 101150123A
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- shielding cover
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Abstract
This invention relates to a semiconductor package structure with an electromagnetic cover including two base boards and an electromagnetic shield cover, in which, each board has a chip, said shield cover is set between the two boards to shield electromagnetic interference between the chips of the two boards, and one of the board includes a containing chamber for placing the cover, therefore, the height of the package structure will not be increased.
Description
Technical field
The present invention relates to a kind of semiconductor package, particularly about a kind of semiconductor package with electromagnetic shielding cover.
Background technology
Owing to the fast development of electronic industry, electronic product or electrical appliance have become indispensable articles for use in people's life at present, but electronic equipment or electrical appliance always produce electromagnetic interference, so that influence miscellaneous equipment or system.It may be quite slight, temporary transient malfunction that this class is disturbed, but also may cause dysfunction, even causes device damage.The generation of described electromagnetic interference is because constantly the electric current of change causes the electric field of change, and follows the electric field of change and what come is exactly the magnetic field that changes.And electromagnetic radiation (electromagnetic wave) is exactly combine (vector product) in vibration and mutually perpendicular electric field and magnetic field.
In High Density Packaging Technology, can adopt side by side (Side by side) formula, multiple chips is come encapsulation together; Perhaps adopt another kind to pile up (Stack) formula, multiple chips is piled up, be combined into a complete system (System In Package).With regard to the mode of covering of electromagnetic interference, can adopt the metallic circuit (Trace) of substrate to realize basic electromagnetic shielding requirement.Yet, adopt the mode of metallic circuit may not necessarily meet demand in fact, the closed intensity of circuit also can influence its screening effect in addition.
In view of this, the present invention proposes a kind of more effectively electromagnetic shielding mode, utilize its special electromagnetic armouring structure, the effect of electromagnetic shielding not only can be provided, prevent to interfere with each other between its chipset, and this electromagnetic armouring structure can not increase the vertical height of piling up of encapsulation.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor package, it has an electromagnetic shielding cover, to shield the electromagnetic interference between the two adjacent chips.
For achieving the above object, the invention provides a kind of semiconductor package, comprise an electromagnetic shielding cover, one first substrate, one second substrate and several Metal Ball with electromagnetic shielding cover.This electromagnetic shielding cover one first room that sets to the concave.This first substrate has one first upper surface and one first lower surface, and this first upper surface is provided with one first chip, and this first lower surface forms one second room, in order to the some of ccontaining this electromagnetic shielding cover.This second substrate has one second upper surface and one second lower surface, and this second upper surface is provided with one second chip.
This electromagnetic shielding cover is located at this second chip top, and this second chip is placed in first room of this electromagnetic shielding cover, separates this first and second chip by this.This second substrate further is provided with at least one via, and it runs through this second substrate.These several Metal Ball comprise several conducting Metal Ball and several grounded metal balls, and it is arranged at first lower surface of this first substrate and second lower surface of this second substrate.These several conducting Metal Ball are respectively in order to electrically connecting the interlock circuit on this first substrate and this second substrate, and the outside I/O end that forms this second substrate, with the I/O signal of telecommunication.These several grounded metal balls are positioned at second lower surface of this second substrate, in order to electrically connect the via of this second substrate.Exposed several ground connection projections in second room of this first substrate, electrically connecting this electromagnetic shielding cover, thereby this electromagnetic shielding cover connects other earthed circuit by this via and this grounded metal ball.Like this, can effectively prevent to pile up phase mutual interference between the chip of setting, and avoid this structural configuration to increase the vertical height of piling up of encapsulation.
The present invention provides a kind of chip ornaments mode the different semiconductor packages with electromagnetic shielding cover in addition, its main difference is that said structure is that one first chip is set on first upper surface of first substrate, this structure then is that first lower surface at first substrate is provided with at least one first chip, and further the end face at this electromagnetic shielding cover is provided with several fins, to improve radiating efficiency.
Compared with prior art, the semiconductor package that the present invention has electromagnetic shielding cover can improve prior art realizes electromagnetic shielding with the metallic circuit on the substrate basic mode, and be not subject to the layout situation of this metallic circuit and influence screening effect, can not increase original encapsulation stacking vertical height yet.
The present invention is further illustrated below in conjunction with accompanying drawing and embodiment.
Description of drawings
Fig. 1 is for having the schematic diagram of the semiconductor package of electromagnetic shielding cover according to one of first embodiment of the invention.
Fig. 2 is for having the schematic diagram of the semiconductor package of electromagnetic shielding cover according to one of second embodiment of the invention.
Embodiment
Relevant detailed description of the present invention and technology contents, existing as follows with regard to accompanying drawings:
Fig. 1 is for having the schematic diagram of the semiconductor package of electromagnetic shielding cover according to one of first embodiment of the invention.This semiconductor package with electromagnetic shielding cover comprises an electromagnetic shielding cover 101, one first substrate 102, one second substrate 103, several conducting Metal Ball 113 and several grounded metal balls 115.
This electromagnetic shielding cover 101 is concaved with one first room 105.This first substrate 102 has one first upper surface 106 and one first lower surface 107, and this first upper surface 106 is provided with one first chip 108, this first lower surface 107 forms the some of one second room 109 in order to ccontaining this electromagnetic shielding cover 101, and this second room 109 can run through or not run through this first substrate 102.This first chip 108 is provided with at least one ground connection projection 116 in order to electrically connect this electromagnetic shielding cover 101.This second substrate 103 has one second upper surface 110 and one second lower surface 111, and this second upper surface 110 is provided with one second chip 112.This electromagnetic shielding cover 101 is located at this second chip, 112 tops, and this second chip 112 is placed in first room 105 of this electromagnetic shielding cover 101, separates this first chip 108 and second chip 112 by this.This second substrate 103 further is provided with at least one via 114, and it runs through this second substrate 103, and this electromagnetic shielding cover 101 forms with earthed circuit (not shown) by this via 114 and electrically connects.These several conducting Metal Ball 113 are arranged at first lower surface 107 of this first substrate 102 and second lower surface 111 of this second substrate 103.The conducting Metal Ball 113 that is positioned at this first lower surface 107 is in order to electrically connect the interlock circuit (not shown) on this first substrate 102 and this second substrate 103,113 of conducting Metal Ball that are positioned at this second lower surface 111 are in order to form the I/O end of this second substrate 103, with the I/O signal of telecommunication.This grounded metal ball 115 is positioned at second lower surface 111 of this second substrate 103, in order to the via 114 that electrically connects this second substrate 103.This ground connection projection 116 is exposed in second room 109 of this first substrate 102, to electrically connect this electromagnetic shielding cover 101.This electromagnetic shielding cover 101 can connect the earthed circuit (not shown) of first chip 108 by this ground connection projection 116, and connects other earthed circuit (not shown) by this via 114 and this grounded metal ball 115.This first substrate 102 is located on this second substrate 103 towards the mode of this second upper surface 110 is folded with this first lower surface 107, thereby the semiconductor package of composition first embodiment of the invention, wherein this first chip 108 and second chip, 112 essence are the relativeness of piling up (Stack).
For realizing the purpose of electromagnetic shielding, this electromagnetic shielding cover 101 is cover of meter hood or nonmetal cover cap.If cover of meter hood, its material can be selected copper, aluminium, silver, golden contour conductive metal.If nonmetal cover cap then can be chosen in and form a metal maskant on its at least one surface.In another embodiment, this nonmetal cover cap comprises non-metallic substrate and metal blending particle.The height essence of this electromagnetic shielding cover 101 is equal to or less than the height summation of the Metal Ball 113 of this first substrate 102 and this first lower surface 107.One heat dissipating layer 117 further optionally is set on this electromagnetic shielding cover 101, and it is between this first chip 108 and electromagnetic shielding cover 101, in order to improve radiating efficiency.The preferable heat-conducting cream that is chosen as of this heat dissipating layer 117, for example heat conduction elargol etc.
Fig. 2 is for having the schematic diagram of the semiconductor package of electromagnetic shielding cover according to one of second embodiment of the invention.
The semiconductor package of this second embodiment comprises an electromagnetic shielding cover 201, one first substrate 202, one second substrate 203, several conducting Metal Ball 213 and several grounded metal balls 215.
This electromagnetic shielding cover 201 is concaved with one first room 205.This first substrate 202 has one first upper surface 206 and one first lower surface 207, and this first lower surface 207 is provided with at least one first chip 208.First lower surface 207 of this first substrate 202 forms one second room 209 in addition, and in order to ccontaining this electromagnetic shielding cover 201 of part, this second room 209 can run through or not run through this first substrate 202.This second substrate 203 has one second upper surface 210 and one second lower surface 211.This second upper surface 210 is provided with one second chip 212.This electromagnetic shielding cover 201 is located at this second chip, 212 tops, and this second chip 212 is placed in first room 205 of this electromagnetic shielding cover 201, separates this first chip 208 and second chip 212 by this.This second substrate 203 further is provided with at least one via 214, and it runs through this second substrate 203.These several grounded metal balls 215 are positioned at second lower surface 211 of second substrate 203, in order to the via 214 that electrically connects this second substrate 203.This electromagnetic shielding cover 201 is connected other earthed circuit (not shown) by this via 214 with this grounded metal ball 215.These several conducting Metal Ball 213 are arranged at first lower surface 207 of this first substrate 202 and second lower surface 211 of this second substrate 203.The conducting Metal Ball 213 that is positioned at this first lower surface 207 is in order to electrically connect the interlock circuit (not shown) on this first substrate 202 and this second substrate 203,213 of conducting Metal Ball that are positioned at this second lower surface 211 are in order to form the I/O end of this second substrate 203, with the I/O signal of telecommunication.This first substrate 202 is located on this second substrate 203 towards the mode of this second upper surface 210 is folded with this first lower surface 207, thereby the semiconductor package of composition second embodiment of the invention, wherein this first chip 208 and second chip, 212 essence are side by side the relativeness of (Side by side).
In order to improve radiating efficiency, can expose these electromagnetic shielding covers 201 by this second room 209, and several fins 218 can optionally be set on the end face of this electromagnetic shielding cover 201, in addition to improve radiating efficiency.This fin 218 protrudes into the top of first upper surface 206 of this first substrate 202.
The difference of this second embodiment and first embodiment is: first chip 108 of this first embodiment is arranged on first upper surface 106 of this first substrate 102, and first chip 208 of this second embodiment is arranged on first lower surface 207 of this first substrate 202, and this second embodiment further is provided with several fins 218 at the end face of this electromagnetic shielding cover 201, to improve radiating efficiency.
The present invention utilizes the above-mentioned semiconductor package with electromagnetic shielding cover, not only can provide effectiveness, prevent to interfere with each other between its chipset, and this electromagnetic shielding cover structure can't increase the vertical height of piling up of encapsulation, simultaneously also can be further by setting up heat dissipating layer or fin improves radiating efficiency.
Claims (13)
1. semiconductor package with electromagnetic shielding cover comprises:
One first substrate has one first upper surface and one first lower surface, and described first upper surface is provided with one first chip;
One second substrate has one second upper surface and one second lower surface, and described second upper surface is provided with one second chip; And
Several Metal Ball, be arranged at described first lower surface of described first substrate and described second lower surface of described second substrate, described several Metal Ball comprise several conducting Metal Ball, described conducting Metal Ball is respectively in order to electrically connecting described first substrate and described second substrate, and the outside I/O end that forms described second substrate;
It is characterized in that: described semiconductor package further comprises an electromagnetic shielding cover, and described electromagnetic shielding cover is concaved with one first room; Described first lower surface of described first substrate forms one second room in order to the ccontaining described electromagnetic shielding cover of part; Described first substrate is folded to be located on described second substrate, and described electromagnetic shielding cover is located at described second chip top, and described second chip is placed in first room of described electromagnetic shielding cover, separates described first and second chip by this.
2. semiconductor package as claimed in claim 1 is characterized in that: described second room runs through described first substrate.
3. semiconductor package as claimed in claim 1 or 2 is characterized in that: described second substrate is provided with at least one via, and described via runs through described second substrate, and described electromagnetic shielding cover forms ground connection by described via.
4. semiconductor package as claimed in claim 3 is characterized in that the Metal Ball of second lower surface of described second substrate comprises several grounded metal balls, and described grounded metal ball electrically connects the via of described second substrate.
5. semiconductor package as claimed in claim 1 or 2 is characterized in that: described electromagnetic shielding cover is a cover of meter hood.
6. semiconductor package as claimed in claim 1 or 2 is characterized in that: described electromagnetic shielding cover is nonmetal cover cap, and its at least one surface has a metal maskant.
7. semiconductor package as claimed in claim 1 or 2 is characterized in that: described electromagnetic shielding cover is nonmetal cover cap, and it comprises non-metallic substrate and metal blending particle.
8. semiconductor package as claimed in claim 1 or 2 is characterized in that: described first chip is provided with at least one ground connection projection to electrically connect described electromagnetic shielding cover.
9. semiconductor package as claimed in claim 1 or 2 is characterized in that: the height of described electromagnetic shielding cover is equal to or less than the height summation of the Metal Ball of described first substrate and described first lower surface.
10. semiconductor package as claimed in claim 1 is characterized in that: described electro-magnetic shielding cover covers has a heat dissipating layer, and described heat dissipating layer is between described first chip and described electromagnetic shielding cover, in order to improve radiating efficiency.
11. semiconductor package as claimed in claim 2 is characterized in that: described second room exposes described electromagnetic shielding cover, to improve radiating efficiency.
12. semiconductor package as claimed in claim 11 is characterized in that: the end face at described electromagnetic shielding cover further is provided with several fins, to improve radiating efficiency.
13. semiconductor package as claimed in claim 12 is characterized in that: the fin of described electromagnetic shielding cover protrudes into the top of first upper surface of described first substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101672773A CN101150123B (en) | 2007-10-31 | 2007-10-31 | Semiconductor encapsulation structure with electromagnetic shielding cover |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101672773A CN101150123B (en) | 2007-10-31 | 2007-10-31 | Semiconductor encapsulation structure with electromagnetic shielding cover |
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| Publication Number | Publication Date |
|---|---|
| CN101150123A true CN101150123A (en) | 2008-03-26 |
| CN101150123B CN101150123B (en) | 2010-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007101672773A Active CN101150123B (en) | 2007-10-31 | 2007-10-31 | Semiconductor encapsulation structure with electromagnetic shielding cover |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347286A (en) * | 2011-10-09 | 2012-02-08 | 常熟市广大电器有限公司 | Anti-interference chip packaging structure |
| CN102656961A (en) * | 2009-12-10 | 2012-09-05 | 罗伯特·博世有限公司 | Electronic control device |
| WO2013029533A1 (en) * | 2011-09-02 | 2013-03-07 | 华为终端有限公司 | Chip-packaging structure, packaging method and electronic device |
| CN104320930A (en) * | 2014-09-30 | 2015-01-28 | 深圳市理邦精密仪器股份有限公司 | Layout structure of laminated type ultrasonic module |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004111656A (en) * | 2002-09-18 | 2004-04-08 | Nec Electronics Corp | Semiconductor device and manufacturing method of semiconductor device |
| KR100639701B1 (en) * | 2004-11-17 | 2006-10-30 | 삼성전자주식회사 | Multi chip package |
| JP4408832B2 (en) * | 2005-05-20 | 2010-02-03 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| KR100714917B1 (en) * | 2005-10-28 | 2007-05-04 | 삼성전자주식회사 | Chip stack structure interposing shield plate and system in package comprising the same |
-
2007
- 2007-10-31 CN CN2007101672773A patent/CN101150123B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102656961A (en) * | 2009-12-10 | 2012-09-05 | 罗伯特·博世有限公司 | Electronic control device |
| US8929078B2 (en) | 2009-12-10 | 2015-01-06 | Robert Bosch Gmbh | Electronic control device |
| CN102656961B (en) * | 2009-12-10 | 2015-11-25 | 罗伯特·博世有限公司 | Control electronics |
| WO2013029533A1 (en) * | 2011-09-02 | 2013-03-07 | 华为终端有限公司 | Chip-packaging structure, packaging method and electronic device |
| CN102347286A (en) * | 2011-10-09 | 2012-02-08 | 常熟市广大电器有限公司 | Anti-interference chip packaging structure |
| CN104320930A (en) * | 2014-09-30 | 2015-01-28 | 深圳市理邦精密仪器股份有限公司 | Layout structure of laminated type ultrasonic module |
| CN104320930B (en) * | 2014-09-30 | 2017-08-08 | 深圳市理邦精密仪器股份有限公司 | A kind of stacked ultrasonic module layout structure |
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| Publication number | Publication date |
|---|---|
| CN101150123B (en) | 2010-06-02 |
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