CN101149974A - Non-volatile memory production method, writing method and reading method - Google Patents
Non-volatile memory production method, writing method and reading method Download PDFInfo
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- CN101149974A CN101149974A CNA2007100889913A CN200710088991A CN101149974A CN 101149974 A CN101149974 A CN 101149974A CN A2007100889913 A CNA2007100889913 A CN A2007100889913A CN 200710088991 A CN200710088991 A CN 200710088991A CN 101149974 A CN101149974 A CN 101149974A
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Abstract
The method for making a non-volatile memory includes: a memory to be coded is provided, which has a plurality of memory banks to be coded which are arranged in array and on which an impedance layer is implanted. A shield is set on the memory. The number of the memory banks at lower part of the opening on the shield is less than that of the rest memory banks. The shield forming a pattern-type implanting layer is implanted in ion into the exposed memory banks to define a first memory bank and a second memory bank which has a second-place state and a first-place state respectively. After that the memory is reversely defined to make the first memory bank and the second memory bank have first-place state and second-place state respectively.
Description
Technical field
The present invention relates to a kind of manufacture method, wiring method and read method of nonvolatile memory, and be particularly related to a kind of manufacture method that causes the nonvolatile memory of ion graft failure because of foreign matter that reduces, and the wiring method and the corresponding read method that can reduce the sequencing time of nonvolatile memory.
Background technology
Along with the arriving in digital and electronic epoch, also ardent day by day for the demand of data storage medium, therefore for can also constantly seeking the mode that improves with the semiconductor technology of a large amount of mediums of cheap cost production.
In the medium of being produced with semiconductor technology, (non-volatile memory, NVM) range of application is the most extensive not need electric power can keep the nonvolatile memory of state data memory.Nonvolatile memory can divide into ion implant definition of data shielded read-only memory (maskread-only memory, MROM); And can a secondary program (one time program, OTP) and repeatedly program (multi-time program, MTP) storer, for example the ROM-BIOS of computing machine (basic input/output system, BIOS).And the user can carry out repeatedly the storer of program-erase, for example flash memory (flash memory).Wherein, shielded read-only memory and a program storage can low cost be produced in a large number because technology is comparatively simple, therefore are fit to a large amount of software product that duplicates, for example the game card caskets produced of needs.
With the shielded read-only memory is example, and its program coding mode is so that ion is implanted a waiting coding memory of finishing in advance.As shown in Figure 1, it shows the partial structurtes synoptic diagram of waiting coding memory.Waiting coding memory 10 has the bit line 1 of many arrangements parallel to each other, and vertical with bit line 1 and be arranged on the character line 2 of top.Character line 2 between any two bit lines 1 is the position of memory bank 3 to be encoded, and the mode of can ion implanting defines different position states, will desire coded program and be recorded on the waiting coding memory 10.
Yet, because implanting, ion must expose the memory bank to be encoded 3 that desire is implanted, might be because foreign matter hides resistance or implants the inaccurate graft failure that causes of impedance layer contraposition.Therefore under the more relatively situation of the memory bank to be encoded that exposes,, also improves relatively graft failure because of causing the probability of defective.
In addition, the present repeatedly program storage that once reaches when data meta state 0 too much the time, needs the expensive time carry out electric sequencing.Add memory bank that residue not have use when too much, also need spended time that the memory bank program of correspondence is turned to 0, waste many time costs virtually.
Summary of the invention
In view of this, the invention provides a kind of manufacture method, read method and wiring method of nonvolatile memory, is with memory bank to be encoded that changes implantation and the reverse definition that cooperates storer, improves the yield rate that nonvolatile memory is produced.Be applied in simultaneously in the sequencing of nonvolatile memory, can also reduce the required production time.
According to the present invention, a kind of manufacture method of nonvolatile memory is proposed.At first, provide a waiting coding memory, have the memory bank a plurality of to be encoded of lining up array.Then, form one and implant impedance layer on waiting coding memory.Then, be provided with one and be shielded from the waiting coding memory, shielding has a plurality of perforates, and the quantity of the part memory bank to be encoded of the below of perforate is less than the quantity of all the other memory banks to be encoded.Then, in implanting impedance layer, implant impedance layer with the shielding define pattern to form a patterning.Patterning is implanted impedance layer and is had a plurality of notches, the memory bank to be encoded of notch exposed portions serve.Then, ion is implanted the memory bank to be encoded that exposes, the memory bank to be encoded of implanting ions is first memory bank to define not, and the definition implanting ions memory bank to be encoded be second memory bank, first memory bank and second memory bank have one second state and one first state respectively.Then, oppositely define waiting coding memory, make first memory bank and second memory bank have first state and second state respectively.
According to the present invention, the manufacture method of another kind of nonvolatile memory is proposed.At first, provide a waiting coding memory, have the memory bank a plurality of to be encoded of lining up array.Then, calculate one first state and one second amount of state in the desire coded program.Then, when first amount of state during, provide a shielding greater than second amount of state.Shielding has a plurality of perforates.The quantity of perforate is identical with second amount of state.Then, form one and implant impedance layer on waiting coding memory.Then, in implanting impedance layer, implant impedance layer with the shielding define pattern to form a patterning.Patterning is implanted impedance layer and is had a plurality of notches, the memory bank to be encoded of notch exposed portions serve.Then, ion is implanted the memory bank to be encoded that exposes, and the memory bank to be encoded of implanting ions is first memory bank to define not, and the memory bank to be encoded of definition implanting ions is second memory bank.First memory bank and second memory bank have one second state and one first state respectively.Then, oppositely define waiting coding memory, make first memory bank and second memory bank have first state and second state respectively.
According to the present invention, a kind of wiring method of nonvolatile memory is proposed, comprise the following steps: that at first a waiting coding memory is provided, and the memory bank of waiting coding memory has first state and second state respectively after sequencing with before the sequencing.Then, calculate first state and second amount of state in the desire coded program data.Then, when first amount of state during greater than second amount of state, oppositely the coded program data are desired in definition.Then, will desire the coded program data writes in the waiting coding memory.
According to the present invention, a kind of read method of nonvolatile memory is proposed, be used to read waiting coding memory as in the previous paragraph, comprise the following steps.At first, read desire coded program data.Then, check whether desire the coded program data oppositely defines.Then, be oppositely definition if desire the coded program data, then oppositely once back output of definition again.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows the partial structurtes synoptic diagram of waiting coding memory;
Fig. 2 shows the manufacture method process flow diagram of nonvolatile memory of the present invention;
Fig. 3 A shows the partial structurtes synoptic diagram of waiting coding memory;
Fig. 3 B shows the vertical view of shielding;
Fig. 3 C shows has the vertical view that patterning is implanted the waiting coding memory of impedance layer;
Fig. 3 D shows among Fig. 3 C the sectional view along profile line AA ';
Fig. 4 shows the read functions calcspar of nonvolatile memory of the present invention;
Fig. 5 A shows the generation circuit diagram of the control signal of first kind of multiplexer of the present invention;
Fig. 5 B shows the generation circuit diagram of the control signal of second kind of multiplexer of the present invention;
Fig. 6 shows writing of nonvolatile memory of the present invention and reads the circuit function synoptic diagram;
Fig. 7 shows the process flow diagram that writes of nonvolatile memory of the present invention; And
Fig. 8 shows the process flow diagram that reads of nonvolatile memory of the present invention.
The reference numeral explanation
1,110: bit line
2,120: character line
3,130: memory bank to be encoded
10,100: waiting coding memory
20: shielding
21,22,23: perforate
130a: first memory bank
130b: second memory bank
140: insulation course
150: ground
210～270: step
300: patterning is implanted impedance layer
310,320,330: notch
400,600: nonvolatile memory
410,602: the non-volatile memories volume array
420,604: induction amplifier
425: phase inverter
430: multiplexer
440,650: output port
610: the 1 group of data input channels
612: the 1 buffer registers
613: the 1 input multiplexers
614: the 1 input inverters
620: the n group data input channels
622: the n buffer registers
623: the n input multiplexers
624: the n input inverters
NM0, NM1:N type metal oxide semiconductor
PM0, PM1:P type metal oxide semiconductor
630: the 1 group of data delivery channels
632: the 1 output multiplexers
634: the 1 output phase inverters
640: the n group data delivery channels
642: the n output multiplexers
644: the n output phase inverters
Embodiment
Please refer to Fig. 2, it shows the manufacture method process flow diagram of nonvolatile memory of the present invention.And please be simultaneously with reference to the 3A～Fig. 3 D.Fig. 3 A shows the partial structurtes synoptic diagram of waiting coding memory.Fig. 3 B shows the vertical view of shielding.Fig. 3 C shows has the vertical view that patterning is implanted the waiting coding memory of impedance layer.Fig. 3 D shows among Fig. 3 C the sectional view along profile line AA '.
At first, shown in step 210, and, provide a waiting coding memory 100 with reference to Fig. 3 A.Waiting coding memory 100 has the bit line 110 of many arrangements parallel to each other, and vertical with bit line 110 and be arranged at the character line 120 of top.Be the memory bank to be encoded 130 of lining up array with character line 120 staggered places between any two bit lines 110, have nine memory banks 130 to be encoded in the present embodiment.
Then, shown in step 220, calculate and desire first state and second amount of state in the coded program.First state for example is that 0, the second state for example is 1 in the present embodiment.Certainly, also first state of definable is that 1, the second state is 0, the invention is not restricted to this.In the present embodiment, it is more to suppose to desire in the coded program first amount of state, and the record of first state 0 need be implanted memory bank 130 to be encoded with ion and carries out sequencing (program).Be to be that example is done explanation in the present embodiment with boron implant (boron).
Then, shown in step 230,, just to carry out bank number that ion implants more for a long time, a shielding is provided when the quantity of first state 0 during greater than the quantity of second state 1.Please refer to Fig. 3 B, shielding 20 has three perforates 21,22,23, a respectively corresponding memory bank 130 to be encoded, and the quantity of perforate is identical with the quantity and the position of second state 1 desiring coded program.That is to say, ion is implanted in the memory bank to be encoded of corresponding second state 1 desiring coded program originally, but not in the memory bank to be encoded of corresponding first state 0 desiring coded program originally.
Then, shown in step 240, form one and implant the impedance material layer on waiting coding memory 100.
Then, shown in step 250, in implanting the impedance material layer, implant impedance layer 300 to form a patterning with the shielding define pattern.Please refer to Fig. 3 C, patterning is implanted impedance layer 300 and is had notch 310,320,330, the memory bank to be encoded 130 of notch 310,320,330 exposed portions serve.That is to say, cover, do not expose and carry out ion and implant and will not carry out memory bank that ion implants originally with originally carrying out the memory bank that ion implants.
Then, shown in step 260, and with reference to Fig. 3 D.Be embedded with multiple bit lines 110 on the ground 150 of waiting coding memory 100, separate with insulation course 140 between character line 120 and the ground 150.So-called memory bank is 110 of two bit lines, is positioned at the passage on the ground 150, and ion passes character line 120 and squeezes in the ground 150 and define.Ion is implanted the memory bank to be encoded 130 that exposes, and the memory bank to be encoded 130 of implanting ions is the first memory bank 130a to define not, and the memory bank to be encoded 130 of definition implanting ions is the second memory bank 130b.And relatively when the conducting first memory bank 130a and the second memory bank 130b, by the first memory bank 130a and first current value of the second memory bank 130b and the size of second current value and a reference current value, have one second state 1 and one first state 0 respectively respectively to define the first memory bank 130a and the second memory bank 130b.First current value is greater than reference current value in the present embodiment, and second current value is less than reference current value.
Then, shown in step 270, because the position state of defined memory bank is just the opposite with the desired position of desire coded program state, so oppositely define waiting coding memory 100.That is to say that when defining first current value greater than reference current value, the first memory bank 130a has first state; Second current value is during less than reference current value, and the second memory bank 130b has second state.Make win memory bank 130a and the second memory bank 130b have first state 0 and second state 1 respectively.The position state that this moment, waiting coding memory 100 was write down is promptly identical with the desired position of desire coded program state.
Yet, in step 230, if the quantity of desiring first state 0 in the coded program during less than the quantity of second state 1, owing to need ion to implant the negligible amounts of first state 0 of definition, provides a secondary shielding.Secondary shielding has second perforate, and the quantity of second perforate is identical with the quantity of first state 0.Then, in implanting the impedance material layer, implant impedance layer with the secondary shielding define pattern to form one second patterning.Second patterning is implanted impedance layer and is had second notch, the memory bank to be encoded of the second notch exposed portions serve.Then, ion is implanted the memory bank to be encoded 130 expose, is the 3rd memory bank with the memory bank to be encoded of definition implanting ions, and defines not that the memory bank to be encoded of implanting ions is the 4th memory bank.And relatively when conducting the 3rd memory bank and the 4th memory bank, by the 3rd memory bank and the 3rd current value of the 4th memory bank and the size of the 4th current value and reference current value, have first state 0 and second state 1 respectively respectively to define the 3rd memory bank and the 4th memory bank.Because the position state of defined memory bank is identical with the desired position of desire coded program state, so need oppositely not define.
Usually know the knowledgeable yet the technical field under the present invention has, technology of the present invention as can be known is not limited thereto.In the step 260 relatively in the step of first current value and second current value, also can be first current value during less than reference current value, the first memory bank 130a has second state 1; Second current value is during greater than reference current value, and the second memory bank 130b has first state 0.Therefore oppositely define in the step of waiting coding memory 100 in step 270, when defining first current value less than reference current value, the first memory bank 130a has first state 0; Second current value is during greater than reference current value, and the second memory bank 130b has second state 1.Hence one can see that, and first state and second state are 0 or 1, and the magnitude relationship of first current value and second current value and reference current value, relevant with the ion of implanting, and is not particularly limited in the present invention.
In addition, do explanation though present embodiment is example with the shielded read-only memory, the scope of utilizing of the present invention is not limited thereto.The present invention also can be used in the formation that contact hole (contact hole) is fastened plug, has the effect that promotes yield rate equally.Utilize mode of the present invention that the protected type storer is carried out ion and implant,, can effectively reduce because foreign matter blocks the probability that causes graft failure and produce the data definition mistake because it is less to expose the memory bank proportion of implanting.
The described reverse definition of the step 270 of leading portion such as Fig. 2 can be reached by circuit design.Please refer to Fig. 4, it shows the read functions calcspar of nonvolatile memory of the present invention.Nonvolatile memory 400 comprises non-volatile memories volume array 410 and induction amplifier 420, and the signal that non-volatile memories volume array 410 is read amplifies back output via induction amplifier 420.Nonvolatile memory 400 can be shielded read-only memory (mask read-only memory, Mask ROM), a secondary program (one-time program, OTP) storer, program (multi-time program, MTP) storer and the flash memory (flash memory) that can carry out repeatedly program-erase repeatedly.As shown in Figure 4,, then can follow path P 2, export output port 440 to after selecting via multiplexer (MUX) 430 with position definition status originally if desire the coded program data originally not through oppositely definition; If desired the oppositely definition once originally of coded program data originally, then can follow path P 1, after oppositely defining once more through phase inverter 425, via exporting output port 440 to after multiplexer (MUX) 430 selections.
As for the selection of path P 1, P2, be control signal V by multiplexer 430
aDecide.Please refer to Fig. 5 A and Fig. 5 B, it shows the generation circuit diagram of the control signal of first kind and second kind multiplexer of the present invention respectively.Shown in Fig. 5 A, circuit polyphone P-type mos (the metal oxide semiconductor in left side, MOS) PM0 and N type metal oxide semiconductor NM0, the circuit polyphone P-type mos PM1 and the N type metal oxide semiconductor NM1 on right side.This kind structure is to decide V by sequencing N type metal oxide semiconductor NM0 or NM1
aOutput voltage.For example when sequencing NM0, though NM0 and NM1 connect high-pressure side V at grid respectively
Cc, but NM0 has higher threshold voltage because of sequencing can't with earth terminal GND conducting.Relative, NM1 can with earth terminal GND conducting, so V
aCurrent potential identical with earth terminal GND.And because the grid of PM0 is coupled to the circuit on right side, so grid potential is identical with earth terminal GND, makes the PM0 conducting and the current potential and the high-pressure side V of circuit on the left of making
CcIdentical.And the grid of PM1 couples with the left side circuit, so the grid potential of PM1 and high-pressure side V
CcIdentical, make the grid of PM1 with pathway closure to suppress electric current.Thus, can avoid the right side circuit to continue to produce electric current and cause loss.Relative, V
aOutput high-pressure side V
CcCurrent potential the time, sequencing NM1 then.
Shown in Fig. 5 B, its assembly is identical with Fig. 5 A but mode of connection is different, and this kind structure is to decide V by sequencing P-type mos PM0 or PM1
aOutput voltage.For example when sequencing PM0, though PM0 and PM1 connect earth terminal GND at grid respectively, PM0 because sequencing has higher threshold voltage can't with earth terminal GND conducting.Relative, PM1 can with high-pressure side V
CcConducting, so V
aCurrent potential and high-pressure side V
CcIdentical.And because the grid of NM0 is coupled to the circuit on right side so grid potential and high-pressure side V
CcIdentical, make the NM0 conducting and make the left side circuit current potential identical with earth terminal GND.And the circuit in the grid of NM1 and left side couples, so the grid potential of NM1 is identical with earth terminal GND, make the grid of NM1 with pathway closure to suppress electric current.Thus, can avoid the right side circuit to continue to produce electric current and cause loss.Relative, V
aDuring the current potential of output earth terminal GND, sequencing PM1 then.
Therefore by the circuit structure that adopts Fig. 5 A or Fig. 5 B, can control V by the different MOS assembly of sequencing
aExport different current potentials, provide nonvolatile memory 400 to select different path output datas.
Propose to be used for writing of OTP, MTP and flash memory and read method please refer to Fig. 6 as for the present invention, it shows writing of nonvolatile memory of the present invention and reads the circuit function synoptic diagram.And please be simultaneously with reference to Fig. 7, it shows the process flow diagram that writes of nonvolatile memory of the present invention.At first, shown in step 701, provide a waiting coding memory 600.Waiting coding memory 600 comprises non-volatile memories volume array 602 and induction amplifier 604, and non-volatile memories volume array 602 has one first state and one second state respectively after sequencing with before the sequencing, refers to 0 in this embodiment respectively with 1.
Then, shown in step 702, the quantity of first state 0 and second state 1 in the calculating one desire coded program data.This function can be write as and be integrated in the circuit structure of waiting coding memory 600 by program language.
Then, shown in step 703, whether the quantity of judging first state 0 is greater than the quantity of second state 1.When the quantity of first state 0 during greater than the quantity of this second state 1, shown in step 704, oppositely the coded program data are desired in definition.Then, shown in step 705, will desire the coded program data and write in the waiting coding memory 600.Relative, if in the step 703, the quantity of first state 0 shown in step 706, keeps original position state to define and writes in the waiting coding memory 600 during less than the quantity of second state 1.
Usually know the knowledgeable but the technical field under the present invention has, technology of the present invention as can be known is not limited thereto.Desire coded program data more can be divided into the 1st to n and organize, for example in the present embodiment, waiting coding memory 600 more comprises n data input channel, distinguishing desire coded program data according to the data input channel that passes through is the 1st to n group, only draws the 1st group of input data channel 610 and n group input data channel 620 among Fig. 6 for simplicity.Each organizes data channel shown in step 702, calculates respectively by the 1st to n group of the 1st to n data channel and desires in the coded program data quantity of the quantity of first state 0 and second state 1.Each data channel of waiting coding memory 600 more comprises and comprises an input multiplexer (MUX) respectively, for example the 1st input multiplexer 613 of Fig. 6 is to n input multiplexer 623, in order to shown in step 703, according to the quantity of first state 0 and second state 1, whether the desire coded program data that write with decision need oppositely definition.The 1st input multiplexer 613 to n input multiplexer 623 respectively by control voltage V
In1 to V
InN controls, V
In1 to V
InN can adopt the circuit structure as 5A figure or Fig. 5 B to produce, and will adopt path P with determination data channel 610
In1_1 or P
In1_2, and data channel 620 will adopt path P
InN_1 or P
InN_2.
When each the 1st to n group is desired in coded program data, the quantity of first state 0 is during greater than the quantity of second state 1, then shown in step 704, use as the 1st input inverter 614 of Fig. 6 to n input inverter 624, oppositely definition desire coded program data.Each group is desired coded program data shown in step 705 then, respectively via the 1st buffer register 612 to the accumulation of n buffer register certain write data after, in the desire coded program data write-once waiting coding memory 600 with accumulation.Relative, when each the 1st to n group is desired in coded program data, the quantity of first state 0 shown in step 706, keeps original position state to define and writes in the waiting coding memory 600 during less than 1 quantity of second state.
By the writing mode that present embodiment proposes, can make electric program change into the time decreased that second state needs, improve the production efficiency of storer.In addition, after more reverse definition waiting coding memory 600 writes and desires the coded program data in the present embodiment, the position state of remaining memory bank in the non-volatile memories volume array 602, this function can be by being provided with other one group of input multiplexer, oppositely defines in order to the position state of the memory bank that whole non-volatile memories volume array 602 is remaining.Because untapped memory bank must be programmed into 0 through electric, if then can significantly save the required time of sequencing through reverse definition.When especially remaining memory bank ratio is very high, more can make the production time of storer significantly reduce, promote production efficiency.
Below introduce the method for reading non-volatile storage 600.Please refer to Fig. 8, it shows the process flow diagram that reads of nonvolatile memory of the present invention, and asks the assembly label of while with reference to Fig. 6.Shown in step 801, the desire coded program data in the reading non-volatile bank array are via exporting behind induction amplifier 604 amplifying signals.
Then, shown in step 802, check the whether oppositely definition of these desire coded program data.
Then, shown in step 803, be oppositely definition if desire the coded program data, then oppositely once back output of definition again.Do not have reverse definition if desire the coded program data, then shown in step 804, keep original position state definition output.
Imported if divide into n group data channel originally, and relatively also needed to export, only drew the 1st group of output data channel 630 and n group output data channel 640 among Fig. 6 for simplicity with n group data channel with present embodiment.Therefore, shown in step 802, check each the 1st to n group desire coded program data was write fashionable whether once oppositely the definition originally, and this function can also be integrated into the circuit that reads of nonvolatile memory 600 by the program writing.If it is oppositely to define that arbitrary the 1st to n group is desired the coded program data, shown in step 803, oppositely definition once exports output port 650 to after each group desire coded program data.For example in the 1st group of data delivery channel 630 and the n group data delivery channel 640, follow path P
Out1_2 and P
OutN_2 is undertaken oppositely by the 1st output phase inverter 634 and n output phase inverter 644.If before arbitrary the 1st to n group is desired the coded program data, do not have reverse definition process mistake, then keep each group to desire the original position state definition of coded program data and export output port 650 to.For example in the 1st group of data delivery channel 630 and the n group data output 640, follow path P
Out1_1 and P
OutN_1.As for the selection in path, be to decide by the output multiplexer in each group data channel, for example output multiplexer 632 of the 1st in the data channel 630 and 640 and n export multiplexer 642.The control voltage V of the 1st output multiplexer 632 and n output multiplexer 642
Out1 and V
OutN can adopt the circuit as 5A figure or Fig. 5 B to produce equally.In addition, if also oppositely definition once of remaining memory bank originally, then oppositely define once more waiting coding memory 600 write desire the coded program data after, export behind the position state of non-volatile memories volume array 602 residue memory banks.This function can be by being provided with other one group of output multiplexer, in order to the position state oppositely definition back output once more of the memory bank that whole non-volatile memories volume array 602 is remaining, is the data kenel of original definition.
The manufacture method of the disclosed nonvolatile memory of the above embodiment of the present invention, be in the bank number to be encoded that ought need ion to implant more for a long time, the memory bank to be encoded that originally need not implant is carried out ion implant, make memory bank to be encoded implant the position state opposite with desiring coded program.Then again that the definition of waiting coding memory is reverse, promptly obtain and the storer of desiring coded program identical bits state.Because the bank number to be encoded exposed is less, can reduces because of foreign matter and stop or implant the probability that the impedance layer misalignment causes graft failure.Therefore the present invention does not need to increase extra step or significantly changes technology, can reduce because of foreign matter blocks or implant the probability that the impedance layer misalignment causes the ion graft failure, promotes the yield rate that nonvolatile memory is produced.And the wiring method of nonvolatile memory proposed by the invention and read method can be saved write time of nonvolatile memory greatly, increase the production efficiency of storer.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (10)
1. the manufacture method of a nonvolatile memory comprises:
(a) provide a waiting coding memory, have the memory bank a plurality of to be encoded of lining up array;
(b) form one and implant the impedance material layer on this waiting coding memory;
(c) be provided with one and be shielded from this waiting coding memory, this shielding has a plurality of perforates, and the quantity of the described memory bank to be encoded of part of the below of described perforate is less than the quantity of all the other described memory banks to be encoded;
(d) implant the impedance material layer with this shielding define pattern in this, implant impedance layer to form a patterning, this patterning is implanted impedance layer and is had a plurality of notches, the memory bank described to be encoded of described notch exposed portions serve;
(e) ion is implanted the memory bank described to be encoded that exposes, the memory bank described to be encoded of implanting ions is a plurality of first memory banks to define not, and the definition implanting ions memory bank described to be encoded be a plurality of second memory banks, described first memory bank and described second memory bank have one second state and one first state respectively; And
(f) oppositely define this waiting coding memory, make described first memory bank and described second memory bank have this first state and this second state respectively.
2. manufacture method as claimed in claim 1 more comprises:
When (g) comparing described first memory bank of conducting and described second memory bank, the size of one first current value and one second current value and the reference current value by described first memory bank and described second memory bank has one second state and one first state respectively to define described first memory bank and described second memory bank respectively.
3. manufacture method as claimed in claim 2, wherein, in step (g), this first current value is greater than this reference current value, and this second current value is less than this reference current value.
4. the manufacture method of a nonvolatile memory comprises:
(a) provide a waiting coding memory, have the memory bank a plurality of to be encoded of lining up array;
(b) calculate one first state and one second amount of state in the desire coded program;
(c) when this first amount of state during greater than this second amount of state, provide a shielding, this shielding has a plurality of perforates, and second amount of state of the quantity of described perforate and this is identical;
(d) form one and implant the impedance material layer on this waiting coding memory;
(e) implant the impedance material layer with this shielding define pattern in this, implant impedance layer to form a patterning, this patterning is implanted impedance layer and is had a plurality of notches, the memory bank described to be encoded of described notch exposed portions serve;
(f) ion is implanted the memory bank described to be encoded that exposes, the memory bank described to be encoded of implanting ions is a plurality of first memory banks to define not, and the definition implanting ions memory bank described to be encoded be a plurality of second memory banks, described first memory bank and described second memory bank have one second state and one first state respectively; And
(g) oppositely define this waiting coding memory, make described first memory bank and described second memory bank have this first state and this second state respectively.
5. manufacture method as claimed in claim 4 more comprises:
When (h) comparing described first memory bank of conducting and described second memory bank, the size of one first current value and one second current value and the reference current value by described first memory bank and described second memory bank has one second state and one first state respectively to define described first memory bank and described second memory bank respectively.
6. manufacture method as claimed in claim 5, wherein, in step (h), this first current value is greater than this reference current value, and this second current value is less than this reference current value.
7. the wiring method of a nonvolatile memory comprises:
(a) provide a waiting coding memory, the memory bank of this waiting coding memory has one first state and one second state respectively after sequencing with before the sequencing;
(b) calculate one and desire this first state and this second amount of state in the coded program data;
(c) when this first amount of state during, oppositely define this desire coded program data greater than this second amount of state; And
(d) should desire the coded program data writes in this waiting coding memory.
8. wiring method as claimed in claim 7 more comprises:
(e) when this first amount of state during less than this second amount of state, the position state definition that keeps original writes in this waiting coding memory.
9. wiring method as claimed in claim 7, wherein, these desire coded program data are more divided into the 1st to n group, and step (b) more comprises:
(b1) calculating respectively the 1st to n is organized in the desire coded program data this first amount of state and this second amount of state;
Wherein, step (c) more comprises:
(c1) desire in the coded program data when the 1st to n group respectively, this first amount of state oppositely defines this group desire coded program data during greater than this second amount of state.
10. the read method of a nonvolatile memory is used to read this waiting coding memory as claimed in claim 22, comprising:
(a) read this desire coded program data;
(b) check the whether oppositely definition of these desire coded program data; And
(c) if this desires the coded program data is oppositely definition, then oppositely once back output of definition again.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201261A (en) * | 2010-03-22 | 2011-09-28 | 旺宏电子股份有限公司 | Multi-level cell programming speed improvement method based on programming level exchange |
| WO2013166974A1 (en) * | 2012-05-09 | 2013-11-14 | 无锡华润上华半导体有限公司 | Method for producing mrom memory based on opt memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201261A (en) * | 2010-03-22 | 2011-09-28 | 旺宏电子股份有限公司 | Multi-level cell programming speed improvement method based on programming level exchange |
| CN102201261B (en) * | 2010-03-22 | 2015-03-04 | 旺宏电子股份有限公司 | Programming device of multi-level cell semiconductor memory and programming method |
| WO2013166974A1 (en) * | 2012-05-09 | 2013-11-14 | 无锡华润上华半导体有限公司 | Method for producing mrom memory based on opt memory |
| US9397106B2 (en) | 2012-05-09 | 2016-07-19 | Csmc Technologies Fabi Co., Ltd. | Method for producing MROM memory based on OTP memory |
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