CN101149972B - FLASH memory chip with a plurality of separate operation memory space - Google Patents
FLASH memory chip with a plurality of separate operation memory space Download PDFInfo
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- CN101149972B CN101149972B CN2007101084678A CN200710108467A CN101149972B CN 101149972 B CN101149972 B CN 101149972B CN 2007101084678 A CN2007101084678 A CN 2007101084678A CN 200710108467 A CN200710108467 A CN 200710108467A CN 101149972 B CN101149972 B CN 101149972B
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Abstract
The FLASH memory chip having a plurality of storage spaces capable of operating independently comprise a processor, storage spaces and data wires. It is characterized in that: the storage space of the chip is divided into multiple areas; each of the control wires in the data wires respectively connecting with each area is independently connected with the processor to operate independently. The invention solves the problem of raised cost, much PCB space occupation, resource waste and difficult design in realizing on-line renewing of starting program and application program.
Description
Technical field
The present invention relates to the employed flicker of circuit design field (FLASH) memory chip, a kind of have a plurality of storage spaces, and certain space is operated and can not have influence on other storage space, the i.e. relatively independent FLASH memory chip of each storage space.
Background technology
Flicker (FLASH) memory chip possesses following characteristics: the data of the inside storage can remain unchanged under the situation of power down, and electrically erasable data allows read-write operation repeatedly.Therefore in circuit design field, come the needed start-up routine of storage of processor system electrifying startup (as BOOT program, bios program etc.) or other application program through FLASH storer commonly used.
Some processor system based on dynamically update, requirement such as online download, need upgrade the content in the FLASH memory chip that has write initialize routine or application program, but in order to occur under the unusual situation, effectively return back to former version, the content in the former FLASH memory chip also will remain and do not wiped or rewrite.Usually the practice is to use a plurality of FLASH memory chips, or carries out subregion in a FLASH chip.A plurality of FLASH memory chips, the one, the rising that can bring cost can take more PCB space in addition, can make troubles for the placement-and-routing of PCB; If carrying out subregion for a FLASH handles, so will be when BOOT starts by means of other control device, decipher for the processor reference-to storage space that powers on, to allow it read the start-up routine of specified partition, this can additionally increase design difficulty and other resource of waste, as the resource of EPLD etc., this software control partitioned method since fault or misoperation also can the content of original storage be damaged.
Summary of the invention
But technical matters solved by the invention is to provide a kind of FLASH memory chip that a plurality of independent operation storage spaces are arranged, and realizes that to solve start-up routine or the cost that the application program online updating was brought increase, problems such as the PCB space hold is more, the wasting of resources, difficult design.
In order to address the above problem, but the invention provides a kind of FLASH memory chip that a plurality of independent operation storage spaces are arranged, form by storage space and data line, it is characterized in that, the storage space of described chip is divided into a plurality of zones, and the control line that is connected with each zone is independently to be connected with processor respectively, carries out independent operation.
FLASH memory chip of the present invention, wherein, the data address bus that connects with each zone is shared.
FLASH memory chip of the present invention, wherein, the data address bus that is connected with each zone is respectively independently.
FLASH memory chip of the present invention, wherein, the data address bus that is connected with each zone is that part is independent, part is shared together.
FLASH memory chip of the present invention, wherein, described control line comprises Ce signal wire, Oe signal wire, Wr signal wire, Byte signal wire, Reset signal wire.
FLASH memory chip of the present invention, wherein, described data address bus comprises data line and address wire.
FLASH memory chip of the present invention, wherein, the storage space of described chip is divided into a plurality of zones, and the size in each zone can five equilibrium or five equilibrium not.
Adopt content of the present invention, compared with prior art, realization can be stored start-up routine or application program in the middle of circuit design, with the online updating (or being dynamic download) of realizing start-up routine or application program easily and reliably, and can reliably easily between new legacy code realize switching, solved defective of the prior art.
Description of drawings
But Fig. 1 is a kind of FLASH memory chip organization figure that a plurality of independent operation storage spaces are arranged of the present invention;
But Fig. 2 is the embodiment of the invention 1 described a kind of FLASH memory chip johning knot composition that a plurality of independent operation storage spaces are arranged;
But Fig. 3 is the embodiment of the invention 2 described a kind of FLASH memory chip johning knot compositions that a plurality of independent operation storage spaces are arranged;
But Fig. 4 is the embodiment of the invention 3 described a kind of FLASH memory chip johning knot compositions that a plurality of independent operation storage spaces are arranged;
Fig. 5 is the existing chip structural drawing that the described online upgrade system of prior art adopts;
But Fig. 6 described employing that is the embodiment of the invention has the FLASH memory chip organization figure of a plurality of independent operation storage spaces.
Embodiment
But the objective of the invention is to introduce a kind of FLASH memory chip that a plurality of independent operation storage spaces are arranged, realize that to solve start-up routine or the cost that the application program online updating was brought increase, problems such as the PCB space hold is more, the wasting of resources, difficult design.
The invention provides following scheme: in conjunction with the accompanying drawings shown in 1, the storage space 102 of FLASH memory chip can carry out partition management, each regional control line is independently, can carry out independent operation for processor 101 like this, can not have any interference each other.Be equivalent to mark off several zones under a chip capacity (capacity is designated as M), the capacity in each zone (representing with Bank) (being designated as M1, M2...Mn respectively) sum equals the capacity of entire chip, i.e. M1+M2+...+Mn=M.M1, M2...Mn can equate, also can not wait.All there are its address wire and data line (being referred to as AD), control line (Ce, Oe, Wr, Byte, Reset etc. are referred to as Control Signals and are abbreviated as CS) in each FLASH space.
Following several form is arranged: (except other signal wires such as AD, CS omit, do not embody in the drawings), in conjunction with the accompanying drawings shown in 2, but embodiment 1 is a kind of FLASH memory chip syndeton that a plurality of independent operation storage spaces are arranged, wherein the data address bus in each zone (BANK) in the FLASH memory chip 201 is shared, but control line is independently.
In conjunction with the accompanying drawings shown in 3, but embodiment 2 is a kind of FLASH memory chip syndeton that a plurality of independent operation storage spaces are arranged, and wherein the data address bus in each zone (BANK) in the FLASH memory chip 301 is independently, and control line also is independently.
In conjunction with the accompanying drawings shown in 4, but embodiment 3 is a kind of FLASH memory chip syndeton that a plurality of independent operation storage spaces are arranged, wherein the data address bus part in each zone (BANK) in the FLASH memory chip 401 independently, a part is shared, but control line all is independently;
Wherein, the data address bus of regional i and regional j is shared to be ADm, and the data address bus of regional k and regional l is shared to be ADn.
Shown in 5, an online upgrade system is as follows in conjunction with the accompanying drawings: for using two storage spaces, need with two independent F LASH chips 503 and 504; In order to realize independent control, need decipher CS (chip selection signal), We (writing enable signal), Re control signals such as (reading enable signal) simultaneously by EPLD502.Can bring following problem like this:
Though 1, the AD bus is one and CPU501, owing to use two FLASH503,504, on PCB, to walk two times AD signal wire, increased the design complexities of PCB like this;
2, two FLASH503,504, the PCB space that takies is also some more;
3, in order to guarantee not maloperation, need to use EPLD502 that control signal is deciphered, increased demand to the EPLD502 logical resource, may bring the increase of chip cost.
And if use chip of the present invention, then as shown in Figure 6, benefit is as follows:
1, the AD bus does not double, and can not bring complexity for the PCB cabling;
2, do not need EPLD to decipher, CPU601 promptly can independently control different memory areas, and guarantee not can maloperation, has lacked the demand to EPLD, has reduced cost;
3, packing forms that can a chip 602 can satisfy the design in two independent control zone chips (zone 1 and 2), therefore the increase that can not bring the PCB area requirements.
Adopt the described content of the embodiment of the invention, compared with prior art, realization can be stored start-up routine or application program in the middle of circuit design, with the online updating (or being dynamic download) of realizing start-up routine or application program easily and reliably, and can reliably easily between new legacy code realize switching, solved defective of the prior art.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (7)
1. but FLASH memory chip that a plurality of independent operation storage spaces are arranged, be made up of storage space and data line, it is characterized in that, the storage space of described chip is divided into a plurality of zones, and the control line that is connected with each zone is independently to be connected with processor respectively, carries out independent operation.
2. FLASH memory chip as claimed in claim 1 is characterized in that, the data address bus that connects with each zone is shared.
3. FLASH memory chip as claimed in claim 1 is characterized in that, the data address bus that is connected with each zone is respectively independently.
4. FLASH memory chip as claimed in claim 1 is characterized in that, the data address bus that is connected with each zone is that part is independent, and part is shared together.
5. FLASH memory chip as claimed in claim 1 is characterized in that, described control line comprises: Ce signal wire, Oe signal wire, Wr signal wire, Byte signal wire, Reset signal wire.
6. as claim 2,3 or 4 described FLASH memory chips, it is characterized in that described data address bus comprises data line and address wire.
7. FLASH memory chip as claimed in claim 1 is characterized in that the storage space of described chip is divided into a plurality of zones, and the size in each zone can five equilibrium or five equilibrium not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101084678A CN101149972B (en) | 2007-06-14 | 2007-06-14 | FLASH memory chip with a plurality of separate operation memory space |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101084678A CN101149972B (en) | 2007-06-14 | 2007-06-14 | FLASH memory chip with a plurality of separate operation memory space |
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| Publication Number | Publication Date |
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| CN101149972A CN101149972A (en) | 2008-03-26 |
| CN101149972B true CN101149972B (en) | 2011-04-06 |
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| CN2007101084678A Expired - Fee Related CN101149972B (en) | 2007-06-14 | 2007-06-14 | FLASH memory chip with a plurality of separate operation memory space |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101916589A (en) * | 2010-07-12 | 2010-12-15 | 成都市华为赛门铁克科技有限公司 | Nonvolatile storage equipment and control method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316087A (en) * | 1999-04-27 | 2001-10-03 | 松下电器产业株式会社 | Semiconductor memory card and data reading apparatus |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316087A (en) * | 1999-04-27 | 2001-10-03 | 松下电器产业株式会社 | Semiconductor memory card and data reading apparatus |
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