CN101149721A - Hardware integrated circuit board backboard interface - Google Patents
Hardware integrated circuit board backboard interface Download PDFInfo
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- CN101149721A CN101149721A CNA2007101240708A CN200710124070A CN101149721A CN 101149721 A CN101149721 A CN 101149721A CN A2007101240708 A CNA2007101240708 A CN A2007101240708A CN 200710124070 A CN200710124070 A CN 200710124070A CN 101149721 A CN101149721 A CN 101149721A
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Abstract
The invention discloses a backplane interface of hardware board that lies on the hardware board. Business data processing unit of the hardware board transmits business data with backplane through the backplane interface. it is characterized in that the backplane interface includes a group of sending trigger used to transmit business data that hardware board pre-sends to the backplane; a group of receiving trigger used to collect and receive data from the backplane, business data processing unit sent to the hardware board. The invention segments the delay from the sender to the receiver through increasing two groups of triggers, in these circumstances, the delay doesn't accumulate, only need to be concerned about the reliability of delay of the receiving and sending trigger and backplane.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of backplane interface design proposal that can eliminate hardware integrated circuit board groove position correlativity.
Background technology
In the communications field, switch, router and various transmission equipment adopt the cabinet system architecture that a plurality of interface draw-in grooves position is arranged usually, each groove position hardware integrated circuit board connects by backboard jack interface and backboard, so just can pass through the core bus transfer data information between each hardware integrated circuit board, its theory structure as shown in Figure 1.In the process of data transmission, the hardware integrated circuit board of each groove position is shared same clock source, the in-phase clock that sends in system clock unit (through backboard be dispensed to each groove position system clock CLK1, CLK2 ... under effect CLKN), finish the transmission and the reception of data.
When equipment adopts system architecture shown in Figure 1, if the hardware integrated circuit board is not done any special design on hardware, usually all can reveal very big dependence (being hardware integrated circuit board groove position correlativity) to the groove bit table, that is to say, hardware integrated circuit board is inserted on some groove positions can operate as normal, and being inserted in then may not operate as normal on other groove positions.Below just its reason is specifically described.Owing to exist on chip (for example: programmable logic device (PLD) FPGA or business processing chip) transmission delay, the transmission board receive time delay of data transmission delay, chip on data transmission delay, backboard propagation delay time, the dash receiver in the data transfer procedure, cause the receiving end data than the transmitting terminal data time delay to be arranged, this time delay is the result of above-mentioned various time delay accumulations.Because the otherness in hardware integrated circuit board and backboard PCB dielectric material characteristic and the wiring, the consistance of propagation delay time are difficult to guarantee that each chip transmit after receive time delay also cannot be controlled.The time delay uncertain factor is many, and its consequence is exactly that the time delay total ripple is big, if the receiving end data sampling designs improperly constantly, the inconsistent problem of data that data and transmitting terminal send will occur receiving, and data transmission credibility also therefore and variation.Below the device that just transmits and receive data with each hardware integrated circuit board all be that programmable logic device (PLD) (such as being programmable logic device (PLD) FPGA1, FPGA2 and FPGA3) is that example describes, as shown in Figure 2, it is groove position 1 integrated circuit board transmits data to groove position 2 or groove position 3 integrated circuit boards a principle schematic.8 circuit-switched data signal FDOUT0, the FDOUT1......FDOUT7 of groove position 1 integrated circuit board FPGA1 output, send to backboard by eight data lines respectively, transfer to groove position 2 (or groove position 3) integrated circuit board through core bus then, finish the reception of eight circuit-switched data FDINA0, FDINA1......FDINA7 (or FDINB0, FDINB1......FDINB7) by FPGA2 (or FPGA3).Tranmitting data register CLK1 and receive clock CLK2, CLK3 are all from system clock unit, and the transmitting-receiving of data utilizes the same edge (is example with the rising edge) of these homology clocks to trigger.Though FPGA1 sends data to each bar data line simultaneously in theory, but always can there be the trickle mistiming when sending, and FPGA2 can receive data on each bar data line simultaneously in theory, but always can there be the trickle mistiming when receiving, add PCB cabling time delay and also have nuance, the eight circuit-switched data signals that just cause FPGA1 to send simultaneously in theory but can't receive when FPGA2 receives simultaneously, referring to Fig. 3 (a), the 8 circuit-switched data signal timing diagrams that its expression FPGA2 receives.For FPGA2, the data-signal that has enters effective retention time in advance, and the hysteresis that has enters, like this data on the data bus from the earliest effectively to effectively continuing for some time U the latest, data bus instability during this period of time.Deduction bus amphibolia,, other in clock period are S stationary phase constantly.If the rising edge with system clock triggers FPGA2 reception data, then have only the rising edge of clock to drop in the time period S, could guarantee to receive correct data.
On the other hand, because the otherness of wiring, the backboard data bus time delay difference of different slots position correspondence, even same hardware integrated circuit board, be inserted in when working on the different groove positions, the data bus generation stationary phase moment and duration length also can be different, and referring to Fig. 3 (b), it is the eight circuit-switched data signal timing diagrams that FPGA3 receives.Using the homology clock to carry out under the synchronous situation, guarantee that the hardware integrated circuit board can both operate as normal in each groove position, must be with clock sampling along being controlled in each groove position bus common factor of stationary phase, in promptly public stationary phase.Yet may not exist this public stationary phase, even exist, because of its time short, the requirement of clock is become harsh, and is difficult to specific implementation on engineering.
In order to address the above problem, industry has a kind of method, be exactly on every hardware integrated circuit board, to increase a clock phase walking circuit, when the hardware integrated circuit board can't be worked on certain groove position, by mobile clock phase, make FPGA2 be used for the clock delay of image data, drop on data bus in stationary phase to guarantee its rising edge.This method need be inserted in the hardware integrated circuit board on each groove position usually, the scope of transportable clock phase when finding out operate as normal, if the scope that each groove position can be regulated is very big, and there is public scope, then as long as clock phase is adjusted in this common range, the hardware integrated circuit board just can be in any groove position operate as normal.Adopt this method, not only increased the workload of later stage debugging greatly, and when practical application, propagation delay time changes owing to the difference of circuit board processing batch and the modification in the design, test time delay and can't guarantee in the method that receiving end is adjusted under various conditions can both the reliable reception data.So above-mentioned solution does not reach ideal effect.
Summary of the invention
In order to eliminate the problem of above-mentioned hardware integrated circuit board groove position correlativity, the present invention proposes a kind of backplane interface of eliminating hardware integrated circuit board groove position correlativity.
The backplane interface of a kind of hardware integrated circuit board provided by the invention, it is positioned on the hardware integrated circuit board, the business data processing unit of hardware integrated circuit board carries out business data transmission by described backplane interface and backboard, described backplane interface comprises: one group sends trigger, is used for the pre-business datum that sends of hardware integrated circuit board is delivered to backboard; And a group of received trigger, be used to gather the data that receive backboard, be sent to the business data processing unit of hardware integrated circuit board.
Wherein, described transmission trigger links to each other with the clock signal terminal of backboard with the clock signal trigger end that receives trigger.Wherein, described transmission trigger and reception trigger are triggered by the rising edge or the negative edge of system synchronization clock respectively.Wherein, described transmission trigger and reception trigger mainly are made of synchronizer trigger.Wherein, described transmission trigger and reception trigger are made of d type flip flop respectively.Wherein, described synchronizer trigger is d type flip flop, Q trigger, the unitized construction of one or more in JK flip-flop, the synchronous rs flip-flop synchronously.Wherein, described transmission trigger links to each other with the interface that transmits and receive data of backboard by data line respectively with input end with the data output that receives trigger, and the isometric wiring of backboard data cabling.
Compared with prior art, the designed backplane interface of the present invention has the following advantages:
In the backplane interface side of hardware integrated circuit board, the synchronizer trigger that adopts system clock to control will send data and get, and so just remove the time delay accumulation to sending the influence of data, guarantee that the hardware integrated circuit board sends to the time delay consistance of the data of backboard; Adopt the synchronizer trigger of system clock control to sample, so just removed the time delay accumulation, guaranteed that backboard sends the time delay consistance of the data of hardware integrated circuit board to receiving the influence of data to receiving data; Add the isometric design of backboard data cabling and the Synchronization Design of entire system, just guaranteed the consistance of each number of slots, make receiving end can stablize, receive reliably data according to the transmitting-receiving phase place.
Description of drawings
Fig. 1 is in the prior art, and the cabinet system principle structural representation of a plurality of interface draw-in grooves position is arranged;
Fig. 2 is in the prior art, carries out the theory structure synoptic diagram of data transfer between the integrated circuit board of different slots position;
Fig. 3 (a) is the eight circuit-switched data signal timing diagrams that the FPGA2 of Fig. 2 receives;
Fig. 3 (b) is the eight circuit-switched data signal timing diagrams that the FPGA3 of Fig. 2 receives;
Fig. 4 is the structural representation of backplane interface provided by the present invention;
Fig. 5 is the example structure synoptic diagram of backplane interface provided by the present invention;
Fig. 6 (a) is the logic timing figure of d type flip flop 412 inputs, output data in the interface circuit shown in Figure 5.
Fig. 6 (b) is the logic timing figure of d type flip flop 413 inputs, output data in the interface circuit shown in Figure 5.
Embodiment
Below will describe each preferred embodiment of the present invention in detail.
Mentality of designing of the present invention is that the backboard side increases by two groups of transmissions and receives trigger on the hardware integrated circuit board, these two groups of triggers cut transmitting terminal to the time delay of receiving end, time delay can not accumulated like this, when carrying out the system sequence design, only need pay close attention to the reliability of transmitting-receiving trigger and backboard time delay, and the time delay of self device cooperates on the hardware integrated circuit board, then by hardware plate inner control.From adopting this design, transmitting terminal is reduced to the data delay fluctuation range of receiving end, the system synchronization design becomes and realizes easily, so just for solve integrated circuit board groove position correlativity provide a kind of simple in structure, be easy to realize, with low cost and can guarantee effective backplane interface of data transmission quality, below specify referring to Fig. 4.
As shown in Figure 4, the backplane interface of hardware integrated circuit board provided by the invention, it is positioned on the hardware integrated circuit board, the business data processing unit 313 of hardware integrated circuit board carries out business data transmission by described backplane interface and backboard 314, described backplane interface comprises: one group sends trigger 311, is used for the pre-business datum that sends of hardware integrated circuit board is delivered to backboard 314; And a group of received trigger 312, be used to gather the data that receive backboard 314, be sent to the business data processing unit 313 of hardware integrated circuit board.Wherein, send trigger 311 and link to each other with the clock signal terminal of backboard 314, just, send trigger 311 and receive trigger 312 and trigger by the rising edge or the negative edge of system synchronization clock respectively with the clock signal trigger end that receives trigger 312.Above-mentioned transmission trigger 311 links to each other with the interface that transmits and receive data of backboard 314 by data line respectively with input end with the data output that receives trigger 312, and the isometric wiring of backboard data cabling.
Below referring to Fig. 5 of the invention process one optimum embodiment is described.As can be seen from Figure 5, structure shown in Figure 5 is with respect to prior art constructions shown in Figure 2, the eight bit synchronization d type flip flops that are used for as above-mentioned transmission trigger 311 and reception trigger 312 have been increased, wherein, the business data processing unit 313 of hardware integrated circuit board is mainly realized by the FPGA process chip.
As shown in Figure 5, it has respectively used eight d type flip flops 411,412 and 413 at the transmitting terminal of hardware integrated circuit board and the backboard side of receiving end, and trigger 411,412 and 413 is imported at the rising edge control down-sampling of system synchronization clock CLK1, CLK2 and CLK3 respectively, the output bus data.Represent to output to the data code flow of backboard among the figure from d type flip flop 411 with DOUT, represent the bitstream of the reception of d type flip flop 412 with DINA from backboard, the data code flow that is input to hardware integrated circuit board FPGA 415 of representing d type flip flop 412 with FDINA, represent the bitstream of the reception of d type flip flop 413 with DINB, represent the data code flow that is input to hardware integrated circuit board FPGA416 of d type flip flop 413 with FDINB from backboard.As can be seen from the figure, d type flip flop 411 is to use as sending trigger 311, and d type flip flop 412 and d type flip flop 413 are to use as receiving trigger 312.
Cut into three parts from the data delay of FPGA 414 to FPGA 415 or FPGA 416 by d type flip flop 411,412 and 413: bitstream enters the time delay τ before the d type flip flop 411
1, d type flip flop 411 output terminals are to the time delay τ of trigger 412 and 413 input ends
2, d type flip flop 412 and 413 time delay τ to back level chip FPGA
3, τ wherein
2Form by three parts accumulations again: the time delay of d type flip flop 411 to the time delay of backboard, backboard cabling time delay, backboard to trigger 412 and 413., normally communication stable in order to realize between integrated circuit board, system only need guarantee that the d type flip flop 412 and 413 that is used to receive can collect data reliably, just controls the time delay τ of each groove interdigit well
2That's all, and time delay τ on the integrated circuit board
1And τ
3Influence, then by controlling in the plate.
As can be seen from Figure 6, d type flip flop 412 and 413 input signal sequential charts among Fig. 5.Because time delay τ
2Fluctuation range little, the data bus amphibolia, be significantly shorter than situation shown in Figure 3, promptly among the figure data of expression on the data bus from the earliest effectively to the latest effectively duration section U obviously shorten, and two numbers of slots do not have notable difference according to the bus generation stationary phase moment and duration length, therefore when guaranteeing each groove position reliable reception data, eliminated the otherness of groove position, solved the dependency problem of integrated circuit board the groove position.In a word, the present invention for solve integrated circuit board groove position correlativity provide a kind of simple in structure, be easy to realize, with low cost and can guarantee the effective ways of data transmission quality.
Above-mentioned is that the example explanation is comparatively concrete with the d type flip flop, but the type that transmission trigger 311 of the present invention and reception trigger 312 are adopted is not limited thereto, send trigger 311 and receive trigger 312 and can mainly constitute by various synchronizer triggers, comprising d type flip flop, Q trigger, synchronous JK flip-flop, synchronous rs flip-flop, can certainly adopt their unitized construction, as long as can realize above-mentioned d type flip flop identical functions.When selecting synchronizer trigger, its data bits is by the figure place decision of hardware integrated circuit board data bus.
Illustrating of foregoing is comparatively concrete, can not therefore think the restriction to scope of patent protection of the present invention, and scope of patent protection of the present invention should be as the criterion with claims.
Claims (7)
1. the backplane interface of a hardware integrated circuit board, it is positioned on the hardware integrated circuit board, and the business data processing unit of hardware integrated circuit board carries out business data transmission by described backplane interface and backboard, it is characterized in that, and described backplane interface comprises:
One group sends trigger, is used for the pre-business datum that sends of hardware integrated circuit board is delivered to backboard;
And a group of received trigger, be used to gather the data that receive backboard, be sent to the business data processing unit of hardware integrated circuit board.
2. backplane interface according to claim 1 is characterized in that, described transmission trigger links to each other with the clock signal terminal of backboard with the clock signal trigger end that receives trigger.
3. backplane interface according to claim 1 is characterized in that, described transmission trigger and reception trigger are triggered by the rising edge or the negative edge of system synchronization clock respectively.
4. backplane interface according to claim 1 is characterized in that, described transmission trigger and reception trigger mainly are made of synchronizer trigger.
5. backplane interface according to claim 4 is characterized in that, described transmission trigger and reception trigger are made of d type flip flop respectively.
6. backplane interface according to claim 4 is characterized in that, described synchronizer trigger is d type flip flop, Q trigger, the unitized construction of one or more in JK flip-flop, the synchronous rs flip-flop synchronously.
7. backplane interface according to claim 1 is characterized in that, described transmission trigger links to each other with the interface that transmits and receive data of backboard by data line respectively with input end with the data output that receives trigger, and the isometric wiring of backboard data cabling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101240708A CN100570590C (en) | 2007-10-16 | 2007-10-16 | A kind of backplane interface of hardware integrated circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101240708A CN100570590C (en) | 2007-10-16 | 2007-10-16 | A kind of backplane interface of hardware integrated circuit board |
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| Publication Number | Publication Date |
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| CN101149721A true CN101149721A (en) | 2008-03-26 |
| CN100570590C CN100570590C (en) | 2009-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007101240708A Active CN100570590C (en) | 2007-10-16 | 2007-10-16 | A kind of backplane interface of hardware integrated circuit board |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986279A (en) * | 2010-11-17 | 2011-03-16 | 许继集团有限公司 | Board card test system |
| CN106452646A (en) * | 2016-11-03 | 2017-02-22 | 电信科学技术第五研究所 | System and method for enlarging number of reference or monitoring signals of time-frequency synchronization equipment |
| CN109857042A (en) * | 2019-03-29 | 2019-06-07 | 中国工程物理研究院化工材料研究所 | A kind of hot Combined Loading device data synchronous control system of power |
-
2007
- 2007-10-16 CN CNB2007101240708A patent/CN100570590C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986279A (en) * | 2010-11-17 | 2011-03-16 | 许继集团有限公司 | Board card test system |
| CN101986279B (en) * | 2010-11-17 | 2013-01-16 | 许继集团有限公司 | Board card test system |
| CN106452646A (en) * | 2016-11-03 | 2017-02-22 | 电信科学技术第五研究所 | System and method for enlarging number of reference or monitoring signals of time-frequency synchronization equipment |
| CN106452646B (en) * | 2016-11-03 | 2019-04-30 | 电信科学技术第五研究所有限公司 | A kind of system and method expanding the reference of temporal frequency synchronizer or monitoring signals quantity |
| CN109857042A (en) * | 2019-03-29 | 2019-06-07 | 中国工程物理研究院化工材料研究所 | A kind of hot Combined Loading device data synchronous control system of power |
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| Publication number | Publication date |
|---|---|
| CN100570590C (en) | 2009-12-16 |
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