CN101145783A - An improved voltage marking D/A converter - Google Patents

Abstract

The invention relates to a circuit, in particular to an improved voltage calibration digital-to-analog converter, which is mainly used in universal serial bus (USB) earphones, microphones, telephones and other audio systems. According to the technical proposal provided in the invention, in a series-parallel combined resistor network, the voltage is divided into a coarse tuning resistor network and a fine tuning resistor network, the output terminal of the coarse tuning resistor network is connected with the positive pole terminal of an operation amplifier, the output terminal of the fine tuning resistor network is connected with the negative pole terminal of the operation amplifier, a quantitative switch is respectively provided on each resistor in the coarse tuning resistor network and fine tuning resistor network, and a correction resistor is connected in the fine tuning resistor network in parallel; and during operation, a binary data to be converted is firstly inputted and separated into high-order data and low-order data, and the middle and low-order data is decoded and used for controlling the quantitative switch in the fine tuning resistor network. The invention reduces the number of resistors, so as to reduce the product cost and improve the conversion accuracy of the product.

Description

A kind of improved voltage marking D/A converter

Technical field

The present invention relates to a kind of circuit, refer in particular to a kind of improved voltage marking D/A converter, be mainly used in audio systems such as USB (USB) earphone, Mike and phone.

Background technology

Traditional simple and easy voltage marking digital-to-analogue conversion (DAC) is by utilizing 2 ⁿThe resistance string that individual resistance is formed is with V _RefBe divided into equal 2 ⁿSection as shown in Figure 2, thereby realizes intrinsic monotonicity.Every group of binary switch tree is selected corresponding to given input data bit.Its another advantage is if the magnitude of voltage V that the top node of resistance string is connected with bottom node _hAnd V _lBe an arbitrary value, then DAC will be at V _hAnd V _lBetween with having 2 ⁿThe resolution of individual quantification step is carried out interpolation.But maximum resistance number (2 ⁿ) and switch number (2 ^N+1-2) the potential measurement DAC of reality is limited in the scope of n≤8, the area that mainly is subject to resistance is too big, and the relative accuracy of resistance effective performance wayward and electronic switch does not reach designing requirement.Thereby influenced the conversion accuracy of DAC.

Summary of the invention

The objective of the invention is to seek a kind of improved voltage marking D/A converter,, reduce the cost of product, improve the conversion accuracy of product by reducing the quantity of resistance.

According to technical scheme provided by the invention, in a string and combined resistance network, voltage is divided into roughly adjusted rheostat network and two parts of fine tuning resistor network, and be connected with the operational amplifier positive terminal at the output of roughly adjusted rheostat network, the output of fine tuning resistor network is connected with the negative phase end of operational amplifier, have the quantification diverter switch respectively on each resistance on roughly adjusted rheostat network and the fine tuning resistor network, correction resistance is connected in parallel on the fine tuning resistor network; During work, import binary data to be converted earlier, and these data are divided into a high position and low level, wherein low level goes to control the quantification diverter switch of fine tuning resistor network after decoding; Go to control the quantification diverter switch of roughly adjusted rheostat network after the high-order decoding, after quantizing, take out the positive terminal that a voltage is given operational amplifier from the roughly adjusted rheostat network, the fine tuning resistor network takes out the negative phase end that a voltage is given operational amplifier, through computing, draw the voltage after the conversion.

Utilize operational amplifier to carry out computing when computing, operational formula is: U _O=2U _M-U _N, U wherein _MCoarse tuning voltage after referring to quantize, U _NFine tuning voltage after referring to quantize, U _oOutput voltage after referring to change.The output of fine tuning resistor network is connected with the negative phase end of operational amplifier after through a follower; The fine tuning resistor network takes out a voltage is given operational amplifier behind follower negative phase end.Wherein decoding again after the negate of low level elder generation.

After applying the present invention to USB voice control chip, can better improve Audio Processing speed.Therefore compare with traditional voltage marking DAC, needed resistance number is few, analog switch is few, has advantages such as precision height, speed are fast, monotonicity.The DAC of traditional voltage marking 16bit needs 2 ¹⁶(about 6.6 ten thousand) individual resistance.Because multicore sheet area is big more for the high more needed resistance of precision, be not easy to relative accuracy control, electronic switch quantity is many, and the cost price of product is too high.So on performance and cost, be difficult to accomplish the high accuracy DAC of 1 6bit.And this project adopted is modified model voltage marking DAC, and the resistance number and the analog switch that are adopted significantly reduce.

Description of drawings

Fig. 1 is the system diagram that applies the present invention to the USB audio control chip.

Fig. 2 is traditional voltage marking digital-to-analogue conversion figure.

Fig. 3 is voltage marking digital-to-analogue conversion figure of the present invention.

Fig. 4 is 16 DAC resistor network schematic diagrames.

Fig. 5 is the computing circuit that takes out voltage.

Embodiment

Mentality of designing of the present invention is: utilize in the CMOS technology, the advantage that the relative accuracy of device can accurately be controlled, a string and combined resistance network have been designed, voltage is divided into roughly adjusted rheostat networking and two parts of fine tuning resistor network, cooperates 1 operational amplifier to realize high-precision 16 figure place weighted-voltage D/A converters at last.Employed resistance number only is 2 ⁹+ 2 ⁷Individual, add 37 in addition and revise resistor network (as shown in Figure 4).Adopt 0.35um CMOS 3.3V/5V technology, polysilicon is done resistance, and the electric resistance array layout structure has effectively dwindled area through ingenious design, and relative accuracy is controlled easily like this, is convenient to integrated.

Under the load of 10k ohm, THD+N (3dB) is-74.29dB, the processing signals bandwidth is 20kHz, SNR is 93.6 dB, and silent SNR can reach 98.2 dB.1LSB can reach 34uV, and it is 1.25Vrms that Dynamic Range can reach 93.8 dB.Output Vltage (rms), Output Vltage Swing is that 0.5v is to 4v, conversion speed is fast, and the precision height has advantages such as monotonicity.And the foundation of signal and sampling cooperate response fast and high sensitivity operational amplifier to be able to quick conversion.What the reference voltage of amplifier adopted is the high accuracy band-gap reference with temperature-compensating.Vref is that 2.25V. guarantees that reference voltage is not subjected to power supply and Temperature Influence, thereby guarantees the precision of DAC.The changing voltage formula

$U_O=\mathrm{Uc}+4*\frac{V_{\mathrm{ref}}-\mathrm{Uc}}{2^9+1+2}+\frac{V_{\mathrm{ref}}-\mathrm{Uc}}{2^9+1+2}*\frac{1}{2^7}(D_{15}{D}_{14}......{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0+1)$

$\mathrm{Uc}=\frac{V_{\mathrm{ref}}}{2^{9}R+2R+R+R_b}*R_b$

D in the formula ₁₅D ₁₄... D ₀Be the 16 bit data input of DA, Uc is the DA bias voltage, R _bIt is according to the value of Uc and fixed biasing resistor.

The effect of Uc: owing to will in resistor network, extract different voltage out, and minimum voltage is very little again, the transmission of voltage is to adopt the NMOS of switching mode to finish, because transmission voltage has the threshold value loss, therefore be necessary for adopt voltage provide a dc offset voltage to come the bucking voltage loss, guarantee the precision of sampled voltage.And for the amplifier of back provides biasing.Its voltage swing with output is relevant simultaneously, so the design tradeoff value is the Vt+Vo value of NMOS.

Operation principle is as follows

Can obtain from Fig. 4: $R_{\mathrm{bc}}=[2R+(2R//\frac{1}{31}R)]//128R=2R......1$

So the electric current of entire circuit is: I _d=V _Ref/ [(2 ⁹+ 1+2) R+R _b] ... 2

U _c＝I _d*R _b

Obtain U by 1 and 2 _Bc=I _d* R _Bc=I _d* 2R=2*U _m... 3

R _bc。Refer to the resistance that the b point is ordered to c among Fig. 4,

U _mRefer to the pressure drop of a resistance on the roughly adjusted rheostat network, 2 ⁹An ohmically dividing potential drop size is I in the resistor network _d* R ... 4

U _nBe 2 ⁷Ohmically dividing potential drop size in the resistor network gets by 1 and 3:

U _n＝U _bc/2 ⁷＝2U _m/2 ⁷＝2U _m/2 ⁶ ......5

That is: U _m=2 ⁶U _n

Fig. 5 is the computing circuit that takes out voltage.

The output voltage of DAC is by 2 ⁹Resistor network and 2 ⁷Resistor network is respectively got a voltage and is obtained through computing:

U _M＝U _m*(D ₁₅～D ₇+1)+U _bc+U _C

$U_N=U_n*(\stackrel{\_}{D_6}~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0})+U_C$

We can obtain U by computing circuit _O=2U _M-U _N

$U_O=2[U_m({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~{\mathrm{<figure-callout\; id="7"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_7+1)+U_{\mathrm{bc}}+U_C]-U_n(\stackrel{\_}{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_6}~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0})+U_C$

Solve $U_O=2*U_m({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~{\mathrm{<figure-callout\; id="7"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_7+1)+2*U_{\mathrm{bc}}-U_n\left(\stackrel{\_}{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_6~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}}\right)+U_C$

$=2*2^6*U_n(D_{15}~D_7+1)+2*2*U_m-U_n(\stackrel{\_}{D_6}~\stackrel{\_}{D_0})+U_C$

$=U_n[2^7*({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~D_7+1)-(\stackrel{\_}{D_6}~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0})]+U_C+4U_m$

$=\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}]*2^6}*[2^7*({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~{\mathrm{<figure-callout\; id="7"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_7+1)-(\stackrel{\_}{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_6}~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0})]+U_C+4*2^6*\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}*2^6}$

If $\mathrm{LSB}=U_n=\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}]*2^6}=\frac{V_{\mathrm{ref}}-U_C}{2^9+1+2}*\frac{1}{2^6}$

$U_T=U_C+4*\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}]}=U_C+4*\frac{V_{\mathrm{ref}}-U_C}{2^9+1+2}$ It is constant coefficient.

That is: $U_O=\mathrm{LSB}*[2^7(D_{15}~D_7+1)-\left(\stackrel{\_}{D_6~\stackrel{\_}{D_0}}\right)]+U_T$

Because $\left(\stackrel{\_}{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_6~\stackrel{\_}{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}}\right)=(2^7-1)-({\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_6~D_0)$

So U _O=LSB*[2 ⁷(D ₁₅～D ₇+ 1)-(2 ⁷-1)-(D ₆～D ₀)]+U _T

＝LSB*[2 ⁷(D ₁₅～D ₇)+(D ₆～D ₀)+1]+U _T

Because 2 ⁷(D ₁₅～D ₇) be equivalent to (D ₁₅～D ₇) be moved to the left 7, with (D ₆～D ₀) addition just obtains:

U _O＝LSB*(D ₁₅～D ₀+1)+U _T

The changing voltage formula: ${\mathrm{<figure-callout\; id="0"\; label="U"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">U</figure-callout>}}_0=U_C+4*\frac{V_{\mathrm{ref}}-U_C}{2^9+1+2}+\frac{V_{\mathrm{ref}}-U_C}{2^9+1+2}*\frac{1}{2^6}({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0+1)$ Or

${\mathrm{<figure-callout\; id="0"\; label="U"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">U</figure-callout>}}_0=U_C+4*\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}]}+\frac{V_{\mathrm{ref}}}{[(2^9+1+2)+\frac{R_b}{R}]}*\frac{1}{2^6}({\mathrm{<figure-callout\; id="15"\; label="D"\; filenames="A20071013450200081.png,A20071013450200091.png"\; state="\{\{state\}\}">D</figure-callout>}}_{15}~{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="A20071013450200071.png,A20071013450200081.png"\; state="\{\{state\}\}">D</figure-callout>}}_0+1)$

So the scope of output voltage is [U _T+ LSB～U _T+ 2 ¹⁶* LSB].

Calculate by deriving, we can obtain full scale (FS)=U of DAC _T+ 2 ¹⁶* LSB, and realized 16 precision.Full scale, be divided into 2 ¹⁶Part, and by changing input data, 2 ¹⁶Individual scale can both reach.

Wherein, I _dRefer to total current, V _RefThe reference voltage that finger provides, U _cRefer to the voltage that c is ordered, U _BcRefer to that the b point is to the voltage between the c point, R _bRefer to c point resistance to earth, U _MCoarse tuning voltage after referring to quantize, U _NFine tuning voltage after referring to quantize, U _ORefer to the output voltage after the conversion, D refers to the binary data of the preparation conversion imported, and LSB refers to minimum quantization unit, U _TRefer to constant,

Refer to the D negate.

Claims (4)

1. improved voltage marking D/A converter, it is characterized in that: in a string and combined resistance network, voltage is divided into roughly adjusted rheostat network and two parts of fine tuning resistor network, and be connected with the operational amplifier positive terminal at the output of roughly adjusted rheostat network, the output of fine tuning resistor network is connected with the negative phase end of operational amplifier, have the quantification diverter switch respectively on each resistance on roughly adjusted rheostat network and the fine tuning resistor network, correction resistance is connected in parallel on the fine tuning resistor network; During work, import binary data to be converted earlier, and these data are divided into a high position and low level, wherein low level goes to control the quantification diverter switch of fine tuning resistor network after decoding; Go to control the quantification diverter switch of roughly adjusted rheostat network after the high-order decoding, after quantizing, take out the positive terminal that a voltage is given operational amplifier from the roughly adjusted rheostat network, the fine tuning resistor network takes out the negative phase end that a voltage is given operational amplifier, through computing, draw the voltage after the conversion.

2. improved according to claim 1 voltage marking D/A converter is characterized in that: utilize operational amplifier to carry out computing when computing, operational formula is: U _O=2U _M-U _N, U wherein _MCoarse tuning voltage after referring to quantize, U _NFine tuning voltage after referring to quantize, the output voltage after UO refers to change.

3. improved according to claim 1 voltage marking D/A converter is characterized in that: the output of fine tuning resistor network is connected with the negative phase end of operational amplifier after through a follower; The fine tuning resistor network takes out a voltage is given operational amplifier behind follower negative phase end.

4. improved according to claim 1 voltage marking D/A converter is characterized in that: wherein decoding again after the negate of low level elder generation.

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