CN101136370B - Semiconductor component and its manufacturing method - Google Patents
Semiconductor component and its manufacturing method Download PDFInfo
- Publication number
- CN101136370B CN101136370B CN2006101280081A CN200610128008A CN101136370B CN 101136370 B CN101136370 B CN 101136370B CN 2006101280081 A CN2006101280081 A CN 2006101280081A CN 200610128008 A CN200610128008 A CN 200610128008A CN 101136370 B CN101136370 B CN 101136370B
- Authority
- CN
- China
- Prior art keywords
- resilient coating
- those
- pmos
- semiconductor element
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
This invention relates to a manufacturing method for semiconductor elements, which first of all provides a base, then forms multiple IO elements and core elements on it, in which, the IO elements include IO PMOS and IO NMOS, the core elements include core PMOS and NMOS, then it forms a buffer layer on the base, removes the buffer layer out of the IO PMOS surface to reduce instability of the negative bias temperature of the IO PMOS and then covers a tensile contact window etched pause layer on the IO NMOS and the core NMOS and covers a compressive contact window etched pause layer on the core PMOS.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relate to a kind of the improvement as input and output (input/output, I/O) semiconductor element and the manufacture method thereof of the back bias voltage temperature instability of the PMOS of element (being called the I/O element again) (negative bias temperature instability is abbreviated as NBTI).
Background technology
Semiconductor element is according to functional I/O element and the core parts (coredevice) of mainly can being divided into.And according to the electrical kind of element, the I/O element can comprise I/O PMOS and I/O NMOS, just as the PMOS of I/O element with as the NMOS of I/O element; Similarly, core parts also comprise as the PMOS of core parts with as the NMOS of core parts.
Have employing strained silicon (strain silicon) to improve the method for core parts usefulness (performance) at present, but this measure there is no help for the reliability (reliability) of I/O PMOS.And because the I/O element must bear higher voltage usually, particularly therefore the part at I/O PMOS can can't effectively reduce or eliminate its back bias voltage temperature instability (NBTI), and can't further improve the usefulness and the reliability thereof of element.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of semiconductor element is being provided, and can increase usefulness and the reliability thereof of I/O PMOS by simple process steps, and can stop that hydrogen is diffused into Si and SiO
2The interface, also can not impact the resistance (Rs) of the metal silicide layer under it.
A further object of the present invention provides a kind of semiconductor element, with the back bias voltage temperature instability (NBTI) of elimination I/O PMOS, and then the usefulness and the reliability thereof of increase element.
The present invention proposes a kind of manufacture method of semiconductor element, and comprising provides a substrate earlier, forms a plurality of I/O elements and a plurality of core parts again in substrate, and wherein the I/O element comprises that I/O PMOS and I/ONMOS, core parts comprise core PMOS and core NMOS.Then, in substrate, form one deck resilient coating, remove I/O PMOS surface resilient coating in addition again, to reduce its back bias voltage temperature instability (NBTI).Then, go up the anti-contact hole etching suspension layer (tensile CESL) of opening of covering one deck in I/O NMOS and core NMOS, and upward cover one deck resistance to compression contact hole etching suspension layer (compressive CESL) in core PMOS.
According to the described manufacture method of one embodiment of the invention, the step of above-mentioned formation resilient coating is prior to forming one deck shielding layer on I/O NMOS beyond the I/O PMOS and the core parts, again surface treatment being carried out in substrate, to form aforementioned resilient coating in substrate surface.And the step that removes the resilient coating beyond the I/O PMOS surface comprises by removing shielding layer and removes above-mentioned resilient coating simultaneously.In addition, above-mentioned surface treatment comprises oxygen plasma treatment, and aforementioned oxygen plasma treatment can comprise physical gas-phase deposition (PECVD) or use photoresist to peel off with instrument (STRIP tool) and handle.
According to the described manufacture method of another embodiment of the present invention, the method that forms above-mentioned resilient coating can be a chemical vapor deposition method.
According to the described manufacture method of embodiments of the invention, when going up covering resistance to compression contact hole etching suspension layer, core PMOS can cover the resilient coating on the I/O PMOS simultaneously.
According to the described manufacture method of embodiments of the invention, go up the resilient coating that can cover simultaneously when covering is anti-opens the contact hole etching suspension layer on the I/O PMOS in I/O NMOS and core NMOS.
The present invention reintroduces a kind of semiconductor element, its structure comprises substrate at least, be positioned at suprabasil a plurality of I/O element and a plurality of core parts, one deck resilient coating, anti-contact hole etching suspension layer and one deck resistance to compression contact hole etching suspension layer opened of one deck, and wherein the I/O element comprises that I/O POMS and I/O NMOS, core parts comprise core POMS and core NMOS.And resilient coating is the surface that is positioned at I/O PMOS.And the anti-contact hole etching suspension layer of opening is covered on I/O NMOS and the core NMOS, and resistance to compression contact hole etching suspension layer then is to be covered on the core PMOS.
According to the described semiconductor element of one embodiment of the invention, above-mentioned resistance to compression contact hole etching suspension layer also comprises and being covered on the resilient coating.
According to the described semiconductor element of one embodiment of the invention, the above-mentioned anti-contact hole etching suspension layer of opening also comprises and being covered on the resilient coating.
According to described method of the preferred embodiments of the present invention or structure, above-mentioned resilient coating comprises sull.
According to described method of the preferred embodiments of the present invention or structure, the thickness of above-mentioned resilient coating is between 10 dusts～200 dusts.
The present invention can stop that hydrogen is diffused into Si and SiO because be formed with the very thin resilient coating of one deck on I/O PMOS surface
2The interface, the back bias voltage temperature instability (NBTI) that therefore can eliminate I/O PMOS does not influence the usefulness of element simultaneously.In addition, resilient coating of the present invention can not impact the resistance of metal silicide layer.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A, 1B, 1C-1,1C-2,1D and 1E are the manufacturing process profiles according to a kind of semiconductor element of a preferred embodiment of the present invention, and wherein Fig. 1 C-1 represents respectively with Fig. 1 C-2 and utilizes two kinds of different technologies to form resilient coating of the present invention.
Fig. 2 is I/O PMOS and the NBTI of an existing I/O PMOS assessment curve chart according to a preferred embodiment of the invention.
The simple symbol explanation
10a：I/O?PMOS 10b：I/O?NMOS
11a: core PMOS 11b: core NMOS
100: substrate 102: isolation structure
104: gate dielectric layer 106: grid
107: compensate for clearance wall 108: clearance wall
110: lightly doped drain 112: source electrode and drain electrode
114: metal silicide layer 116: shielding layer
118: surface treatment 120: resilient coating
122: mask layer 124: the anti-contact hole etching suspension layer of opening
126: resistance to compression contact hole etching suspension layer
Embodiment
Figure 1A to Fig. 1 E is the manufacturing process profile according to a kind of semiconductor element of a preferred embodiment of the present invention.
Please refer to Figure 1A, in substrate 100, be formed with I/O element (input/output device) 10a, 10b and core parts (core device) 11a, 11b, and the I/O element is divided into I/O PMOS 10a and I/O NMOS 10b two kinds, core parts are divided into core PMOS 11a and core NMOS 11b two kinds with isolation structure 102.And normally partly leading transistor by the golden oxygen with gate dielectric layer 104, grid 106, clearance wall 108, lightly doped drain 110, source electrode and drain electrode 112, core parts 11a, 11b and I/O PMOS 10a, I/O NMOS10b constituted.The mode that wherein forms source electrode and drain electrode 112 has a lot of selections; For instance; the method that can adopt general ion to inject; perhaps can adopt the mode of the semi-conducting material that recharges to form the source electrode and the drain electrode (SiGe refilled S/D) of recharging as SiGe; and between grid 106 sidewalls and clearance wall 108, can form a compensate for clearance wall (offsetspacer) 107 earlier usually, its material for example is a silica.
Then, please refer to Figure 1B, form layer of metal silicide layer 114 in the surface of grid 106, source electrode and drain electrode 112, its material for example is metal silicides such as cobalt silicide, nickle silicide, tungsten silicide, titanium silicide, palladium silicide, tantalum silicide, platinum silicide.
Then, please refer to Fig. 1 C-1 and Fig. 1 C-2, these two figure represent respectively and utilize two kinds of different technologies to form resilient coating of the present invention (buffer layer) 120.Be example with Fig. 1 C-1 earlier, on the I/O NMOS 10b beyond the I/O PMOS10a and core PMOS 11a and core NMOS 11b, form one deck shielding layer 116, again one surface treatment 118 carried out in substrate 100, and formed resilient coating 120 in the surface of I/O PMOS 10a.Wherein, resilient coating 120 for example is a sull, and its thickness is for example between 10 dusts～200 dusts, so can not impact the resistance (Rs) of metal silicide layer 114.And above-mentioned surface treatment 118 can be one lower oxygen plasma treatment (O of power
2Plasmatreatment), it can comprise physical gas-phase deposition (PECVD) or use photoresist to peel off with instrument (STRIP tool) and handle.For instance, the conditional parameter of oxygen plasma treatment for example: 1) use N
2O is as handling gas, 2) gas flow is about 100～1000sccm, 3) processing time between 20～100 seconds, 4) power when handling is about 200～1000W.In addition, because the resilient coating 120 that forms by oxygen plasma treatment can not have influence on other element, thus also can be directly and be formed on all sidedly in the substrate 100, and do not need to use as the shielding layer among Fig. 1 C-1 116.
In addition, also can select the technology of Fig. 1 C-2 to form resilient coating 120, for example utilize chemical vapor deposition method earlier, in substrate 100, deposit one deck resilient coating (not illustrating) all sidedly, remove I/OPMOS 10a resilient coating in addition again.And the aforementioned method that removes resilient coating can form one deck mask layer 122 earlier on I/O PMOS 10a, again with this mask layer 122 as etching mask, the resilient coating on I/ONMOS 10b and core PMOS 11a and the core NMOS 11b is removed in etching.
Subsequently, please refer to Fig. 1 D, is with after forming resilient coating 120 through surface treatment 118 (asking for an interview Fig. 1 C-1) or the mode (asking for an interview Fig. 1 C-2) of deposition before no matter, all needs first shielding layer 116 or mask layer 122 to be removed.And remaining this layer resilient coating 122 is because can stop that hydrogen is diffused into Si and SiO
2The interface, so can reduce the back bias voltage temperature instability (NBTI) of I/O PMOS 10a.Then, on I/O NMOS 10b and core NMOS 11b, can cover the anti-contact hole etching suspension layer (tensile CESL) 124 of opening of one deck.
Afterwards, please refer to Fig. 1 E, on core PMOS 11a, cover one deck resistance to compression contact hole etching suspension layer (compressive CESL) 126.
In addition, the formation of above-mentioned Fig. 1 D and Fig. 1 E order can be complied with required exchanging.And, because I/O PMOS10a is connected in external power source, its gate dielectric layer 104 general elements are thick, and the quality of I/O element does not lie in speed but in reliability, because of its external voltage that bears is big far beyond general element, so resilient coating 120 surfaces in Fig. 1 D or Fig. 1 E need not add contact hole etching suspension layer (CESL).But, because the formation of above-mentioned two kinds of contact hole etching suspension layers all is comprehensive deposition.So, can when Fig. 1 D, also can select on the resilient coating 120 of I/O PMOS 10a, to form simultaneously the anti-contact hole etching suspension layer 124 of opening.In like manner, when Fig. 1 E, can select on the resilient coating 120 of I/O PMOS 10a, to form simultaneously above-mentioned resistance to compression contact hole etching suspension layer 126.
For confirming usefulness of the present invention, please refer to Fig. 2, it is according to the abovementioned embodiments of the present invention I/OPMOS and the NBTI of existing I/O PMOS assessment curve chart.Wherein transverse axis is that stress time (stresstime), the longitudinal axis are Vts change (shift).Can learn that from Fig. 2 the position of curve of the present invention is more existing I/O PMOS and have only the element that forms resistance to compression contact hole etching suspension layer low obviously; That is to say that under same stress time, Vts change of the present invention is starkly lower than other structure.
In sum, in semiconductor element of the present invention,, stop that hydrogen is diffused into Si and SiO because the very thin resilient coating of the one deck of formation is arranged
2The interface, so can reduce the back bias voltage temperature instability (NBTI) of I/O PMOS.In addition, resilient coating of the present invention is because as thin as a wafer, so can't impact the resistance (Rs) of the metal silicide layer in the element.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (15)
1. the manufacture method of a semiconductor element comprises:
Substrate is provided;
Form a plurality of I/O elements and a plurality of core parts in this substrate, wherein those I/O elements comprise a plurality of I/O PMOS and a plurality of I/O NMOS, and those core parts comprise a plurality of core PMOS and a plurality of core NMOS;
In this substrate, form resilient coating;
Remove those I/O PMOS surfaces this resilient coating in addition;
Go up the anti-contact hole etching suspension layer of opening of covering in those I/O NMOS and those cores NMOS; And
Go up covering resistance to compression contact hole etching suspension layer in those cores PMOS.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein this resilient coating comprises sull.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein the thickness of this resilient coating is between 10 dusts～200 dusts.
4. the manufacture method of semiconductor element as claimed in claim 1, the step that wherein forms this resilient coating comprises:
On those I/O NMOS beyond those I/O PMOS and those core parts, form shielding layer; And
Surface treatment is carried out in this substrate, to form this resilient coating in this substrate surface.
5. the manufacture method of semiconductor element as claimed in claim 4, the step that wherein removes this resilient coating beyond those I/OPMOS surfaces comprise by removing this shielding layer and remove this resilient coating simultaneously.
6. the manufacture method of semiconductor element as claimed in claim 4, wherein this surface treatment comprises oxygen plasma treatment.
7. the manufacture method of semiconductor element as claimed in claim 6, wherein this oxygen plasma treatment comprises physical gas-phase deposition or uses photoresist to peel off with instrument and handle.
8. the manufacture method of semiconductor element as claimed in claim 1, the method that wherein forms this resilient coating comprises chemical vapor deposition method.
9. the manufacture method of semiconductor element as claimed in claim 1 wherein comprises this resilient coating that covers simultaneously on those I/O PMOS when those cores PMOS goes up this resistance to compression contact hole etching suspension layer of covering.
10. the manufacture method of semiconductor element as claimed in claim 1 wherein comprises this resilient coating that covers simultaneously on those I/OPMOS when those I/O NMOS and this anti-contact hole etching suspension layer of the last covering of those cores NMOS.
11. a semiconductor element comprises:
Substrate;
A plurality of I/O elements are positioned in this substrate, and wherein those I/O elements comprise a plurality of I/O POMS and a plurality of I/O NMOS;
A plurality of core parts are positioned in this substrate, and wherein those core parts comprise a plurality of core POMS and a plurality of core NMOS;
Resilient coating is positioned at the surface of those I/O PMOS;
The anti-contact hole etching suspension layer of opening is covered on those I/O NMOS and those cores NMOS; And
Resistance to compression contact hole etching suspension layer is covered on those cores PMOS.
12. semiconductor element as claimed in claim 11, wherein this resilient coating comprises sull.
13. semiconductor element as claimed in claim 11, wherein the thickness of this resilient coating is between 10 dusts～200 dusts.
14. semiconductor element as claimed in claim 11, wherein this resistance to compression contact hole etching suspension layer also comprises and being covered on this resilient coating.
15. semiconductor element as claimed in claim 11 wherein should resist a contact hole etching suspension layer also to comprise and be covered on this resilient coating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101280081A CN101136370B (en) | 2006-08-31 | 2006-08-31 | Semiconductor component and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101280081A CN101136370B (en) | 2006-08-31 | 2006-08-31 | Semiconductor component and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136370A CN101136370A (en) | 2008-03-05 |
| CN101136370B true CN101136370B (en) | 2010-06-09 |
Family
ID=39160351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101280081A Active CN101136370B (en) | 2006-08-31 | 2006-08-31 | Semiconductor component and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101136370B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112908855A (en) * | 2021-01-28 | 2021-06-04 | 上海华力集成电路制造有限公司 | Method for improving negative bias temperature instability of P pipe assembly |
| CN115692320A (en) * | 2021-07-22 | 2023-02-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040235236A1 (en) * | 2003-05-21 | 2004-11-25 | Thomas Hoffmann | Integrated circuit with improved channel stress properties and a method for making it |
| CN1269190C (en) * | 2002-11-19 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Method for making contact hole on top of nickel silicide layer |
-
2006
- 2006-08-31 CN CN2006101280081A patent/CN101136370B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1269190C (en) * | 2002-11-19 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Method for making contact hole on top of nickel silicide layer |
| US20040235236A1 (en) * | 2003-05-21 | 2004-11-25 | Thomas Hoffmann | Integrated circuit with improved channel stress properties and a method for making it |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101136370A (en) | 2008-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6551884B2 (en) | Semiconductor device including gate insulation films having different thicknesses | |
| CN100466291C (en) | Thin film transistor (TFT) device structure for reducing starting voltage deviation and its manufacture | |
| CN102938378B (en) | Manufacturing method for semiconductor device | |
| US8269281B2 (en) | Method for forming gate oxide of semiconductor device | |
| US20070218618A1 (en) | Interlayer dielectric under stress for an integrated circuit | |
| CN102110651B (en) | Semiconductor device and manufacturing method thereof | |
| JP2008504693A (en) | Complementary metal oxide semiconductor integrated circuit with NMOS and PMOS transistors using different gate dielectrics | |
| CN104347418A (en) | Forming method of MOS (Metal Oxide Semiconductor) transistor | |
| CN103377924B (en) | A kind of semiconductor structure and manufacture method thereof | |
| US8822317B2 (en) | Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact | |
| US9257519B2 (en) | Semiconductor device including graded gate stack, related method and design structure | |
| CN101136370B (en) | Semiconductor component and its manufacturing method | |
| CN104078341A (en) | Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure | |
| US20080230814A1 (en) | Methods for fabricating a semiconductor device | |
| US7928512B2 (en) | Semiconductor device | |
| JP2001332723A (en) | Method of manufacturing semiconductor device | |
| US7682890B2 (en) | Method of fabricating semiconductor device | |
| JP2001298095A (en) | Method of manufacturing mos semiconductor device | |
| US9099461B2 (en) | Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure | |
| US8735244B2 (en) | Semiconductor device devoid of an interfacial layer and methods of manufacture | |
| TWI256108B (en) | Method for manufacturing semiconductor device | |
| US20090007037A1 (en) | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures | |
| US20050142889A1 (en) | Method of forming oxide layer in semiconductor device | |
| US7524720B2 (en) | Method of manufacturing semiconductor device | |
| CN112640043A (en) | Method for forming silicon-containing layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |