CN101136356A - Copper interconnected fabricating method for semiconductor device and structure thereof - Google Patents
Copper interconnected fabricating method for semiconductor device and structure thereof Download PDFInfo
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- CN101136356A CN101136356A CNA2006100306281A CN200610030628A CN101136356A CN 101136356 A CN101136356 A CN 101136356A CN A2006100306281 A CNA2006100306281 A CN A2006100306281A CN 200610030628 A CN200610030628 A CN 200610030628A CN 101136356 A CN101136356 A CN 101136356A
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Abstract
This invention relates to a manufacturing method for semiconductor apparatuses connected by copper including providing a semiconductor substrate with a medium isolation layer and a copper layout layer inserted in the medium isolation layer, forming a diffusion blocking layer on the surface of the copper layout layer and the isolation layer, and the diffusion blocking layer is a TaN material in a face-centered cubic structure with an Al cushion layer formed on it. This invention also provides a structure based on this method, which changes the technology and structure of a deposited diffusion blocking layer by turning the crystal structure of TaN film from body-centered cubic structure to a face-centered cubic structure to be covered on the Cu layout layer.
Description
Technical field
The present invention relates to a kind of manufacture method and structure thereof of semiconductor device, particularly a kind of manufacture method of semiconductor device of copper-connection and structure thereof.
Background technology
Along with improving constantly of integrated circuit integrated level, Al has been difficult to the fine requirement of satisfying integrated circuit as its performance of intraconnections material.Cu has low resistivity than Al and high deelectric transferred ability is widely used in deep sub-micron technique.Yet Cu is again the arch-criminal who causes component failure, and this is main because Cu is a heavy metal species, under the situation of high temperature and added electric field, can be in semi-conductor silicon chip and silicon dioxide rapid diffusion, cause the problem of device reliability aspect.So, between Cu wiring layer and buffer layer, must add the diffusion barrier material that prevents the Cu diffusion, for example TaN, TiSiN, Ta wait the purpose that realizes preventing the Cu diffusion.
Simultaneously, along with the raising of chip integration, it is thinner, narrower, thinner that interconnecting line becomes, and therefore current density wherein is increasing.Under higher current density effect, the metallic atom in the interconnecting line will move along the electron motion direction, and this phenomenon is exactly electromigration (EM).Electromigration can make the interconnecting line among the IC produce in the course of the work to open circuit or short circuit, be a kind of important mechanisms that causes ic failure.So, add that between Cu wiring layer and buffer layer diffusion barrier material can also stop Cu that electromigration takes place, and can improve the adhesiveness of Cu and buffer layer in addition.
Disclosed in the past patent or document have a lot of open and reports to the diffusion impervious layer between Cu wiring layer and the buffer layer, be that 2004/0152301 and 2004/0152330 and 2005/0023686 U.S. Patent application prevents that by add diffusion impervious layer such as Ta and TaN, metal nitride and WSiN material between Cu wiring layer and buffer layer Cu from spreading to buffer layer as publication number, yet prevent measure for the diffusion of Cu in metal A l is unexposed.In deep submicron process, the metal gasket of making on top layer Cu wiring layer of drawing still adopts Al, because Cu can spread in the Al bed course, reacting generates the bigger CuAl of resistivity
2, therefore must between top layer Cu wiring layer and metal A l bed course, introduce barrier layer.
Ta is the diffusion impervious layer of a kind of very attractive Cu, and the nitride of Ta just is widely used in the Cu interconnection process at present such as effective barrier layer that TaN is a kind of Cu and F ion.But in common technology, the TaN structure of formation is more loose, the ability that prevents the Cu diffusion a little less than.Illustrate below with reference to Fig. 1 to Fig. 5, in the 90nm logical circuit, Cu wiring layer 12 is formed on the Semiconductor substrate 11, then on Cu wiring layer 12, form TaN as the diffusion impervious layer 13 that prevents the Cu diffusion, on diffusion impervious layer 13, form Al bed course 14 at last, total as shown in Figure 1, because the structure of diffusion impervious layer 13 is more loose, especially bad in metal step place spreadability, form in " weak district ", the Cu in the top layer Cu wiring layer 12 often passes diffusion impervious layer 13 in this " weak district ", arrive Al bed course 14, the cavity 15 that forms in top layer Cu simultaneously, Cu16 that diffuses out and Al bed course 14 react, and generate the big CuAl of resistivity
2, influence device performance.
Adopt X-ray diffraction (XRD) to determine the crystal structure of the diffusion impervious layer 13 of prior art for preparing, the result as shown in Figure 5, abscissa shown in Figure 5 is the angle of diffraction 20, unit is degree, ordinate is the ratio I/I of diffracted intensity
0The TaN diffusion impervious layer 13 of preparation is 37 °, 53 ° and 68 ° 20 respectively and locates to occur more intense diffraction maximum, contrast with standard spectrum, corresponding to the diffraction of (110), (200) and (211) crystal face, the crystal structure of TaN is body-centered cubic (bcc) structure respectively at these peaks.
Adopt HCl corrosion part A l bed course, utilize the remaining Al bed course of observation by light microscope, the result as shown in Figure 2, exist many black to stain 21 in the Al mat surface, as everyone knows, Cu can not react with HCl, adopt energy disperse spectroscopy (EDX) to test the composition of these black contaminations 21 simultaneously, be mainly Cu and O, show Cu in the Cu wiring layer 12 pass diffusion impervious layer 13 be diffused in the Al bed course 14 and also part oxidized, this shows body-centered cubic structure TaN prevent that the Cu diffusivity is relatively poor.
Adopt focusing of ion beam (FIB) section to test the cross section pattern of the top layer Cu wiring layer 12 of said structure, the result as shown in Figure 3, the cavity appears in Cu wiring layer 12, the result of this result and top light microscope and EDX is consistent, and promptly the Cu in the Cu wiring layer 12 spreads out and causes forming cavity 15 in the Cu wiring.
Tested on the same wafer inefficacy that comes analysis device from electromigration (EM) characteristic of 15 unit of S31 to S45, the result as shown in Figure 4, as can be seen, cell S 31 has just formed the resistance peak as far back as 2 hours, the resistance peak had all appearred in remaining element before 10 hours, show that these unit the cavity occurred in 10 hours of test, caused component failure.
By top discussion as can be known, the TaN diffusion impervious layer of body-centered cubic structure prevent that Cu diffusion and electromigration ability are a little less than.As everyone knows, electromigration and the diffusion of Cu by barrier material mainly occurs along the grain boundary of barrier material, therefore needs to optimize barrier material, thereby minimizes the grain boundary district and/or prolong the evolving path along the grain boundary.
Summary of the invention
The problem that the present invention solves is that the Cu in the Cu wiring layer in the semiconductor device spreads in the Al bed course, corrodes the Al bed course, thereby causes device performance to lose efficacy.
For addressing the above problem, the invention provides a kind of preparation method of semiconductor device of Cu interconnection, comprise the steps: to provide the Semiconductor substrate that has buffer layer and copper wiring layer, described copper wiring layer is embedded in the buffer layer; On described dielectric isolation laminar surface and copper wiring layer, form diffusion impervious layer; Form aluminum cushion layer on diffusion impervious layer, described diffusion impervious layer is the tantalum-nitride material of face-centred cubic structure.
Diffusion impervious layer can adopt physical vapor deposition (PVD) or chemical vapor deposition (CVD) or vacuum electronic beam evaporation or the formation of pulsed laser deposition (PLD) method, and the method for comparative optimization is for adopting the method for physical vapor deposition (PVD).
The deposition power scope that adopts the physical vapor deposition (PVD) method to form diffusion impervious layer is 3000W to 8000W, and atmosphere is N
2, N
2Range of flow be 25sccm to 55sccm.
The diffusion impervious layer thickness range is 30nm to 100nm.
The face-centered cubic crystal structure of diffusion impervious layer can form in deposition, also can annealing realize after deposition.
Diffusion impervious layer can be made of the TaN of individual layer or multilayer face-centred cubic structure.
Correspondingly, the invention provides a kind of semiconductor device structure of Cu interconnection, comprise the Semiconductor substrate that has buffer layer and copper wiring layer, described copper wiring layer is embedded in the buffer layer; Be positioned at the diffusion impervious layer on dielectric isolation laminar surface and the copper wiring layer and be positioned at aluminum cushion layer on the diffusion impervious layer, described diffusion impervious layer is the tantalum nitride of face-centred cubic structure.
The present invention also provides a kind of manufacture method of semiconductor device of copper-connection, comprises the steps: to provide the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Formation contacts rete with the dielectric isolation laminar surface at described copper wiring layer; On the contact rete, form diffusion impervious layer; Form aluminum cushion layer on diffusion impervious layer, described diffusion impervious layer is the tantalum-nitride material of face-centred cubic structure.
Described contact rete is made of any metal in platinum family element, the iron family element.
The present invention also provides a kind of semiconductor device structure of copper-connection, comprises the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Be positioned at the rete that contacts of copper wiring layer and dielectric isolation laminar surface; Be positioned at contact on the rete diffusion impervious layer and be positioned at aluminum cushion layer on the diffusion impervious layer, described diffusion impervious layer is the tantalum nitride of face-centred cubic structure.
Compared with prior art, the present invention has the following advantages: the present invention is by changing the technology of deposition diffusion impervious layer, the crystal structure that has changed diffusion impervious layer is a face-centred cubic structure, thereby the grain boundary district on minimizes diffusion barrier layer, prolonged the evolving path of copper along the grain boundary, make that the diffusion impervious layer that covers on the Cu wiring layer is more fine and close, especially can cover " the weak district " of metal platform exponent part better, stopped that copper especially spreads and electromigration by " the weak district " of metal platform exponent part to the Al bed course, prevented that the Al bed course from suffering erosion.
Description of drawings
Fig. 1 is the Cu wiring layer on the Semiconductor substrate of prior art for preparing and the structural profile schematic diagram of Al bed course.
Fig. 2 is the XRD result of the diffusion impervious layer of prior art for preparing
Fig. 3 is the light micrograph after the Al bed course of prior art for preparing adopts the HCl corrosion.
Fig. 4 is the cross section FIB test result of the Cu wiring layer of prior art for preparing.
Fig. 5 is the EM test result of the Cu wiring layer of prior art for preparing.
Fig. 6 A to Fig. 6 B is the first embodiment schematic diagram of the diffusion impervious layer of the technology of the present invention preparation.
Fig. 7 is the XRD result who adopts the diffusion impervious layer of the technology of the present invention preparation.
Fig. 8 is the SEM photo after the Al bed course of technology preparation of the present invention adopts the HCl corrosion.
Fig. 9 is the cross section FIB test result of the Cu wiring layer of technology preparation of the present invention.
Figure 10 A is the TTF logarithm normal distribution curve of EM test result of the Cu wiring layer of technology of the present invention preparation.
Figure 10 B is the relative resistance value degenerated curve of EM test result that adopts the Cu wiring layer of technology preparation of the present invention.
Figure 11 A to Figure 11 B is the second embodiment schematic diagram of the diffusion impervious layer of the technology of the present invention preparation.
Embodiment
Below describe specific embodiment in detail by the foundation accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:
Present embodiment has at first provided the manufacture method of the semiconductor device of copper-connection, and processing step is: the Semiconductor substrate that has buffer layer and copper wiring layer is provided, and described copper wiring layer is embedded in the buffer layer; Form diffusion impervious layer at described copper wiring layer and dielectric isolation laminar surface; Form aluminum cushion layer on diffusion impervious layer, described diffusion impervious layer is the tantalum-nitride material of face-centred cubic structure.
Fig. 6 A to Fig. 6 B adopts preparation method of the present invention to form the first embodiment schematic diagram of diffusion impervious layer between top layer Cu on the Semiconductor substrate and upper strata Al bed course.Below in conjunction with accompanying drawing the specific embodiment of the present invention is done a detailed explanation.Fig. 6 A is the structural representation that Cu wiring layer on Semiconductor substrate and dielectric isolation laminar surface form diffusion impervious layer.Semiconductor substrate 61 has buffer layer 62 and Cu wiring layer 63, Cu wiring layer 63 is embedded in the buffer layer 62, form diffusion impervious layer 64 at Cu wiring layer 63 and buffer layer 62 surfaces, described diffusion impervious layer 64 is made of the TaN of face-centred cubic structure.
The substrate of the semiconductor device structure that described Semiconductor substrate 61 is constituted for one deck or multilayer conductive layer and insulating barrier.
Described buffer layer 62 can be individual layer or multilayer, by SiO
2, USG (undoped silicate glass), BPSG (boron-phosphorosilicate glass), PSG (phosphorosilicate glass), SiN, SiON, SiOF, AlN, Al
2O
3, the constituting of at least a in the group such as BN, diamond like carbon, SOG (spin-coating glass), FOX (flowable oxide), polymer and they.
Described Cu wiring layer 63 adopts known photoetching and lithographic technique to form, and Cu wiring layer 63 is formed for the Cu film that can be individual layer or multilayer.
Described diffusion impervious layer 64 can be individual layer or multilayer, and the thickness range of diffusion impervious layer 64 is 30 to 100nm scopes.Diffusion impervious layer 64 can adopt physical vapor deposition (PVD), chemical vapor deposition (CVD) or vacuum evaporation, pulsed laser deposition (PLD) or other existing plated film modes to form.The preparation method of comparative optimization is the physical vapor deposition (PVD) mode, selects for use metal Ta to make target, and the deposition power scope is 3000W to 8000W, and the atmosphere of deposition is Ar and N
2Mist, N
2Range of flow be 25sccm to 55sccm, the underlayer temperature scope is 80 to 150 ℃ in the time of deposition.
The face-centered cubic crystal structure of diffusion impervious layer 64 can form in deposition process, also can adopt in-situ annealing or be displaced to form face-centred cubic structure in the annealing furnace such as body-centered cubic structure after being deposited as other crystal structures.
In an embodiment of the invention, adopt Ta to make target, utilize the PVD device, 1.3 * 10
-2To 1.3 * 10
-1Under the Pa air pressure, at N
2Under the atmosphere of Ar, N
2Flow be 40sccm, under 120 ℃, form the TaN film with the deposition rate of per second 1.5nm, deposition power is 5500W, the thickness of the TaN film of formation is 65nm, the crystal structure of TaN film is a face-centred cubic structure.
In yet another embodiment of the present invention, utilize the PVD device, 1.3 * 10
-2Pa to 6.5 * 10
-2Under the Pa air pressure, at N
2Under the mixed atmosphere of Ar, N
2Flow is 10sccm, and with the deposition rate formation TaN film of per second 1.5nm, deposition power is 9000W, and the thickness of the TaN film of formation is 70nm, and the crystal structure of TaN film is a body-centered cubic structure.
Then at N
2Under the atmosphere, utilize quick anneal oven (RTA), under 80 ℃ to 450 ℃ temperature, annealing in process 30s to the 300s time, the heating rate of annealing process is 10 to 30 ℃/s, and rate of temperature fall is 5 to 30 ℃/s.The TaN membrane structure that annealed back forms is a face-centred cubic structure, and this TaN layer is as the diffusion impervious layer 64 of anti-Cu diffusion.
With reference to Fig. 6 B is to form Al bed course 65 structural representations on diffusion impervious layer 64.Al bed course 65 can be individual layer or multilayer, and the thickness range of Al bed course is 9500 to 10500 , and the figure of Al bed course adopts known photoetching and lithographic technique to form.
In a specific embodiment of the present invention, adopt Al to make target, utilize the PVD device, 2.6 * 10
-1Under the Pa air pressure, under Ar atmosphere, under 270 ℃ of temperature, with the deposition rate formation Al film of per second 167 , deposition power is 22000W.
In conjunction with Fig. 6 A to Fig. 6 B, and the description of above-mentioned technology, the present invention provides the specific embodiment of a preparation diffusion impervious layer between Cu wiring layer and Al bed course, and is as follows:
On Semiconductor substrate 61, form buffer layer 62 and Cu wiring layer 63, Cu wiring layer 63 forms for adopting known photoetching and lithographic technique, form diffusion impervious layer 64 at Cu wiring layer 63 that exposes and buffer layer 62 surfaces, diffusion impervious layer 64 adopts the physical vapor deposition (PVD) mode to form.Select for use metal Ta to make target and form the TaN film, deposition power is 6500W, and the atmosphere of deposition is N
2, N
2Flow be 30sccm, the underlayer temperature scope is 100 ℃ in the time of deposition.Adopting the crystal structure of the TaN diffusion impervious layer 64 of this technology formation is face-centred cubic structure, and the thickness of TaN diffusion impervious layer 64 is 80nm.
On diffusion impervious layer 64, form Al bed course 65 at last.The thickness of Al bed course 65 is 1000nm.
After above process implementing, obtain final structure for shown in Fig. 6 B.Comprise the Semiconductor substrate that has buffer layer 62 and Cu wiring layer 63, Cu wiring layer 63 is embedded in the buffer layer 62, be positioned at the diffusion impervious layer 64 on Cu wiring layer 63 and buffer layer 62 surfaces and be positioned at Al bed course 65 on the diffusion impervious layer 64, diffusion impervious layer 64 is that the TaN of face-centred cubic structure constitutes.
Adopt Britain hundred to get the BedeMetrix of (Bcde) company
TMThe X-ray diffractometer of-F model has been tested the X ray diffracting spectrum (XRD) of above-mentioned diffusion impervious layer 64, the result as shown in Figure 7, the TaN diffusion impervious layer 64 of preparation is 35.847 °, 41.603 °, 60.414 ° and 72.222 ° 20 respectively and locates to occur more intense diffraction maximum, these peaks are respectively on the diffraction surfaces corresponding to (111), (200), (220) and (331), contrast with standard spectrum, the crystal structure of TaN is face-centered cubic (fcc) structure.
Adopting HCl to corrode above-mentioned part A l bed course pattern afterwards adopts western come card (Leica) the Inm300 model light microscope of exerting optical instrument Co., Ltd to test, the result as shown in Figure 8, Al bed course 65 surface ratios are clean and smooth, the black that does not occur among Fig. 3 stains 21, showing does not have Cu to diffuse in the Al bed course 65, shows that the TaN diffusion impervious layer 64 of the face-centred cubic structure of the technology of the present invention preparation prevents that Cu from spreading and the electromigration ability is better.
Correspondingly, adopt the U.S. take preparation of (Fei) company DB235 type focusing of ion beam (FIB) testing of equipment the cross section pattern of Cu wiring layer 63, the result as shown in Figure 9, Cu wiring layer 63 is evenly continuous, cavity shown in Figure 4 do not occur, show that Cu wiring layer 63 does not spread.
Simultaneously, after adopting the diffusion impervious layer 64 of the technology of the present invention formation, tested the electromigration characteristic of Cu wiring layer 63, at the peculiar limit (Qulitau of company of Kui Li, Ltd.) carry out in electromigration (EM) system, the result is shown in Figure 10 A and 10B, Figure 10 A provides the TTF logarithm normal distribution curve of different units electromobility on the wafer of finishing wiring, these unit began at 75 hours to occur losing efficacy as can be seen, curve ratio is more steep, shows that diffusion impervious layer 64 blocking effects that adopt the present invention to prepare are relatively good.In the unit of all tests, half occurs losing efficacy in the unit of approximately testing in 150 hours, and then at about about 180 hours, because the electromigration characteristic of Cu self, all unit all lost efficacy.
Figure 10 B provides relative resistance degenerated curve, and as can be seen, before 75 hours, resistance remains unchanged, and occurs because the resistance that the cavity that electromigration occurs causes increases the peak afterwards, and at about 180 hours, the top appearred in the increase of resistance.This is owing to due to the electromigration of Cu self, show this moment because the empty volume maximum that electromigration occurs causes the resistance maximum.Compare (result as shown in Figure 5) with diffusion impervious layer with the Cu wiring layer that adopts prior art for preparing, resistance just occurs at 10 hours among Fig. 5 and increase the peak, show that having occurred the cavity in the Cu line causes resistance to increase, and after changing diffusion impervious layer preparation technology, the cavity did not appear in Cu wiring layer 63 before the electromigration characteristic of Cu self occurs, corresponding with the light microscope result of Fig. 7, show formation face-centred cubic structure of the present invention TaN diffusion impervious layer 64 stop that Cu diffusion and electromigration ability are relatively good.
Figure 11 A to Figure 11 B adopts preparation method of the present invention to form the schematic diagram of second embodiment of diffusion impervious layer between top layer Cu on the Semiconductor substrate and upper strata l bed course.Below in conjunction with accompanying drawing the specific embodiment of the present invention is done a detailed explanation.Figure 11 A is the structural representation that Cu wiring layer on Semiconductor substrate and dielectric isolation laminar surface form diffusion impervious layer.Semiconductor substrate 61 has buffer layer 62 and Cu wiring layer 63, Cu wiring layer 63 is embedded in the buffer layer 62,62 surface formation contact rete 71 with buffer layer at Cu wiring layer 63, form diffusion impervious layer 72 on contact rete 71, described diffusion impervious layer 64 is made of the TaN of face-centred cubic structure.
Diffusion impervious layer 72 adopts the method among the embodiment one to form, and is not described further at this.
With reference to Figure 11 B is to form Al bed course 73 schematic diagrames on diffusion impervious layer 72, and the figure of Al bed course adopts known photoetching and lithographic technique to form.
After above process implementing, obtain final structure for shown in Figure 11 B.Comprise the Semiconductor substrate that has buffer layer 62 and Cu wiring layer 63, Cu wiring layer 63 is embedded in the buffer layer 62, and what be positioned at Cu wiring layer 63 and buffer layer 62 surfaces contacts rete 71; Be positioned at contact on the rete 71 diffusion impervious layer 72 and be positioned at aluminum cushion layer 73 on the diffusion impervious layer 72, the tantalum nitride formation that described diffusion impervious layer 72 be a face-centred cubic structure.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the manufacture method of the semiconductor device of a copper-connection comprises the steps: to provide the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Form diffusion impervious layer at described copper wiring layer and dielectric isolation laminar surface; Form aluminum cushion layer on diffusion impervious layer, it is characterized in that, described diffusion impervious layer is the tantalum-nitride material of face-centred cubic structure.
2. the preparation method of the semiconductor device of copper-connection according to claim 1 is characterized in that: described diffusion impervious layer can adopt physical vapour deposition (PVD) or chemical vapour deposition (CVD) or vacuum electronic beam evaporation or pulse laser sediment method to form.
3. the preparation method of the semiconductor device of copper-connection according to claim 2, it is characterized in that: the deposition power scope that described physical gas-phase deposite method forms diffusion impervious layer is 3000W to 8000W, the atmosphere that forms diffusion impervious layer is nitrogen, and the range of flow of nitrogen is 25sccm to 55sccm.
4. according to the preparation method of claim 1 or 2 or 3 described semiconductor device, it is characterized in that: described diffusion impervious layer thickness range is 30nm to 100nm.
5. according to the manufacture method of claim 1 or 2 or 3 described semiconductor device, it is characterized in that: the tantalum nitride of described face-centred cubic structure is individual layer or sandwich construction.
6. the manufacture method of the semiconductor device of a copper-connection comprises the steps: to provide the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Formation contacts rete with the dielectric isolation laminar surface at described copper wiring layer; On the contact rete, form diffusion impervious layer; Form aluminum cushion layer on diffusion impervious layer, it is characterized in that, described diffusion impervious layer is the tantalum-nitride material of face-centred cubic structure.
7. the manufacture method of semiconductor device according to claim 6, it is characterized in that: described contact rete is made of any metal in platinum family element, the iron family element.
8. the semiconductor device structure of a copper-connection comprises the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Be positioned at the diffusion impervious layer of copper wiring layer and dielectric isolation laminar surface and be positioned at aluminum cushion layer on the diffusion impervious layer, it is characterized in that described diffusion impervious layer is the tantalum nitride of face-centred cubic structure.
9. the semiconductor device structure of copper-connection according to claim 8, it is characterized in that: the tantalum nitride of described face-centred cubic structure is individual layer or sandwich construction.
10. the semiconductor device structure of a copper-connection comprises the Semiconductor substrate that has buffer layer and copper wiring layer, and described copper wiring layer is embedded in the buffer layer; Be positioned at the rete that contacts of copper wiring layer and dielectric isolation laminar surface; Be positioned at contact on the rete diffusion impervious layer and be positioned at aluminum cushion layer on the diffusion impervious layer, it is characterized in that described diffusion impervious layer is the tantalum nitride of face-centred cubic structure.
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| CN102024767B (en) * | 2009-09-09 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer edge film structure and formation method thereof |
| CN106133930A (en) * | 2014-03-31 | 2016-11-16 | 索尼公司 | Semiconductor unit, semiconductor device, light-emitting device, display device and method, semi-conductor device manufacturing method |
| CN111584383A (en) * | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Method for judging blocking capability of copper diffusion blocking layer and structure thereof |
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| CN101882587B (en) * | 2009-05-04 | 2012-03-28 | 中芯国际集成电路制造(北京)有限公司 | Structure for achieving wire bonding and packaging and production method thereof |
| US20100314765A1 (en) * | 2009-06-16 | 2010-12-16 | Liang Wen-Ping | Interconnection structure of semiconductor integrated circuit and method for making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6077780A (en) * | 1997-12-03 | 2000-06-20 | Advanced Micro Devices, Inc. | Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure |
| US6140231A (en) * | 1999-02-12 | 2000-10-31 | Taiwan Semiconductor Manufacturing Company | Robust diffusion barrier for Cu metallization |
| TW518680B (en) * | 2001-06-13 | 2003-01-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
| US20050215048A1 (en) * | 2004-03-23 | 2005-09-29 | Lei Li | Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits |
| US20060113675A1 (en) * | 2004-12-01 | 2006-06-01 | Chung-Liang Chang | Barrier material and process for Cu interconnect |
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| CN102024767B (en) * | 2009-09-09 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer edge film structure and formation method thereof |
| CN106133930A (en) * | 2014-03-31 | 2016-11-16 | 索尼公司 | Semiconductor unit, semiconductor device, light-emitting device, display device and method, semi-conductor device manufacturing method |
| CN111584383A (en) * | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Method for judging blocking capability of copper diffusion blocking layer and structure thereof |
| US12027462B2 (en) | 2020-05-14 | 2024-07-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method and structure for determining blocking ability of copper diffusion blocking layer |
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