CN101131848B - Circuit and method for processing signal - Google Patents
Circuit and method for processing signal Download PDFInfo
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- CN101131848B CN101131848B CN2007101456967A CN200710145696A CN101131848B CN 101131848 B CN101131848 B CN 101131848B CN 2007101456967 A CN2007101456967 A CN 2007101456967A CN 200710145696 A CN200710145696 A CN 200710145696A CN 101131848 B CN101131848 B CN 101131848B
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Abstract
The present invention relates to a signal processing circuit and a signal processing method for converting FM modulation signals into digital data. The purpose of the present invention is to provide a signal processing circuit and a signal processing method capable of eliminating the influence of noise content to perform detection during a high level period or/and a low level period of the input pulse signal. The solving means comprises the following: providing input pulse signal and clock according to the level and the output clock of input pulse signal clearing the output of counting value and counting the clock based on the output pulse signal and setting or resetting the output pulse signal in accordance with the counting value.
Description
The application is an original application application number 02104636.0, and on February 10 2002 applying date, denomination of invention is divided an application for " signal processing circuit and signal processing method ".
Technical field
The invention relates to signal processing circuit and signal processing method, particularly about making FM (Frequency Modulation) modulating signal be converted to signal processing circuit and the signal processing method of numerical data (digital data).
Background technology
Fig. 6 represents square frame (block) pie graph of optical disc apparatus, and Fig. 7 represents to illustrate the pie graph of CD.
Optical disc apparatus 100 shown in Figure 6 for example is CD-R (Compact Disc Recorderable:CD-R etch-recordable type) CD-ROM drive, and installing CD-R discs 40 is carried out recording of information/regeneration to CD-R discs 40.
CD-R discs 40 forms along recording of information/regeneration rail (track) 40a as shown in Figure 7 and rocks (wobble) 40b.Rock (wobble) 40b through the FM modulation, make and rock (wobble) 40b regeneration, to regenerated signal carry out the FM demodulation and the FM restituted signal, the various control informations that can write down with the FM restituted signal.
Optical disc apparatus 100, by optical system 41, Spindle Motor (spindle motor) 42, sled motor (thread motor) 43, laser driver (laser driver) 44, preceding monitor (frontmonitor) 45, ALPC automatic laser power control (auto laser power control) circuit 46, record compensating circuit 47, rock (wobble) signal processing part 48, RF (radio frequency) amplifier (RF:radio frequency) 49, focus on (focus)/seek rail (tracking) servo (servo) circuit 50, transmit servo (servo) circuit 51, main axle servo (spindle servo) circuit 52, CD (CD) coding (encode)/decoding (decode) circuit 53, D/A (digital-to-analog) converter (converter) 54, sound intensifier (audio amplifier) 55, RAM (random access memory) 56,58, CD-ROM (compact disc read-only memory) coding (encode)/decoding (decode) circuit 57, interface (interface)/buffer control unit (buffer controller) 59, CPU (central processing unit) 60 constitutes, and response is carried out recording of information/regeneration from the instruction (command) of main frame (hostcomputer) 61.
Spindle Motor (spindle motor) 42 makes discs 40 turn round with decided winding number by main axle servo (spindle servo) circuit 52.Subtend configuration optical system 4l in discs 40.Optical system 4l makes information be recorded in discs (disc) 40 to discs 40 irradiating lasers (1aser) light, simultaneously, from the reflected light of discs (disc) 40, responsing recording information, output regenerated signal.Optical system 41 is according to Spindle Motor (spindle motor) 43, focusing (focus)/seek rail (tracking) servo (servo) circuit 50, and the position of light beam (beam) B of CD (disc) is shone in control.
Wherein, sled motor (thread motor) 43 makes the carrier (carriage) that constitutes optical system 41 move to the radial direction of discs (disc) 40 by the drive controlling that transmits servo (servo) circuit 51.And, focus on (focus)/seek rail (tracking) servo (servo) circuit 50 and drive the focusing (focus) of control optical system 41 and seek rail (tracking) actuator that (actuatoD (not icon) is to control focusing (focus)/seek rail (tracking).
Regenerated signal in optical system 41 regeneration is supplied with RF (radio frequency) amplifier 49.RF amplifier 49 amplifies regenerated signal, and the main signal among the regenerated signal is supplied with CD (CD) coding (encode)/decoding (decode) circuit 53 and deciphered.And, take out various servo (servo) signal to each servo (servo) control circuit output.
The processing that coding (encode)/decoding (decode), the initial code (header) of the error correction coding ECC (Error Correction Coding) that CD-ROM coding (encode)/57 couples of CD-ROM of decoding (decode) circuit are intrinsic detects etc.RAM56 is with being CD-ROM coding (encode)/decoding (decode) circuit 57 handled operation field of storage.Carry out at interface (interface)/buffer control unit (buffer controller) the 59th and the data of main frame (host computter) 61 are taught, the control of data buffering (data buffer).It is the operation field of storage of interface (interface)/buffer control unit (buffer controller) 59 that RAM58 uses.
And, when discs (disc) 40 is sound CD (audio disc), signal in CD coding (encode)/decoding (decode) circuit 53 demodulation is delivered to D/A converter (conveIrter) 54, be converted to simulation (analog) by numeral (digita1), amplify output by sound intensifier (audio amplifier) 55 again.
CPU60 carries out all control of device according to the instruction (command) of main frame (host computter) 61.
The CD of CD-R etc. is pre-formed along the rail (track) that should form by recorded information and rocks (wobble), according to rocking (wobble) and rock (wobble) signal with regeneration by detecting this.Rock (wobble) signal through the FM modulation, this FM modulating signal is converted to numerical data (digitaldata), can represent the address information such as (address) of CD position.At this moment, for obtaining correct address information such as (address), need make the FM modulating signal correctly be converted to numerical data.
Fig. 8 represents the block scheme of the signal processing circuit of a known example.And Fig. 9～Figure 12 represents the sequential chart (timing chart) of common known signal treatment circuit.
At Fig. 8, signal processing circuit 500 by two edges (edge) detecting circuit 501, the counting (counter) circuit 502, latch (1atch) circuit 503, digital LPF circuit 504 is constituted.
The FM modulating signal that two edges (, edge) detecting circuit 501 is supplied with shown in Fig. 9 A by terminal 505.Two edges detecting circuit 501, at first, the FM modulating signal of supply is compared with zero accurate position (zero leve1), generation is high levle (high leve1) during greater than zero accurate position (zero leve1) shown in Fig. 9 B, during less than zero accurate position is pulse (pulse) signal of low level (10W leve1), detect the rising edge and the drop edge of institute's production burst (pulse) signal again, generate two edges signal 18 shown in Fig. 9 C.This two edges signal is supplied with counting (counter) circuit 502, is latched (latch) circuit 503 and digital LPF circuit 504.
Counting (counter) circuit 502 is removed (clear), is counted (count) clock pulse (clock) from clock pulse (clock) terminal feeding by the two edges signal of two edges detecting circuit 501.The variation of count value shown in Fig. 9 D of counting (count) circuit 502 supplied with and latched (latch) circuit 503.
Latch (latch) circuit 503 and supply with count value and two edges detecting circuit 501 supply two edges signals by counting circuit 501, preface (timing) latchs (latch) count value Q in the edge output of two edges signal
1～Q
nThe count value that latchs is supplied with digital LPF circuit 504.
(latch) circuit 503 is supplied with count value to numeral LPF504 and two edges detecting circuit 501 is supplied with the two edges signal by latching.LPF504 is according to latching the count value that (latch) circuit 503 is supplied with for numeral, carry out low pass (low pass) by numeral (digital) processing and filter (filter) processing, remove denoising (noise) composition, FM signal through the digital filtering processing, by terminal 507 outputs, carry out demodulation process, extract out in the information of rocking (wobble) signal overlap.
But actual FM modulating signal is to have noise (noise) overlapping.
Figure 10～Figure 12 A, B, C represent common known signal treatment circuit action specification figure.
Actual FM modulating signal as shown in figure 10 at zero accurate position (zero level) near side (ns), has plural number to report to the leadship after accomplishing a task by the influence and the zero accurate position (a zero level) of noise (noise).Therefore, during commutation pulse (pulse) signal, shown in Figure 11 A, before and after pulse (pulse) signal unwanted pulse (pulse) can take place in the same old way.Shown in 11B, detect plural number time rising edge and drop edge.Thus, shown in Figure 11 B between the edge,, shown in Figure 11 D,, export most subtotal numerical value in noise (noise) part if during clock pulse (clock) shown in counting (count) Figure 11 C.Therefore can't obtain correct pulse (pulse) signal.
At this, motion can be got rid of noise between the emergence period, can detect the method for pulse (pulse) signal edge.Get rid of noise (noise) between the emergence period, detect the method for pulse (pulse) signal edge, be illustrated together with Figure 12 A, B, C.
Figure 12 represents that known noise (noise) removes the key diagram of method.Figure 12 A is input pulse (pulse) signal, and Figure 12 B is except that pulse (pulse) signal behind the denoising, and Figure 12 C represents the two edges signal except that pulse (pulse) signal behind the denoising (noise).
Known when continuing certain time interval T 3 for pulse (pulse) signal, begin to detect edge (edge).Input pulse (pulse) is though signal has rising shown in Figure 12 A at time tl, and the relation through descending before the certain time interval T 3 can not detect edge (edge).When time t2, t7, shown in Figure 12 A, input pulse (pulse) signal rises, and continues the relation of high levle (high level) state of certain time interval T more than 3, can detect the edge on the one hand.
And at time t4, shown in Figure 12 A, input pulse (pulse) is though signal has decline, and before process certain time interval T 3, the relation that rises can not detect the edge.When time t5, t9, shown in Figure 12 A, input pulse (pulse) signal descends, and continues low level (low level) state relation of certain time interval T more than 3, can detect the edge on the one hand.
As above, shown in Figure 12 C, can detect two edges signal except that denoising (noise) composition.
As mentioned above, actual pulse (pulse) signal has noise (noise) to exist, and noise (noise) pulse (pulse) signal takes place to rise and descend thus.Thus, when the edge that detects this kind pulse (pulse) signal detected, the edge can comprise the pulse (pulse) that contains noise (noise).Therefore, counting is during (count) marginating compartment so in the same old way, and noise (noise) composition also is contained in count value output, and the problem points that can't correctly carry out signal Processing etc. is arranged.
And, shown in Figure 12 A, B, C, when continuing same surely (level) of certain time interval T 3 or more, to detect the method at edge, shown in Figure 12 A, B, C, noise (noise) is arranged when existing, can take place to be long delay time Tx, Ty than certain time interval T 3, the delay time of certain time interval T 3 only takes place in noise (noise) when not existing.And shown in Figure 12 A, B, C, as delay time Tx, Ty, because of noise (noise) the number delay time also different relation, the cyclical swing of signal has the problem points that can't correctly carry out signal Processing.
Summary of the invention
The present invention is point in view of the above problems, a kind of signal processing circuit and signal processing method are provided, during the high levle (level) of input pulse (pulse) signal or during the low level, can remove the influence of denoising (noise) composition, can correctly detect input pulse (pulse) signal is purpose.
The invention is characterized in, signal processing circuit is output, remove output pulse (pulse) signal of denoising (noise) composition from input pulse (pulse) signal, establish accumulated time determination part and pulse (pulse) signal efferent in this signal processing circuit, the accumulated time determination part, measure in input pulse (pulse) signal, the accumulated time of one side's polarity, pulse (pulse) signal efferent is when the accumulated time that the accumulated time determination part is measured reaches Preset Time, make the polarity of output pulse (pulse) signal anti-phase, the polarity of the output pulse (pulse) of being exported from pulse (pulse) signal efferent is the polarity chron of other party, remove the accumulated time of (clear) accumulated time determination part, forbid measuring accumulated time simultaneously.
According to the present invention, only during the high levle (highlevel) of the noise (noise) of input pulse signal or only during low level (low level), the relation that accumulation decision is risen can not be subjected to the influence of noise (noise) can detect the edge of input pulse (pulse) signal.
The present invention is by pulse (pulse) signal efferent, and to the anti-phase Preset Time of polarity of exporting pulse (pulse) signal, this Preset Time is according to the delay time of output pulse (pulse) signal to input pulse (pulse) signal, and making becomes the different feature that is.
According to the present invention, according to different by the time that makes the mensuration accumulated time, setting that can be comfortable is to the delay time of the output pulse signal of input pulse signal.
The present invention has other party accumulated time determination part and other party pulse signal efferent, other party accumulated time determination part is in the input pulse signal, measure the accumulated time of other party polarity, other party pulse signal efferent is at other party accumulated time determination part, when the accumulated time of being measured reaches Preset Time, make the polarity of output pulse signal anti-phase.By the pulse signal efferent, make the anti-phase Preset Time of the polarity of output pulse signal with by other party pulse signal efferent, make the anti-phase Preset Time of polarity of output pulse signal, make the different feature that is.
According to the present invention, with the accumulated time of the polarity of each polarity detection input pulse signal, according to different by the accumulated time that makes each polarity, can the comfortable duty ratio (duty factor) of setting output pulse signal.
The present invention supplies with input pulse (pulse) signal and clock pulse (clock), accurate position (level) output clock pulse (clock) according to input pulse (pulse) signal, simultaneously remove (clear) output count value according to output pulse (pulse) signal, one side is counted clock pulse (clock), according to the value of collecting, make output pulse (pulse) home position signal (set) or reset (reset).
During the present invention is high levle (high level) at output pulse signal, the clock pulse (clock) that counting is supplied with during the low level (low level) of input pulse signal, simultaneously, during the low level (low level) of output pulse signal, the clock pulse (clock) that counting is supplied with during the high levle (highlevel) of input pulse signal, count value during the low level of input pulse signal and the count value during the high levle, reach during fixed count value, make and carry out set (set) or reset (reset).And, by output pulse signal delay signal latch (latch) count value between regularly, signal removal (clear) count value that the signal that latchs (latch) count value is delayed.
Description of drawings
Fig. 1 is the block scheme of the signal processing circuit of one embodiment of the invention.
Fig. 2 A～M is the movement oscillogram of the signal processing circuit of one embodiment of the invention.
Fig. 3 is the square frame pie graph that noise (noise) is removed the variation of portion.
Fig. 4 A～G is that noise (noise) is removed the movement oscillogram of the variation of portion.
Fig. 5 is the square frame pie graph that noise (noise) is removed other variation of portion.
Fig. 6 is the square frame pie graph of optical disc apparatus.
Fig. 7 is the pie graph of discs.
Fig. 8 is the square frame pie graph of an example of common known signal treatment circuit.
Fig. 9 A-D is the action specification figure of common known signal treatment circuit.
Figure 10 is the action specification figure of common known signal treatment circuit.
Figure 11 A-D is the action specification figure of common known signal treatment circuit.
Figure 12 A-C is the action specification figure of common known signal treatment circuit.
Description of reference numerals:
1: signal processing circuit
11,12:AND: grid (gate)
13,14,15: counter (counter)
16:RS flip-flop (nip-flop)
17,18:D flip-flop (nip-flop)
19: negative circuit
20,21:EX-OR grid (gate)
22: latch (1atch) circuit
23: numeral (digita1) LPF
Embodiment
Embodiments of the invention are illustrated together with drawing.
Fig. 1 is the block scheme of the signal processing circuit of one embodiment of the invention, represents the movement oscillogram of the signal processing circuit of one embodiment of the invention at Fig. 2.
The signal processing circuit 1 of present embodiment is located in shown in Figure 6 rocking (wobble) signal processing part 48.Signal processing circuit 1 comprises AND grid (gate) 11,12, counter (counter) 13,14,15, RS flip-flop (nip-flop) 16, D flip-flop (nip-flop) 17,18, negative circuit 19, EX-OR grid (gate) 20,21, latchs (1atch) circuit 22,23 formations of numeral (digita1) LPF (LOWPASS FILTER).
The action of signal processing circuit 1 is illustrated together with Fig. 2 A-M.
Fig. 2 A-M represents the movement oscillogram of the signal processing circuit of one embodiment of the invention.Fig. 2 A represents to rock (wobble) signal, Fig. 2 B represents clock pulse (clock), Fig. 2 C represents the output of AND grid (gate) 11, Fig. 2 D represents the output of negative circuit 19, Fig. 2 E represents the output of AND grid (gate) 12, Fig. 2 F represents the output of counter (counter) 13, Fig. 2 G represents the output of counter (counter) 14, Fig. 2 H represents the noninverting output of RS flip-flop (nip-flop) 16, Fig. 2 I represents the anti-phase output of RS flip-flop (nip-flop) 16, Fig. 2 J represents the output of D flip-flop (nip-flop) 17, Fig. 2 K represents the output of D flip-flop (flip-flop) 18, Fig. 2 L represents the output of EX-OR grid (gate) 20, and Fig. 2 M represents the output of EX-OR grid (gate) 21.
Rocking (wobble) signal shown in Fig. 2 A is FM pulse (pulse) signal, from terminal T
1Supply with AND grid (gate) 11 and negative circuit 19.And clock pulse shown in Fig. 2 B (clock) is from terminal T
2Supply with AND grid (gate) 11 and AND grid (gate) 12.
AND grid (gate) 11 is shown in Fig. 2 C, from terminal T
1Rock (wobble) signal and be high levle (high leve1) time, make clock pulse (clock) from terminal T
2By, clock pulse (clock) input terminal of supply counter (counter) 13.The clock pulse (clock) that counter (counter) 13 countings are supplied with from AND grid (gate) 1l, the value Q of i position in its count value
i, set (set) terminal of supply RS flip-flop (flip-flop) 16.And, be that the occasion of " 3 " is that example describes with " i " at Fig. 2.
And negative circuit 19 makes from terminal T shown in Fig. 2 D
1(wobble) signal inversion of rocking supply with AND grid (gate) 12.AND grid (gate) 12 when anti-phase rocking (wobble) signal of negative circuit 19 is high levle (high leve1), makes from terminal T shown in Fig. 2 E
2Clock pulse (clock) pass through, supply with clock pulse (clock) input terminal of counter (counter) 14.
Counter (counter) 14 countings are from the clock pulse (clock) of AND grid (gate) 12, the value Q of i position in its count value
iSupply with replacement (reset) terminal of RS flip-flop (nip-flop) 16.RS flip-flop (nip-flop) 16 shown in Fig. 2 H, Fig. 2 I, the count value Q of the i position of counter (counter) 13
iDuring rising, make noninverting output Q set (set), though high levle (highlevel), the count value Q of the i position of counter (counter) 14
iDuring rising, noninverting output Q is reset (reset), that is, making becomes low level (10W level).
The noninverting output Q of RS flip-flop (nip-flop) 16 supplies with removing (clear) terminal of counter (counter) 13, simultaneously, supplies with D flip-flop (nip-flop) 17 and EX-OR grid (gate) 20.Again, the anti-phase output of RS flip-flop (flip-flop) 16/Q supplies with removing (clear) terminal of counter (counter) 14.
Counter (counter) the 13rd becomes removing (clear) state when the noninverting output Q of RS flip-flop (flip-flop) 16 is high levle (hi spider level).Counter (counter) the 14th becomes removing (clear) state when the anti-phase output/Q of RS flip-flop (nip-flop) 16 is high levle (high level).
To D flip-flop (flip-flop) 17, the noninverting output Q of RS flip-flop (flip-flop) 16 supplies with data terminal, from terminal T
2Clock pulse (clock) supply with the clock pulse terminal.The accurate position of the data terminal when D flip-flop (nip-flop) 17 keeps clock pulse (clock) to rise is exported.The output Q of D flip-flop (nip-flop) 17 supplies with the data terminal and the EX-OR grid (gate) 20 of D flip-flop (flip-flop) 18.EX-OR grid (gate) 20 outputs, the EX-OR logic of the noninverting output Q of RS flip-flop (nip-flop) 16 and the output of D flip-flop (nip-fop) 17.The output of EX-OR grid (gate) 20 is supplied with and is latched (1atch) circuit 22.Latch (1atch) circuit 22 and be output according to output latch (1atch) counter (counter) 15 of EX-OR grid (gate) 20.
And to D flip-flop (nip-flop) 18, its data terminal is supplied with the output Q of D flip-flop (nip-flop) 17, and its clock pulse (clock) terminal is from terminal T
2Supply with clock pulse (clock).The accurate position (1evel) of the data terminal when D flip-flop (nip-flop) 18 keeps clock pulse (clock) to rise is exported.The output Q of D flip-flop (nip-flop) 18 supplies with EX-OR grid (gate) 21.The EX-OR logic of the output of EX-OR grid (gate) 21 output D flip-flops (nip-flop) 17 and the output of D flip-flop (flip-flop) 18.Removing (clear) terminal of counter (counter) 15 is supplied with in the output of EX-OR grid (gate) 21.Counter (counter) 15 is removed (clear) count value according to the output of EX-OR grid (gate) 21.
Counter (counter) 15 countings are from terminal T
2Clock pulse (clock), count value is supplied with is latched (latch) circuit 22.Latch (latch) circuit 22 and when the output of EX-OR grid (gate) 20 is risen, latch the count value of (latch) counter (counter) 15.
Numeral (digital) LPF23 output is from the signal of address that variation writes (address) information of numeral (digital) value that latchs (latch) circuit 22 etc., for example two-phase (bi-phase) signal.
When the time of Fig. 2 t1 and t9, counter (counter) 14 becomes removing (clear) state because of the anti-phase output/Q of RS flip-flop (flip-flop) 16 is the relation of high levle (high level).And counter (counter) 13 is the relation of low level (low level) because of the noninverting output Q of RS flip-flop (flip-flop) 16, and counting is from the clock pulse (clock) of AND grid (gate) 11.
The output Qi of counter (counter) 13 is set in the 3rd value Q
3, from counting (count), when being 8 countings (count) to the clock pulse (clock) from AND grid (gate) 11, when time t2 and t10, anti-phase by low level (low level) is high levle (high level).
When time t2, t10, the output Q of counter (count) 13
iAnti-phase, when becoming high levle (highlevel), the noninverting high levle (high level) that is output as of RS flip-flop (flip-flop) 16, anti-phase output/Q is low level (low level).When the anti-phase output Q of RS flip-flop (flip-flop) 16 was low level (low level), removing (clear) state of counter (counter) 14 was removed, and counter (counter) 14 begins the clock pulse (clock) of counting from AND grid (gate) 12.And at this moment, counter (counter) 13 becomes removing (clear) state because of the noninverting output Q of RS flip-flop (flip-flop) 16 is the relation of high levle (high level).
And, when time t2, t10, when RS flip-flop (flip-flop) 16 is output as high levle (highlevel), the output of D flip-flop (flip-flop) 17 is retained to the relation of the clock pulse (clock) of next with low level (low level), the input of EX-OR grid (gate) 20 becomes high levle (highlevel) and low level (low level), and its output is anti-phase by low level (low level) to be high levle (highlevel).Because of going out by low level (low level) is anti-phase, the wheel of EX-OR grid (gate) 20 is high levle (high level), latch (latch) circuit 22 in the rising edge of the output of EX-OR grid 20 (upedge), latch the output of (latch) counter (counter) 15.
Secondly, when time t3, t11, D flip-flop (flip-flop) 17 is output as high levle (highlevel), and one of EX-OR grid (gate) 21 is input as high levle (highlevel).At this moment, the output of D flip-flop (flip-flop) 18 becomes the relation of low level (lowlevel) between the clock pulse (clock) of supplying with next, and the other party of EX-OR grid 21 is input as low level (low level).Therefore, the output of EX-OR grid (gate) 21 is anti-phase for high levle (highlevel) by low level (low level).Counter (counter) the 15th when becoming high levle (high level) according to the output of EX-OR grid 21 by low level (low level), is removed (clear) count value.So, in the count value of counter (counter) 15.By latching (latch) circuit 22, latched (latch) after, the beginning is removed the count value of (clear) counter (counter) 15.
At time t4, t12, when clock pulse (clock) rose, it was high levle (high level) that D flip-flop (flip-flop) 18 latchs (latch) noninverting output Q.When the noninverting output Q of D flip-flop (flip-flop) 18 is high levle (highlevel), input because of EX-OR grid (gate) 21, be the relation of high levle (high level) simultaneously, EX-OR grid (age) 21 returns low level (low level), and the removing (clear) of counter (counter) 15 becomes may state.
Secondly, time t5, t13, when rocking (wobble) signal and being low level (low level), counter (counter) 14 is the relation of low level (lowlevel) because of the anti-phase output/Q of RS flip-flop (flip-flop) 16, and counting (count) is from the clock pulse (clock) of AND grid (gate) 12.At time t6, t14, the 3rd place value Q of the count value of counter (counter) 14
3During rising, the output of RS flip-flop (flip-flop) 16 is reset (reset).When RS flip-flop (flip-flop) 16 is reset (reset), the output of EX-OR grid (gate) 20 becomes high levle (highlevel) by low level (low level), latchs the count value that (latch) circuit 22 latchs (latch) counter (counter) 15 at that time.
At time t7, t15, when the clock pulse (clock) of D flip-flop (flip-flop) 17 rose, D flip-flop (flip-flop) 17 latched the output Q of (latch) RS flip-flop (flip-flop) 16, becomes low level (low level).The output of D flip-flop (flip-flop) 17, when becoming low level (low level), the output of EX-OR grid (gate) 20 becomes low level (low level).And when the output of D flip-flop (flip-flop) 17 became low level (low level), the output of EX-OR grid (gate) 21 became the relation of low level (low level), and counter (counter) 15 is eliminated.At time t8, when supplying with clock pulse (clock) rising of D flip-flop (flip-flop) 18, D flip-flop (flip-flop) 18 latchs the output of (latch) D flip-flop (flip-flop) 17, becomes low level (lowlevel).
As mentioned above, after detecting the rising or decline of rocking (wobble) signal, during high levle (highlevel) or low level (low level), count up to the numerical value of devising a stratagem, detect next the decline or the rising of rocking (wobble) signal, during low level (low level) or high levle (high level), count up to the numerical value of devising a stratagem, in view of the above, not need comprise noise (noise) during count.Therefore, only the relation of counting during high levle (high level) or low level (low level) can alleviate The noise, can correctly detect during the high levle (highlevel) that rocks (wobble) signal and during the low level (low level).
And, at present embodiment, be that example is illustrated to be useful in optical disc apparatus, be not to be limited to this, main points applicable to the high levle (highlevel) that detects pulse (pulse) signal during and the occasion during the low level (low level).
And the noise of present embodiment (noise) is removed portion according to by the mensuration accumulated time of counting clock pulse (clock) with numeral (digital), and also the charging that can be waited by capacitor (condenser) is to simulate the mensuration accumulated time of (analog).
Fig. 3 represents that noise removes the square frame pie graph of the variation of portion.
Among the figure with the same component part of Fig. 1, attached same label, its explanation is omitted.
The noise of present embodiment (noise) is removed portion 200 and is comprised constant current source 211,212, analog switch (analog switch) circuit 213～216, capacitor (condenser) 220,221, buffer amplifier (buffer amplifier) 224,225, comparer (comparator) 226,227, RS flip-flop (flip-flop) 234, reference voltage source 236,237 formations of phase inverter (inverter).
The action that noise (noise) is removed portion 200 is illustrated together with Fig. 4.
Fig. 4 A～G represents that the noise (noise) of one embodiment of the invention removes the movement oscillogram of the variation of portion.What Fig. 4 A was expressed as input pulse (pulse) signal rocks (wobble) signal, Fig. 4 B represents the variation of the charging voltage of capacitor (condenser) 200, Fig. 4 C represents the output of negative circuit 237, Fig. 4 D represents the variation of the charging voltage of capacitor (condenser) 221, Fig. 4 E represents the output of comparer (comparator) 227, Fig. 4 F represents the output of comparer (comparator) 227, and Fig. 4 G represents the output of RS flip-flop (flip-flop) 234.
Rocking (wobble) signal shown in Fig. 4 A is FM pulse (pulse) signal, from terminal T
1Supply with analog switch (analog switch) circuit 213 and negative circuit 237.Negative circuit 237 makes and rocks (wobble) signal inversion shown in Fig. 4 C, supplies with analog switch (analog switch) circuit 214, and analog switch (analog switch) circuit 213 is from terminal T
1Pulse (pulse) signal when being positive polarity, become conducting (ON), during negative polarity, become disconnection (OFF).
When time t0, the output of comparer (comparator) 227 rose to high levle (highlevel) by low level (low level), RS flip-flop (flip-flop) 234 was set (set).During RS flip-flop (flip-flop) 234 set, making noninverting output Q is high levle (highlevel), and anti-phase output/Q is low level (low level).When the noninverting output Q of RS flip-flop (flip-flop) 234 was high levle (highlevel), analog switch (analog switch) circuit 215 became disconnection (OFF).According to becoming disconnection (OFF), capacitor (condenser) 220 can be charged by pulse (pulse) signal by analog switch (analog switch) circuit 215.
At this moment, the anti-phase output/Q of RS flip-flop (flip-flop) 234 is low level (low level).When the anti-phase output/Q of RS flip-flop (flip-flop) 234 was low level (low level), analog switch (analog switch) circuit 216 became conducting (ON).When analog switch (analog switch) circuit 216 becomes conducting (ON), capacitor (condenser) 221 discharges.During capacitor (condenser) 221 discharges, the voltage ratio of non-inverting input of comparer (comparator) 227 is little relation from the reference voltage of reference power supply 236, and the output of comparer (comparator) 227 becomes low level (low level).
Capacitor (condenser) 220 be at t1～t2, input pulse (pulse) signal be high levle (highlevel) during, charged by constant current source 211.At time t2, when the charging voltage of capacitor (condenser) 220 was bigger than decide voltage, the voltage ratio of the noninverting terminal of comparer (comparator) 226 was big from the reference voltage of reference power supply 236.The output of comparer (comparator) 226 becomes high levle (highlevel) by low level (low level) thus.
The output of comparer (comparator) 226, when becoming high levle (high level) by low level (low level), RS flip-flop (flip-flop) 234 is reset (reset).Flip-flop (flip-flop) 234, when resetting (reset), noninverting output Q becomes low level (low level), and anti-phase output/Q becomes high levle (highlevel).
When the anti-phase output/Q of RS flip-flop (flip-flop) 234 was high levle (highlevel), analog switch (analog switch) circuit 216 became disconnection (OFF).Analog switch (analog switch) circuit 216, when disconnecting (OFF), capacitor (condenser) 221 can be by pulse (pulse) signal of negative circuit 237, and making becomes charging possibility state.
On the one hand, when the noninverting output Q of RS flip-flop (flip-flop) 234 was low level (lowlevel), analog switch (analog switch) circuit 215 became conducting (ON).According to being conducting (ON), make capacitor (condenser) 220 discharges by analog switch (analog switch) circuit 215.Because of the discharge of capacitor (condenser) 220, the voltage ratio of non-inverting input of comparer (comparator) 226 is little relation from the reference voltage of reference power supply 236, and output becomes low level (low level).
As previously discussed, rock (wobble) signal from low level (low level0 become high levle (high level) during, make capacitor (condenser) 220 chargings, during becoming low level (low level) from high levle (high level), make capacitor (condenser) 221 chargings, according to make the anti-phase sequential (timing) of output, the influence that can alleviate noise (noise) by decision.To rocking the becoming the sequential (timing) of high levle (highlevel) and become the sequential (timing) of low level (low level) of (wobble) signal, can correctly be determined from high levle (high level) from low level (low level).
And, at this variation constant current source 211,212, phase inverter (inverter) 237, analog switch (analog switch) circuit 213,214,215,216, with the sequential that discharges and recharges (timing) of control capacitor (condenser) 220,221, circuit also can be simplified.
Fig. 5 represents that noise removes other routine square frame pie graph of circuit.
It is by constant current source 301, analog switch (analogswitch) circuit 302 that the noise of this variation is removed circuit 300, in addition the sequential (timing) of the charging of control capacitor (condenser) 220,221.
Deciding sources 301 is to produce constant-current charge capacitor (condenser) 220,221.Constant current source 301 is supplied with analog switch (analog switch) circuit 302.Analog switch (analog switch) circuit 302, there is contact to switch, when input pulse (pulse) signal is high levle (high level), make and decide current supply capacitor (condenser) 220 from constant current source 301, when input pulse (pulse) signal is low level (low level), makes and decide current supply capacitor (condenser) 221 from constant current source 301.
As above, capacitor (condenser) 220, can be during the high levle (highlevel) of input pulse (pulse) signal to capacitor (condenser) 220 chargings, during the low level (low level) of input pulse (pulse) signal, can carry out the action same to capacitor (condenser) 221 chargings with Fig. 4.
And, be illustrated with the example that is useful in optical disc apparatus at present embodiment, be not to be limited to this, main points are appropriate to detect during the high levle (highlevel) of pulse (pulse) signal and the situation during the low level (low level).And, all effective to the signal Processing of the cyclical signal of FM modulation or FSK modulation etc., not only at optical disc apparatus, also can be applicable to the vast field of communication system etc.
According to the present invention, because of only during the high levle (high level) of the noise (noise) of input pulse (pulse) signal or only during low level (low level), the relation that the accumulation decision is risen, have and be not subjected to noise (noise) influence, with the speciality at the edge (edge) that detects input pulse (pulse) signal.
And,,, can comfortablely set the delay time of output pulse (pulse) signal to input pulse (pulse) signal according to by making the time of measuring accumulated time different according to the present invention.
According to the present invention,,, has the speciality of the duty ratio (duty factor) that can comfortablely set output pulse (pulse) signal according to different by the accumulated time that makes each polarity with the accumulated time of the polarity of each polarity detection input pulse (pulse) signal.
According to the present invention, have and be not subjected to noise (noise) shadow to, the speciality that can detect during the high levle (high level) of input pulse (pulse) signal and the low level (low level) etc.
According to the present invention, input pulse (pulse) signal comprise vibration (chattering) during, only during the positive polarity of input pulse (pulse) signal or only during negative polarity, charge, according to by being that sampling keeps (sample hold) with the charging voltage, exported, had the influence that is not subjected to Dan moving (chattering), can be detected during the positive polarity of input pulse (pulse) signal or the speciality during the negative polarity etc.
Claims (2)
1. a signal processing circuit is removed noise contribution from the input pulse signal, makes output pulse signal output, it is characterized in that: comprising:
One first charging device when this input pulse signal is positive polarity, charges;
One second charging device when this input pulse signal is negative polarity, charges;
One output unit when reaching the default accurate position of benchmark in the accurate position of the charging of this first charging device and this second charging device, makes the polarity of this output pulse signal anti-phase; And
One electric discharge device when this output pulse signal of exporting at this output unit is positive polarity, makes this second charging device discharge, when this output pulse signal is negative polarity, makes this first charging device discharge.
2. a signal processing method from the input pulse signal, is removed noise contribution, makes output pulse signal output, it is characterized in that: comprising:
Carry out the charging of first charging device during for positive polarity at this input pulse signal;
Carry out the charging of second charging device during for negative polarity at this input pulse signal;
When reaching the default accurate position of benchmark in the accurate position of the charging of this first charging device and this second charging device, make the polarity of this output pulse signal anti-phase; And
When this output pulse signal is positive polarity, make this second charging device discharge, when this output pulse signal is negative polarity, make this first charging device discharge.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001044222 | 2001-02-20 | ||
| JP2001-044222 | 2001-02-20 | ||
| JP2001044222 | 2001-02-20 | ||
| JP2001272571 | 2001-09-07 | ||
| JP2001272571A JP3724398B2 (en) | 2001-02-20 | 2001-09-07 | Signal processing circuit and signal processing method |
| JP2001-272571 | 2001-09-07 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021046360A Division CN100370541C (en) | 2001-02-20 | 2002-02-10 | Signal process circuit and method thereof |
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| Publication Number | Publication Date |
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| CN101131848A CN101131848A (en) | 2008-02-27 |
| CN101131848B true CN101131848B (en) | 2011-07-06 |
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| CN2007101456986A Expired - Fee Related CN101127228B (en) | 2001-02-20 | 2002-02-10 | Signal processing circuit and signal processing method |
| CN2007101456967A Expired - Fee Related CN101131848B (en) | 2001-02-20 | 2002-02-10 | Circuit and method for processing signal |
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| CN2007101456986A Expired - Fee Related CN101127228B (en) | 2001-02-20 | 2002-02-10 | Signal processing circuit and signal processing method |
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| PL2786488T3 (en) * | 2011-11-30 | 2019-06-28 | Abb Schweiz Ag | An electronic system for an electrical apparatus and related method |
| CN107809225B (en) * | 2017-11-16 | 2020-12-01 | 湖南工业大学 | Narrow interference pulse filtering method |
| CN107947786A (en) * | 2017-11-16 | 2018-04-20 | 湖南工业大学 | Tipping-bucket rain-gauge counts method for generating pulse |
| CN112217497B (en) * | 2017-11-16 | 2023-10-10 | 深圳市盛装科技有限公司 | Continuous interference pulse filter circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159586A (en) * | 1995-12-21 | 1997-09-17 | 株式会社艾德温特斯特 | Method of measuring delay time and random pulse train generating circuit used in such method |
| US5874839A (en) * | 1996-02-05 | 1999-02-23 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Timer apparatus |
| US6337649B1 (en) * | 2000-03-28 | 2002-01-08 | Litton Systems, Inc. | Comparator digital noise filter |
-
2002
- 2002-02-10 CN CN2007101456986A patent/CN101127228B/en not_active Expired - Fee Related
- 2002-02-10 CN CN2007101456967A patent/CN101131848B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159586A (en) * | 1995-12-21 | 1997-09-17 | 株式会社艾德温特斯特 | Method of measuring delay time and random pulse train generating circuit used in such method |
| US5874839A (en) * | 1996-02-05 | 1999-02-23 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Timer apparatus |
| US6337649B1 (en) * | 2000-03-28 | 2002-01-08 | Litton Systems, Inc. | Comparator digital noise filter |
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| Publication number | Publication date |
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| CN101131848A (en) | 2008-02-27 |
| CN101127228B (en) | 2011-04-13 |
| CN101127228A (en) | 2008-02-20 |
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