CN101131713B - System for concurrent development of ASIC and programmable logic device, and development method - Google Patents

Abstract

An integrated circuit development method for generating a net list called a logical core composed of a net connecting ports of a block not depending on a device technology by using only connection information in the block port specification which is a result of circuit architecture study and a part of logical design document, selecting blocks as objects from the logical core, grouping the blocks, and using the grouped logical core data. A system for concurrent development of ASIC and FPGA is constituted by a fire wall for monitoring access from the Internet, a Web server for communicating with the Web client used by a user, an authentication server for performing user authentication, a user management server for managing a user, a logical synthesis server for executing an ASIC and FPGA development program, a mail server for distributing a mail to those associated with the project, a file server for storing design information, an application server for executing an ASIC implement design program, and a monitoring server for monitoring the ASCI and FPGA development state.

Description

ASIC and programmable logic device parallel development system and development approach

The application gets into the dividing an application of Chinese invention patent application (application number is 03808566.6, denomination of invention be " program memory medium of the development approach of integrated circuit and the development approach of having stored integrated circuit and ASIC and PLD be development system, development sequence and development approach simultaneously ") in China national stage in the PCT international application of on April 15th, 2003 application for same applicant.

Technical field

The present invention relates to the development approach and program memory medium and ASIC programmable logic device parallel development system, development sequence and the development approach of having stored the development approach of integrated circuit of integrated circuit.

The present invention relates to integrated circuit development approach, stored control device and the ASIC that the user utilizes from the networked computer aspect and parallel development system, development sequence and the development approach of PLD of program memory medium and logic synthetics of the development approach of integrated circuit.

In more detail; The PLD constructive method that relates to lsi development; Relate to such integrated circuit development approach and can seamless unoccupied place concurrent development ASIC and PLD; Can make and guarantee designing quality and shorten the development time and take into account, can reduce resource and the ASIC of cost and the parallel development system of PLD that consumes in the exploitation, development sequence and development approach simultaneously; That is to say; Only utilize as the link information of circuit structure result of study, generate a kind of net table that is called as logicor logic core that network constituted that links between port device technology, piece and the port, alternative piece from logicor logic core of not relying on as the port specification of the piece of the part of logical design file; Make up, use the logicor logic core data of combination to carry out the exploitation of integrated circuit.

Background technology

According to the program of integrated circuit, at first when the decision specification, cautiously do not have with omitting and scrutinize, design according to this specification then.Figure 11 is the process flow diagram of expression IC design program.At first, according to product specification, obtain the design sheets (g1) of ASIC (the so-called application-specific integrated circuit of special-purpose).Study circuit structure (g2) then.Moreover, carry out circuit design (g3) according to the circuit structure result of study.This circuit design is that the limit is carried out logic checking (g4) limit and designed.

Then,, circuit design carries out the logic synthetic (g5) of circuit after finishing.Behind the logic end of synthesis, synthetic result carries out programming and distribution (g6) according to logic.Accomplish circuit design in this stage.Circuit design is made this circuit (g7) after accomplishing, and utilization is processed circuit and carried out real machine evaluation (g8).In above process, relate to the synthetic part of logic that part of the present invention relates to the g5 step.

In lsi development, the research of the function that realizes specification as input, for realizing the research of the circuit structure that function is carried out is implemented by following flow process.Usually, the exploitation of integrated circuit is, according to product specification, the function that realizes product carefully screened, and studies realizing the circuit structure of having selected function, and IP (intellecture property) etc. is carried out macrovisual study.At this, so-called macroscopic view is meant not to be changed employable to the RAM that yet comprises IP, ROM etc. yet.

The circuit of research structure and the realization scale of IP are carried out according to a preliminary estimate, at this moment, if known in advance; Then calculate by the door number; Under the situation of not knowing the sect number, according to the number of signals of necessity with handle the required time and calculate the trigger circuit number, the realization scale is estimated.Here, go into signal (below be called port) number, be divided into one group to a plurality of functions, as a piece according to the output of the scale of estimating and each function.This grouping is carried out repertoire.

In logical design, according to above-mentioned functions and estimation scale, utilizing HDL means such as (hardware description languages) is that object carries out circuit design with the PLD, carries out functional evaluation onboard.After estimating end, when carrying out ASICization, design again and checking again.

After functional evaluation finishes; Utilize under the situation that ASICization reduces cost; Be not from being object when designing, just considering the design of ASIC with PLD (for example FPGA), but since inputoutput buffer, device with the difference between PLD such as macroscopic views such as hookup, storer and the ASIC; So; Is that object produces design again according to the Design of Programmable Logic Parts data with ASIC, because the dual command that designs the design data that occurs again, Design and Features is verified and made exploitation renewal and development cost increase again, and problem is come to the surface.

At this, the characteristic that ASIC has is that the construction cycle is long, but cost is low, and on the other hand, the characteristic that PLD (FPGA) has is that the construction cycle is short, but cost is high.

The scheme that The present invention be directed to these problems and propose, its purpose is: the circuit structure that the logical design in the exploitation of extensive ASIC, logic are synthetic, be suitable in (walk abreast) exploitation in the programming and distribution provides in studying:

The development approach of integrated circuit, the method for its application (as the spy open 2000-90142 number said) be, to generate interblock net table as the link information between port according to the port information that chip is carried out the piece that function cuts apart and the port information of chip; And

Development device is used for the steering logic synthetics, so that according to interblock net table and generate the block structure of the integrated circuit of developing with the development approach of said integrated circuit and the net between the piece according to the number of scale arbitrarily.

Provide a kind of and can realize the architecture sharing, can avoid designing again and the development approach of the integrated circuit of verifying again and the program memory medium of having stored the development approach of integrated circuit as far as possible.

And, in recent years, because the semiconductor microactuator refinement also can be developed the above ASIC of 10M door.But along with the multifunction of electronic equipment and complicated, carry out that specifications design, logical design and piece, logic are synthetic, the instrument design of programming and distribution design, regularly checking, take a long time, be difficult to guarantee designing quality simultaneously.Especially doing over again of ASIC exploitation not only makes the electronic equipment development time prolong, and causes cost to rise, and loses the chance of putting on market.

Therefore, need short, the easier PLD of change in design of construction cycle (TAT) in a large number, but the PLD cost is high; Be difficult to little difficultyization, so, mostly be at first to realize function with PLD; After prototype debug, make ASIC get into a large amount of production phases.

But the problem of existence is: even turn to prerequisite with ASIC, make model machine with PLD and verify, shorten performance history total also be difficult to make from PLD to the serial exploitation of ASIC.Especially if the problem that can not on time accomplish of the instrument design in ASIC when exploitation occur then possibly cause and do over again, and begins from the design again of PLD.Under the situation of entrusting outside cooperations such as little semiconductor enterprise, be difficult to guarantee that consignee's human resources and its expense are very high.

Moreover, because the structure between PLD and the ASIC device is different, when needing the special ASIC of being to design again; Not only the debugging with PLD loses meaning, and the construction cycle increases; Cost also rises, and also can lose the good opportunity of putting on market.

And, cause the long and countermeasure taked of construction cycle to extensiveization of ASIC, it is said to open the 2000-90142 communique like the spy, carries out circuit structure research, logical design simultaneously. checking, instrument design.But, because the function of electronic equipment is complicated very fast with market development, so specifications design, logical design, proving period are long, are difficult to the shortening performance history.Under the situation of developing at the same time, need have the human resources and the developing instrument of ASIC development knowledge,, also need strengthen the training of complicated developing instrument along with the progress of semiconductor technology.

Summary of the invention

So; The object of the present invention is to provide a kind of can seamless unoccupied place concurrent development ASIC and PLD; Can make and guarantee designing quality and shorten the development time and take into account; Can reduce simultaneously the human resources that consume in the exploitation and ASIC and the parallel development system of PLD, development sequence and the development approach of cost.

Fig. 1 is the process flow diagram of the principle of expression the inventive method.

The invention of the disclosed program memory medium of the 1st embodiment is characterized in that: have following steps:

Utilize the logicor logic core of a kind of ASIC that constitutes from link information by the port of piece and port; The method that selection has any piece of annexation to make up generates a kind of logicor logic core (1 step) of HDL form that link information constituted, that the logic synthetics can read of port and port of the piece by random scale, number;

Terminal information according to chip is made interim chip design pattern with the logic synthetics, and terminal (2 step) takes place on this pattern;

Inner at the pattern of processing, the pattern identical with 2 steps takes place as a unit (3 step).

The port (4 step) that connects the same title between pattern and the unit.

To the net between the port that has connected, insert the inputoutput buffer (5 step) that exists with ... device technology.

Logicor logic core and unit to making in 1 step are replaced, and launch the pattern stratum as top layer, generate net table (6 step).

In the invention of the disclosed program memory medium of the 1st embodiment, go into definition according to port name, scope, output, produce to output in the file and (write in the file) as the entity of the port specification of piece.This method of signal file is exported in utilization to the port establishment of being gone into to export definition by output; Whether the sub output port name of output place instance of checking the interior appointment of input port of certain piece is mistake; In output place Instance Name, have under the situation of the key words such as I/O of sealing terminal that are intended to interface unit; Be referred to as the name that has on the output port name of output place instance the package terminal name of device; Utilization judges that according to the definition of scope this terminal is one or the device of a plurality of (vectors); The definition of going into according to output judges that this terminal is input or the device of output and judges according to the definition of kind whether this terminal is the device of twocouese, and establishment outputs in the file as the entity of logicor logic core port specification.At this, so-called instance is meant circuit unit.

Going into definition at the port of piece by output imports under the situation of definition; Whether the group of output port name of checking output place Instance Name and the output place instance of this port is present in the device in the above-mentioned output signal file; Above-mentioned check result; The connection of the port between instance is judged as under the possible situation, generates the signal to connecting between instance, outputs in the file.Comprise the inspection of full instance, when processing finishes, read net between entity and the instance of above-mentioned logicor logic core, the formation logic magnetic core is input in the file.

If check result is no problem; Then be to have write down recording medium a kind of like this program, that computing machine can read; That is to say by the output of piece go between specification and instance be connected net and instance and device package terminal, be that the net that is connected between outside terminal constitutes, making computer-executed method is to export the file of the HDL (hardware description language) that does not have the logical design part fully (below be called " logicor logic core ").

So if adopt a kind of program memory medium, wherein program stored can make computing machine carry out the method for the logicor logic core of the invention that generates the 1st embodiment; Then in lsi development, its effect is to guarantee to design as RTL the quality of the port of the piece of importing in advance, in addition; A lot of in functional block; In the exploitation of the large scale integrated circuit that design resource is also a lot, also can confirm the connection of interblock, so can guarantee the certain assembly unit success of chip in advance.

The invention of the development approach of the disclosed integrated circuit of the 1st embodiment under the situation that ASIC and PLD are developed simultaneously, is characterized in that having following steps:

Utilize a kind of suites of measure; Promptly from the so-called logicor logic core of the ASIC that link information constituted of the port of piece and port; Selecting any piece with annexation makes up; Generate port and the link information of port and the logicor logic core (1 step) that is constituted of the piece of random scale, number like this

Utilize the logic synthetics to work out the layout of interim chip (2 step) according to the terminal information of chip.

In this layout, be utilized in the title that has in the terminal information of said chip terminal (3 step) takes place.

Layout same as described above takes place as unit (4 step) in portion within it.

Connect by the pattern of 2 steps making and the port of the same title between the unit (5 step).

This connection net is inserted the inputoutput buffer (S6 step) that exists with ... device technology according to the terminal information of chip.

Replace to said units (7 step) to the logicor logic core that generates in 1 step.

Stratum to as the above-mentioned establishment layout of the top layer of this logicor logic core launches, and generates the net table (8 step) of the chip of PLD.

The invention of the development approach of the disclosed integrated circuit of the 1st embodiment is a kind of development approach of integrated circuit; It is characterized in that: in the concurrent development of ASIC and PLD; ASIC logicor logic core according to the invention of the 1st embodiment; The function of utilizing control device that program memory medium has been installed to come the steering logic synthetics; Wherein program stored can make computing machine carry out the net table generating method of the invention of the disclosed program memory medium of following the 1st embodiment, any piece with annexation is made up, as the logicor logic core taking-up of PLD; Insertion exists with ... the inputoutput buffer of PLD, generates the net table of the chip of PLD.

So; If the development approach of the integrated circuit of the invention of employing the 1st embodiment; Then from the ASIC logicor logic core, under the original state that connects between maintainance block, cut out the logicor logic core of PLD, so; If come PLD is verified, then in ASIC, can avoid repeated authentication at least with same structure with this logicor logic core.Therefore, can carry out the concurrent development of ASIC and PLD expeditiously.

And; When inserting inputoutput buffer; Terminal information according to chip generates interim logicor logic core; Utilization replaces to the means of the logicor logic core that is generated by piece, can cross-check by the port information of the chip of piece definition and the terminal information of chip, can guarantee the port specification of piece and the quality of chip terminal specification.

The invention of the disclosed program memory medium of the 1st embodiment; It is characterized in that: utilize a kind of suites of measure; Promptly from the so-called logicor logic core of the ASIC that link information constituted of the port of piece and port; Select any piece and make up, generate the net table that link information constituted (1 step) of port and port of the piece of random scale, number like this with annexation.

If adopt this structure, then can generate the net table that constitutes by the link information of the port of the piece of random scale, number and port.

The invention of the disclosed program memory medium of the 1st embodiment; It is characterized in that: utilize a kind of suites of measure; Promptly from the so-called logicor logic core of the ASIC that link information constituted of the port of piece and port; Select any piece and make up, generate the logicor logic core that link information constituted (1 step) of port and port of the piece of random scale, number like this with annexation

According to the interim chip design pattern that the terminal information of chip utilizes the logic synthetics to generate, on this layout, utilize the title that has in the terminal information of said chip that terminal (2 step) takes place,

Layout same as described above takes place as unit (3 step) in portion within it,

The port (4 step) that connects the same title between above-mentioned layout and unit,

This connection net is inserted the inputoutput buffer (5 step) that exists with ... device technology according to the terminal information of chip,

Replace to said units (6 step) to the logicor logic core that generates in 1 step,

The stratum at the layout of 2 steps establishment to as the top layer of this logicor logic core launches, and generates chip net table (7 step).

If adopt such structure, then can be according to generating chip net table by the port of the piece of random scale, number and the net table that link information constituted of port.

The invention of the development approach of the disclosed integrated circuit of the 1st embodiment; It is characterized in that: generate under the situation of chip net table by the port of the piece of random scale, number and the net table that link information constituted of port in basis; For the port name that makes top layer consistent with the port name of piece from the user name junction; Port name is made amendment, generate the net table that the link information by the port of piece and port constitutes.

The invention of the development approach of the disclosed integrated circuit of the 1st embodiment; In ASIC and programmable logic device parallel exploitation; ASIC logicor logic core according to the link information by the port of piece and port constitutes makes up any piece with annexation, uses the function of logic synthetics; Cut out under the situation of logicor logic core of PLD, the port title on the top of the logicor logic core that cuts out usually becomes the user name that is connected with this port.

A kind of control method of logic synthetics is characterized in that: the function to the logic synthetics is controlled, and net is followed the tracks of to logicor logic core inside from port, is modified to the port title of the piece of initial discovery.

So; If adopt the logic synthetics that makes of the invention of the 1st embodiment to come executive routine; Generate the program memory medium of the logicor logic core of PLD, the user name that then can prevent to be difficult to judge port function is that the debugging efficiencies such as logic checking under the situation of port title reduce.

As stated, according to the data of design document, the formation logic magnetic core; According to this logicor logic core under the state that keeps hierarchical structure and link information; For using, PLD regenerates logicor logic core, like this can the common circuit structure, and insert circuit data; Through circuit data that does not exist with ... device technology in the instance of functional verification and the net between instance; Under the situation of ASICization, can avoid verifying again, also can avoid designing again because of the difference between ASIC and the PLD.

And; In the present invention; Utilize a kind of suites of measure, promptly from the logicor logic core of the port of piece and the ASIC that link information constituted between the port, select any piece that constitutes ASIC and make up; Generate the port of the piece that constitutes by the piece of having selected and the logicor logic core of the PLD that link information constituted between the port like this, in the control device of the logic synthetics that this generation is controlled, have:

Control device; Port for the logicor logic core of the PLD of selecting by the deviser that piece constituted that generates by the logic synthetics; Pay the user name of port name by the logic synthetics; Explore the net be connected with this port, change the port title of the piece that becomes the PLD that formation connected;

Generating apparatus is used for utilizing the logic synthetics to generate to have the interim chip design pattern by the port of the terminal information appointment of chip according to the terminal information of chip;

Generating means is used at the above-mentioned interim chip design pattern of the inner generation of this layout as the unit;

Alternative; Be used between the port of the pattern of above-mentioned interim chip and the same title between the unit, connecting; To this net that has connected; Terminal information according to chip is inserted the inputoutput buffer that exists with ... device technology, and the logicor logic core and the unit of the PLD of being selected by the deviser that piece constituted of changing that the logic synthetics of above-mentioned title generates are replaced; And

The net table creating device, it launches to generate the chip net table of PLD through the top layer to this logicor logic core.

If adopt this structure, then can generate the chip net table of PLD,

And the present invention is the concurrent development method of ASIC and PLD, comprising following operation:

Net table generates operation, and it constitutes the functional block of ASIC according to link information between port, generates by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

The logic synthesis procedure is worked out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and is used the logic generated data with logic generated data and PLD;

The ROM data generate operation, are filled into by above-mentioned net table with the logic generated data about the PLD of the functional block of combinations thereof to generate in the net table that operation generated, and generation has been write down the real machine evaluation of PLD circuit and used the ROM data;

Butut (layout) generates operation, and the ASIC that utilization is worked out by above-mentioned logic synthesis procedure uses the logic generated data, and the Butut generation of ASIC and the real machine evaluation of timing checking and above-mentioned ROM data generation operation are carried out with the generation of ROM data simultaneously; And

Difference reflection operation is utilized the circuit data change of being undertaken by the data based real machine evaluation result of ROM of above-mentioned ROM data generation operation generation, in being reflected in the making of above-mentioned ASIC programming and distribution figure and regularly verifying.

And the present invention is the concurrent development program of ASIC and PLD, comprising following operation:

Net table generates operation, and it constitutes the functional block of ASIC according to link information between port, generates by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

The logic synthesis procedure is worked out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and is used the logic generated data with logic generated data and PLD;

The ROM data generate operation, are filled into by above-mentioned net table with the logic generated data about the PLD of the functional block of combinations thereof to generate in the net table that operation generates, and generation has been write down the real machine evaluation of PLD circuit and used the ROM data;

Butut generates operation, utilizes the ASIC that is worked out by above-mentioned logic synthesis procedure to use the logic generated data, and the Butut generation of ASIC and the timing checking and the real machine evaluation of above-mentioned ROM data generation operation are carried out with the generation of ROM data simultaneously; And

Difference reflection operation is utilized the circuit data change of being undertaken by the data based real machine evaluation result of ROM of above-mentioned ROM data generation operation generation, in being reflected in the making of above-mentioned ASIC programming and distribution figure and regularly verifying.

So concurrent development ASIC and PLD expeditiously can shorten construction cycle of ASIC.

If adopt the present invention, then constitute the functional block of ASIC according to link information between port, generate by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

The circuit data of determining according to the function that constitutes ASIC is worked out ASIC and is used the logic generated data with logic generated data and PLD;

PLD about the functional block of combinations thereof is filled into the logic generated data in the net table of generation, generates the real machine evaluation of having write down the PLD circuit and uses the ROM data;

Utilize the ASIC that has worked out to use the logic generated data, the planning chart drafting of ASIC is carried out with the generation of ROM data with regularly verifying with the real machine evaluation simultaneously;

Utilize to have generated the circuit data change that the data based real machine evaluation result of ROM that operation generates is carried out, be reflected in the making of above-mentioned ASIC planning chart and the checking regularly.

And the present invention is the concurrent development program of ASIC and PLD, comprising following operation:

Net table generates operation, and it constitutes the functional block of ASIC according to link information between port, generates by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

The logic synthesis procedure is worked out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and is used the logic generated data with logic generated data and PLD;

The ROM data generate operation, are filled into by above-mentioned net table with the logic generated data about the PLD of the functional block of combinations thereof to generate in the net table that operation generates, and generation has been write down the real machine evaluation of PLD circuit and used the ROM data; And

Butut generates operation, utilizes the ASIC that is worked out by above-mentioned logic synthesis procedure to use the logic generated data, and the Butut generation of ASIC and the timing checking and the real machine evaluation of above-mentioned ROM data generation operation are carried out with the generation of ROM data simultaneously;

So concurrent development ASIC and PLD expeditiously can shorten construction cycle of ASIC.

If adopt the present invention, then constitute the functional block of ASIC according to link information between port, generate by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

Work out ASIC according to the circuit data of the functional block that constitutes ASIC and use the logic generated data with logic generated data and PLD;

PLD about the functional block of combinations thereof is filled into the logic generated data in the net table of generation, generates the real machine evaluation of having write down the PLD circuit and uses the ROM data; And

Utilize the ASIC that has worked out to use the logic generated data, the planning chart drafting of ASIC is carried out with the generation of ROM data with regularly verifying with the real machine evaluation simultaneously;

So concurrent development ASIC and PLD expeditiously can shorten construction cycle of ASIC.

And the present invention is the ASIC that utilized by the user from the computing machine of networking and the parallel development system of PLD, it is characterized in that having:

ASIC logic synthesizer is used for according to above-mentioned customer requirements, and the logic of carrying out ASIC is synthetic;

The synthetic judgment means as a result of ASIC logic is used to judge the speed ability that whether has been satisfied above-mentioned customer requirements by the synthetic result of the ASIC logic of above-mentioned ASIC logic synthesizer establishment;

PLD logic synthesizer is used for the judged result of making according to the synthetic judgment means as a result of above-mentioned ASIC logic, and it is synthetic that PLD is carried out logic;

Logic is synthesized device displaying result, is used for demonstrating on computers above-mentioned ASIC logic synthesizer execution result and above-mentioned PLD logic synthesizer to the PLD logic synthetic execution result synthetic to the ASIC logic; And

Logic is synthesized notifying device, is used for sending to above-mentioned user through Email the notice of following content: by above-mentioned ASIC logic synthesizer to the synthetic execution beginning of ASIC logic and execution result and the execution beginning and the execution result that the PLD logic are synthesized by above-mentioned PLD logic synthesizer.

And the present invention is the ASIC that utilized by the user from the computing machine of networking and the concurrent development method of PLD, it is characterized in that having:

ASIC logic synthesis procedure is used for according to above-mentioned customer requirements, and the logic of carrying out ASIC is synthetic;

The synthetic judgment means as a result of ASIC logic is used to judge the speed ability that whether has been satisfied above-mentioned customer requirements by the synthetic result of the ASIC logic of above-mentioned ASIC logic synthesis procedure establishment;

PLD logic synthesis procedure is used for judging the judged result that operation is made according to the synthetic result of above-mentioned ASIC logic, PLD is carried out logic synthesize;

The synthetic result of logic shows operation, is used for demonstrating on computers above-mentioned ASIC logic synthesis procedure execution result and above-mentioned PLD logic synthesis procedure to the PLD logic synthetic execution result synthetic to the ASIC logic; And

The synthetic notice of logic operation is used for sending to above-mentioned user through Email the notice of following content: by above-mentioned ASIC logic synthesis procedure to the synthetic execution beginning of ASIC logic and execution result and the execution beginning and the execution result that the PLD logic are synthesized by above-mentioned PLD logic synthesis procedure.

If adopt the present invention, then according to above-mentioned customer requirements, the logic of carrying out ASIC is synthetic;

Judge the speed ability whether synthetic result of the ASIC logic of having worked out has satisfied above-mentioned customer requirements;

According to judged result, PLD is carried out logic synthesize;

Logic is synthesized device displaying result, is used for demonstrating on computers synthetic execution result of ASIC logic and the synthetic execution result of PLD logic;

Send the notice of following content to above-mentioned user through Email: execution beginning and execution result that execution beginning that the ASIC logic is synthetic and execution result and PLD logic are synthetic.

So; The user needn't be provided with the synthetic full-time staff of logic; It is synthetic at any time can both to carry out logic, can carry out as the full-time staff, can keep logic to synthesize the quality uniformity; Can come synthetic beginning of RL and result's notice through Email simultaneously, needn't make regular check on the synthetic situation of carrying out of logic with computing machine.

And the present invention is characterized in that also having:

The net table creating device, it is according to the functional block that constitutes above-mentioned ASIC by above-mentioned customer requirements, and generation is by the net table that is constituted of link information between the port of a plurality of functional blocks of above-mentioned user's appointment;

The ROM data generating device is used for being filled into the data of the synthetic object functionality piece that finishes of logic in the net table that is generated by above-mentioned net table creating device, generates the ROM data that write down the PLD circuit;

The ROM data generate device displaying result, are used on the aforementioned calculation machine, demonstrating the ROM data that generated by above-mentioned ROM data generating device and generate the result; And

The ROM data generate the result notification device, and it utilizes Email to generate the result to user notification by the ROM data that above-mentioned ROM data generating device generates.

If adopt the present invention, then according to the functional block that constitutes above-mentioned ASIC by above-mentioned customer requirements, the net table that link information constituted between the port of generation by a plurality of functional blocks of above-mentioned user's appointment;

Be filled into the data of the synthetic object functionality piece that finishes of logic in the net table that has generated, generate the ROM data that write down the PLD circuit;

On the aforementioned calculation machine, demonstrate the ROM data that generated and generate the result;

Utilize Email to user notification simultaneously.

So the user does not need the special-purpose development environment of PLD, can reduce the ROM data of record PLD circuit are write required load, time and expense.

And; The present invention; It is characterized in that also having a kind of interim net table creating device; This device is used for not accomplishing as yet and not having under the situation of circuit data in the function block design of the ASIC that constitutes user's appointment, generates a kind of circuit interim trigger circuit of use etc. and is inserted into the input terminal of this functional block and the net table in the lead-out terminal.

Should invention if adopt, the function block design that then constitutes the ASIC of user's appointment is not accomplished as yet and is not had under the situation of circuit data, generates a kind of circuit interim trigger circuit of use etc. and is inserted into the input terminal of this functional block and the net table in the lead-out terminal.So, in the checking of passing through model machine of PLD,, also can verify by enough model machines even be not the design completion as yet of the functional block of identifying object, can improve verification efficiency.

And the present invention is characterized in that having:

Monitoring arrangement, the change scale that up-to-date circuit data that is used for above-mentioned user is had and instrument deviser carry out between the instrument designed circuit data is kept watch on;

Change is notifying device regularly; Be used in that time is up the date of planning according to the supervision result of above-mentioned monitoring arrangement and required time of planning and design when reaching; The instrument that is reflected in above-mentioned change above-mentioned ASIC designs interior timing, notifies the instrument deviser of above-mentioned user and ASIC with E-mail mode; And

Reflection stops claimed apparatus, is used for requirement and stops, so that the user responds regularly notifying device of above-mentioned change, changes the date of above-mentioned reflection.

If adopt the present invention, then because the change scale that up-to-date circuit data that above-mentioned user is had and instrument deviser carry out between the instrument designed circuit data keep watch on;

According to the supervision result of above-mentioned monitoring arrangement and required time of planning and design and time is up the inside the plan date when reaching; The instrument that is reflected in above-mentioned change above-mentioned ASIC designs interior timing, notifies the instrument deviser of above-mentioned user and ASIC with E-mail mode; And

Requirement stops, so that the user responds above-mentioned notice, changes the date of above-mentioned reflection.

So, can be reflected to the change that takes place expeditiously in the ASIC planning and design, through setting the timing of reflection change, can judge the user and when can change simultaneously, can revise calendar plan in the stage early.

And; The present invention; It is characterized in that: on the one hand; The 1st layout of describing according to all or part of the terminal information of FPGA of functional block that comprises a plurality of functional blocks and the 2nd layout of describing as the described terminal information identical of subordinate's layer of the 1st layout with this FPGA; Generate between the same terminal in the 1st layout, the 2nd layout and connect; And the FPGA that between this terminal, has inserted FPGA corresponding buffered device uses layout information, on the other hand, and the 3rd layout of describing according to the terminal information of the ASIC that comprises a plurality of functional blocks and the 4th layout of describing as the described terminal information identical of subordinate's layer of the 3rd layout with this ASIC; Generate between the same terminal between the 3rd layout, the 4th layout and connect, and the ASIC that between this terminal, has inserted ASIC corresponding buffered device uses layout information.

Above-mentioned the 2nd layout, the 4th layout are replaced as the circuit information that the link information according to the included functional block of each layout generates respectively,

So, generate the net table of FPGA and ASIC.

If adopt the present invention; Then because on the one hand; The 1st layout of describing according to all or part of the terminal information of FPGA of functional block that comprises a plurality of functional blocks and the 2nd layout of describing as the described terminal information identical of subordinate's layer of the 1st layout with this FPGA; Generate between the same terminal in the 1st layout, the 2nd layout and connect; And the FPGA that between this terminal, has inserted FPGA corresponding buffered device uses layout information; On the other hand; The 3rd layout of describing according to the terminal information of the ASIC that comprises a plurality of functional blocks and the 4th layout of describing as the described terminal information identical with this ASIC of subordinate's layer of the 3rd layout generate between the same terminal between the 3rd layout, the 4th layout and connect, and the ASIC that between this terminal, has inserted ASIC corresponding buffered device uses layout information.

Above-mentioned the 2nd layout, the 4th layout are replaced as the circuit information that the link information according to the included functional block of each layout generates respectively,

So, generate the net table of FPGA and ASIC.

So concurrent development ASIC and PLD expeditiously can shorten construction cycle of ASIC.

Description of drawings

Fig. 1 is the process flow diagram of the principle of expression the inventive method.

Fig. 2 is the action specification figure of the present invention's the 1st embodiment.

Fig. 3 is the block scheme of embodiment one example of the control device of expression logic synthetics of the present invention.

Fig. 4 is the block scheme of expression control device one embodiment example.

Fig. 5 is the process flow diagram (1) of presentation logic magnetic core generator program

Fig. 6 is the process flow diagram (2) of presentation logic magnetic core generator program

Fig. 7 is the process flow diagram of the detailed procedure of expression the present invention the 1st embodiment.

Fig. 8 is the process flow diagram of presentation logic magnetic core layout inspection control.

Fig. 9 is the process flow diagram of expression Combination Control.

Figure 10 is the process flow diagram and processing image figure that the expression inputoutput buffer inserts control.

Figure 11 is the process flow diagram of expression IC design program.

Figure 12 explanation relates to ASIC of this 2nd embodiment and the key diagram that FPGA concurrent development notion is used.

Figure 13 explanation relates to ASIC of this 2nd embodiment and the FBD that the FPGA parallel development system constitutes.

Figure 14 is the figure that is illustrated in catalogue formation one example that store data is used in the file server.

Figure 15 is that presentation logic CORE generates the figure with an example of table.

Figure 16 is the process flow diagram of handling procedure of ASIC and the FPGA parallel development system of expression the 2nd embodiment.

Figure 17 is the figure of expression typing picture one example.

Figure 18 is the figure of representation program picture one example.

Figure 19 is the process flow diagram that presentation logic CORE generates the handling procedure of interface routine.

Figure 20 is the figure that presentation logic CORE generates interface screen one example.

Figure 21 is the process flow diagram (1) of the handling procedure of expression ASIC logic CORE generator program

Figure 22 is the process flow diagram (2) of the handling procedure of expression ASIC logic CORE generator program

Figure 23 is the process flow diagram of the handling procedure of presentation logic CORE scrutiny program.

Figure 24 is the figure that the expression situation shows an example of selecting picture.

Figure 25 is the figure of an example of presentation logic CORE generating state picture.

Figure 26 is the process flow diagram of the handling procedure in the display frame of expression ASIC logic CORE generating state.

Figure 27 is the figure that expression fpga logic CORE generates interface screen one example.

Figure 28 is the process flow diagram (1) of the handling procedure of expression fpga logic CORE generator program

Figure 29 is the process flow diagram (2) of the handling procedure of expression fpga logic CORE generator program

Figure 30 is the figure that an example of encapsulating sheet is exchanged in expression.

Figure 31 is the process flow diagram of the handling procedure of the synthetic interface routine of presentation logic.

Figure 32 is the figure of an example of the synthetic interface screen of presentation logic.

Figure 33 is the process flow diagram of the synthetic interface handling procedure of expression fpga logic.

Figure 34 is the figure of an example of the synthetic situation display frame of presentation logic.

Figure 35 is the input of expression fitting data and the figure that carries out an example of picture.

Figure 36 is the figure of an example of expression ROM data generating state picture.

Figure 37 is that the figure routine with of real screen is scheduled in expression.

Figure 38 is the figure of the example of expression handwork time.

Embodiment

Following with reference to accompanying drawing, specify embodiment example of the present invention.

< the 1st embodiment >

Fig. 2 is the action specification figure of the present invention's the 1st embodiment.This figure is input with the circuit structure result of study, makes the design data universalization, common circuit structure, exploitation integrated circuit.

Under the situation that with HDL is the means function that designs realization, the chip of product own is made up of the instance with certain function.This instance is with reference to the piece that a plurality of function constituted by the HDL design, if specific piece is needs to the realization chip functions, and so can be repeatedly with reference to this piece.

Following according to Fig. 2, flow process of the present invention is described, X, Y, Z are the tables that comes the port specification to the piece worked out according to the circuit structure result of study to define according to definition format.These Table X, Y, Z must work out when design block, and it has with the lower part: piece name, Instance Name, port name, scope, output are gone into, kind, output place instance, the output port name of output place instance etc.These data are by the manual input of user.Each table of establishment like this, in advance is main points of the present invention.

It is input that the S1 step is utilized the table data with above-mentioned whole instances; To whether being connected device of correctly checking and the device that the net between instance is defined between instance with between instance and the outside terminal that is defined as the device package terminal, only generate the logicor logic core that constitutes by the port of piece and interblock link information.Walk out of at S1 under the situation of existing mistake, turn back to the user place to mistake, re-enter data (arrow labeled 1 expression of the garden shape shown in the figure repeatedly) by the user.

The S2 step is with reference to FPGA table 2; Be read into the logicor logic core of S1 step output in the logic synthetics, select group, under the state that keeps level information, generate new logicor logic core as the instance of PLD through the function of steering logic synthetics; Export the net table of the identical logicor logic core of a kind of and S1 step output; Wherein do not comprise inputoutput buffer that exists with ... device technology etc., in the figure, X, Y are by user's appointment.

The S3 step is according to the conduct terminal name of the terminal specification table data of the device package of definition format; Generate interim logicor logic core; The inputoutput buffer that exists with ... device technology by the appointment of table data; After being inserted in the port of interim logicor logic core, replace to the net table of S2 step output, this is a key of the present invention.Handle through this, formed net table, then as the device chip of object; The function of steering logic synthetics; From the synthetic results repository 3 of FPGA, read and accomplished the synthetic circuit data of logic, be filled in the corresponding piece, accomplish the net table of required device with the object device technology.The net table that generates as FPGA carries out match with the programming and distribution instrument of FPGA, realizes the ROM datumization.

And,, carry out ASICization with reference to the synthetic results repository 4 of ASIC from the S2 step.

If adopt the 1st embodiment, then in lsi development, its effect is; Can guarantee port specification quality in advance as the piece of RTL design input; And, have many functional blocks, in the exploitation of the large scale integrated circuit that design resource is also a lot; Therefore connection that also can the prior confirmation interblock can guarantee that one assembles chip surely.

Fig. 3 is the block scheme of an embodiment of expression logic synthetics control device of the present invention.

Among the figure, the 22nd, the control device that molar behavior is controlled, the 24th, show the CRT of various information, the 21st, to control device 22 in, import the input media of usefulness such as various instructions, the 23rd, be connected with control device 22, be used for the memory storage of storing various information.

Input media 21 is used for the starting command of input logic magnetic core generator program, the control command of logic synthetics, in memory storage 23, has stored logic synthetics, logicor logic core generator program, the synthetic control program of logic.

If the list file of physical block from input media 21; Input logic magnetic core generator program starting command; Then the logicor logic core generator program reads list file, formation logic magnetic core, output file in memory storage 23; If wrong in this is handled, then be shown to this error message on the CRT24 of display device.

The deviser under vicious situation, after the list file correction, fill order once more.In the control of logic synthetics, at first the necessary data used of prepare control stores on the assigned position in the memory storage 23 as the logicor logic core file that generates in file and the logicor logic core generator program together.And, as if the control command of coming the input logic synthetics from input media 21, then logic synthetics starting, result is presented on the CRT24.Handle under the situation of failure halfway, the state during failure is shown on the CRT24.

Fig. 4 is the routine block scheme of an embodiment of the control device 22 of presentation graphs 3.The symbol that the part identical with Fig. 3 mark is identical, among the figure, the 31st, the CPU that molar behavior is controlled, the 32nd, the storer of storing various information, the 21st, the keyboard of input various command etc., the 24th, as the CRT that shows device.The 23rd, memory storage, it is by the control program 35 of logicor logic core generator program 36, logic synthetics, logic synthetics 34 and operating system (OS) 33 and constituting.The 37th, connect the bus between each inscape.Memory storage 23 for example adopts Winchester disk drive.

In the system of this formation, CPU31, when input during from the order of keyboard 21, retrieval storage devices 23 calls this program, carries out this program.

Fig. 5, Fig. 6 are the process flow diagrams of presentation logic magnetic core generator program.Wherein, utilize X, the Y of Fig. 2, the table data of Z to describe.Read the file of table data X, Y, Z (instance also is X, Y, Z), file is handled singly.Read the data of X at F1, the total data in that F2 extracts the table of port A out stores in the storer, and the limit is with reference to the data of this storer, and following processing is carried out on the limit.Whether at F2 ' inspection port is output.

Because port A is input, goes on foot and jump over over so be used for outputing to F3 in the file A to Instance Name and port name, in the entering F3 '.In F3 ' inspection whether the concatenated key with package terminal is arranged.Then, because there is not the concatenated key of package terminal, so, skip and be used for storing the total data of following port B the F4 of package terminal information stores in the storer into storer in.

Because port B is output, so utilize the F3 step to output to " XB " in the file A of memory storage 23.At this, X is a filename, and B is a port name.Below, because there is not the concatenated key of package terminal, so, skip F4, store the total data of following port Z in the storer into.Because port Z is output, so utilize the F3 step to output to " XZ [2:0] " in the above-mentioned file A.At this, [2:0] expression 2,1,0.

Below, because there is not the concatenated key of package terminal, so, skip F4, store the total data of following port one in the storer into.Because port one is input, so, skip F3, below because the concatenated key " IO " of package terminal is arranged, so " IN puT, in, 2:0,, store in the storer as the port name of logicor logic core.All whether port finishes (F4 ') in inspection below.Under whole still unclosed situation of port, turn back to the F2 step.

Like this, if the processing of whole ports of X finishes, be VHDL, then output to entity file in the memory storage 23 with following information.

A：in?std_logic；

B：out?std_logic；

Z：out?std_logic vector(2?downto?0)；

I：in?std_logic；

More than handle the data of Y, Z are also all carried out, when all files finishes (F5 '), utilize the F6 step, if VHDL then outputs to the entity file of the logicor logic core with following information in the memory storage 23.

INPUT：in?std_logic；

OUT：out?std_logic；

And, the following data of record in file A.

XB、XZ[2:0]、YC[1:0]，YO、ZF

Below go on foot the data that read above-mentioned file A with F7, go on foot to store memory storage with F8, file is handled singly.Check with the F8 ' step whether port is input.At this, describe with the table data instance of X.Because port A is input, so, go on foot the Y that extracts output place out and the C of port name with F9, utilize F10 to go on foot and retrieve according to the data of having stored YC [1:0] by F8.And, whether consistent with the inspection of F10 ' step.

The result of retrieval is because exist, so utilize the F12 step to output to following link information in the file B.Under the inconsistent situation of result, output to the title of port or the not equal error message of scope in the log file of memory storage 23, be also shown on the CRT24 simultaneously.

A＝＞YC

Be output likewise below because of port B, so, utilize the F11 step to output to following link information in the file B.

B＝＞XB

Below, likewise because port Z is output,, output to following link information in the file B so utilize the F11 step.

Z＝＞XZ

Below, port one is input, but utilizes the retrieval in F10 step to cannot see " IOINPUT ", utilizes the F13 step, outputs in the log file as mistake, is simultaneously displayed on the CRT24.But, under the situation of the port that is connected with package terminal, not problem, opposite to outputing to the error message on the record, can confirm is that which port of which instance with which terminal of encapsulation is connected.Below utilize the F12 step to output to following link information in the file B.

1＝＞IOINPUT

Whether whole ports of all showing in the inspection of F12 ' step finish, under unclosed situation, turn back to the F8 ' step.

Above processing; Table data to Y, Z are also carried out; When end, utilize F14 to go on foot and output to the port of failing to work out link information in the log file, utilize F15 to go on foot and make the entity of the logicor logic core of exporting by the F6 step and go on foot the link information of exporting to combine formation logic magnetic core net table by F11 and F12; Output in the memory storage 23 termination routine.

Below utilize accompanying drawing, specify the detailed procedure of the present invention's the 1st embodiment.Fig. 7 is the process flow diagram of the detailed procedure of expression the present invention the 1st embodiment.It is the later processing of S2 of input that this process flow diagram is illustrated in the logicor logic core of exporting with S1 in the 1st embodiment of Fig. 2 explanation in detail.Among the figure, solid line is represented the flow process handled, and dotted line is represented the flow process of data.Before processing was carried out, if input device need be by the logicor logic core of S2 step output, then utilizes mode such as duplicate to put into the control documents that occurs in the explanation afterwards on the interior position of the memory storage of control program reference.

At first, inspection logicor logic core layout (a1).Check this logicor logic core layout whether well (a1 ') then.Not under the good situation, carrying out once more after the table data of controlling chart 2 explanations (a10).Being under the good situation, with reference to file 12,13, make up (a2), store as logicor logic core 10.Then, the table 14 with reference to being made up of terminal name and impact damper name generates interim logicor logic core (a3).Its result generates interim logicor logic core 11.

Following basis this interim logicor logic core 11 and table 14 insert inputoutput buffer (a4).Then, logicor logic core 10 and interim logicor logic core 11 are compared inspection (a5).And whether inspection the comparative result of good (a5 '), being under the good situation, carries out terminal processes (a6).Be not under the good situation, inspection device package terminal specification (a9) after the table data of controlling chart 2 explanations, is carried out (a10) once more.

When the terminal processes in a6 step finishes, with reference to synthetic destination file 15, insert circuit data (a7), with reference to file 16, insert DFT circuit (a8).

Following further explain is in each step illustrated in fig. 7.Fig. 8 is the process flow diagram of presentation logic magnetic core layout inspection control.

At first whether inspection has the file (a11) of logicor logic core.Under situation about having, read (a12) with the logic synthetics.Under situation about not having, do not do any action.A1 (referring to Fig. 7) step at the logicor logic core of S2 step output as input, the step to the HDL describing method of logicor logic core, empty input port etc. are checked if there is the logicor logic core file, then is read into logicor logic core in the logic synthetics in the a12 step.The logic synthetics has when reading in the function of the inspection syntax etc.If the result then confirms content with CRT wrong, and the table data to the port specification of description block shown in the a10 step are examined, and check layout once more.

Fig. 9 is the process flow diagram of expression Combination Control, the detailed content in a step of its presentation graphs 7.At first inspection has or not logicor logic core file (a13), and under situation about having, whether inspection has the instance document (a14) of combination.Under situation about having; Even among the result in a1 step under the no problem situation; If the file 13 of piece name record in delegation of the object of pair PLDization is arranged; Then it is read (a21), under the state that the level information of object piece keeps, the combination function of logic synthetics is controlled, make up (a22) as new logicor logic core.

Under the situation of using combination function; Because the logicor logic core name becomes the user name to connecting between the instance; So, make net to the logicor logic core internal trace to whole ports of logicor logic core, utilize the initial instance port name of finding that new port takes place in logicor logic core; Become the net that is connected on the port of the logicor logic core that user name claims and be connected on the new port of generation, the port deletion (a23) that becomes user name.This is in order to make new port, the old port of cancellation.

Below whether inspection has monitor port information (a23 ').Under situation about having, in logicor logic core, utilize the port name of the instance of appointment to come originating port, give be connected (a24) with the piece end.Under situation about not having; Being not included in interior net table to the inputoutput buffer that exists with ... device technology outputs in the memory storage 10 (referring to Fig. 7) (a25); In the case, in display device, can utilize the Presentation Function of logic synthetics to confirm.

Other in this a2 step if be necessary that the piece port that then also can make up is as logicor logic core port (a24).This function has when being used in the functional evaluation of PLD under the situation of the port that desire keeps watch on.Designation method is shown in file 12, to read after combination and port name change for the file of in each row, putting down in writing the port name of a port.

So far, because deviser itself utilizes the data of the port specification of specified block to generate logicor logic core, so the port between the piece in the logicor logic core should be to be free from mistakes on connecting.Yet; Under the situation of the ASIC that directly uses the logicor logic core that the S1 step (referring to Fig. 2) generates; The device package terminal title that in logicor logic core, defines in the table data of piece; Generally with reference to device package terminal specification, so possibly be that simple mistake or change of Printed Circuit Board Design etc. are former thereby mistake occurred.In contrast, the port of the logicor logic core that is generated by a2 (referring to Fig. 7) becomes under the situation of device package terminal, because this port becomes specification, so the same with above-mentioned situation have difference.This problem goes on foot a5 step by a3 and solves.

Figure 10 is the figure of the image of expression inputoutput buffer process flow diagram and the processing of inserting control.The processing in the a4 step of this flowcharting Fig. 7.In following explanation, from a3 to a5,, be to handle continuously with an order but handle as independent.

At first, whether inspection has the file (a15) of outside terminal information and logicor logic core.Carry out following processing sometimes.A3 is different with a2; Be shown in the 1st row like 14 of Fig. 7 the terminal title is defined; In the 2nd row, the inputoutput buffer name that exists with ... used device technology is carried out justice, if the table data of such device package terminal specification exist, so; It is read; (a31), above-mentioned interim chip design pattern takes place as unit (as subordinate's layer of the 1st layout, the 2nd layout that the terminal information identical with the 1st layout of describing is described) in portion within it to work out out interim chip design pattern (the 1st layout that the terminal information of title of the 1st row is described); Port to the same title between above-mentioned layout and said units is connected, the interim logicor logic core of output in memory storage 11.

Go on foot at a4; Read the interim logicor logic core of storer 11; The inputoutput buffer that has in the 2nd row for device package terminal specification table data 14 inserts the inputoutput buffer (a32) that exists with ... device technology according to chip terminal information to interim logicor logic core net.

Go on foot at a5; In the port of above-mentioned interim logicor logic core since be do not relate to the device of the irrelevant logic of function peculiar; And the port of eliminating that test is used etc. is replaced (a33) as the logicor logic core of internal element and memory storage 10, checks out whether have terminal name inconsistent (a33 ').If the port title between 2 logicor logic cores is all consistent, fill successfully so.So, the terminal title that can cross-check device package terminal specification table data and the port title of logicor logic core can be eliminated the problems referred to above.End process under the situation of unanimity, output net table under inconsistent situation.

Under the situation of failure, shown in the a9 step, inspection device package terminal specification goes on foot beginning from a3 and carries out once more, and perhaps shown in the a10 step, the table data that inspection defines piece terminal specification go on foot (referring to Fig. 2) from S1 and carry out once more.Under case of successful, launch logicor logic core stratum, form chip.

In a6 step, on the I/O port of whole pieces of said chip, be connected to piece inside to trigger circuit, as the terminal.This terminal processes be for, even there is uncompleted of circuit design, also can generate the net table, no problem, can carry out the programming and distribution operation.

In the a7 step, the synthetic circuit data that finishes of logic is read from synthetic results repository, is filled in the corresponding piece.At this moment, if there is not the synthetic result to the piece of chip internal, and the layout title of piece or unit title meet naming rule, and so, input port and the output port to this piece carries out connection processing in this piece inside by rule in advance.

This is handled, and under the situation of PLD, does not exist; Become distinctive of DLL that makes PLD etc. under the situation of ASIC and just carry out.In the inner processing that connects of piece, can keep one-piece construction through not eliminating this piece.And, exist under the situation of macroefficiency such as storer in piece inside, replace to the distinctive memory circuitry data of device.

In the processing of A8 under the situation of ASIC, the SCAN test circuit of test component inserts automatically, perhaps imports a kind of file 16 that the order of piece is defined, so that connect the SCAN test circuit, connects by definition of order.

As stated; If adopt this 1st embodiment, then generate logicor logic core according to the data in the design document, keeping from this logicor logic core under the state of hierarchical structure and link information; For PLD with regenerating logicor logic core; Such effect is can the common circuit structure, and this logicor logic core is filled the circuit data that does not exist with ... device technology and the net between instance in the instance that circuit data function verifies, can under the situation of ASICization, avoid verifying again.Therefore its effect is, also can be to ASIC and PLD concurrent development expeditiously.

< the 2nd embodiment >

Below specify the parallel development system that relates to ASIC of the present invention and FPGA.And the design language of logic has C language, UML etc., in the 2nd embodiment, describes as design language with HDL.

The notion of the concurrent development of the ASIC that relates to the 2nd embodiment and FPGA at first, is described.Figure 12 is that explanation relates to the key diagram that the concurrent development notion of ASIC and the FPGA of the 2nd embodiment is used.Shown in figure; The characteristic of the concurrent development of this ASIC and FPGA is: carry out simultaneously in order to make the model machine checking and the design of ASIC instrument that utilize FPGA; Designing according to the ASIC instrument provides a kind of ROM data; Wherein write down model machine and verified necessary FPGA circuit, can carefully seamlessly develop FPGA and ASIC.

In the concurrent development of this ASIC and FPGA; In circuit structure research, consider and verify model machine with FPGA; Utilize the realization circuit of suitable expectation scale to divide the realization function; Relate between ASIC and the FPGA structure not simultaneously function divide stratum etc., the port of the functional block that the general purpose function block between ASIC and FPGA design is constituted is formulated specification.The port specification data of this functional block formation and functional block, layout, the logic that becomes the instrument design of ASIC synthesized, the conventional data of planning and design.

In the RTL design verification, according to the structure of circuit structure result of study, carry out the general RTL design of ASIC and FPGA, every kind of function is attached most importance to the angle box carry out software verification with the logic detection instrument.To carry out the ASIC logic simultaneously synthetic with this RTL design verification, if can guarantee the characteristic of ASIC, it is synthetic to carry out fpga logic below then, forms circuit at model machine one by one on the FPGA on the substrate, and model machine that can enough FPGA is verified.

On the other hand; In the programming and distribution of ASIC; According to the general utility functions block structure between ASIC and FPGA design, reflect the checking result of software verification and model machine at any time simultaneously, shorten like this and play ASIC from verifying of the model machine of FPGA and develop the cycle till finishing.

Below explanation relates to the system architecture of parallel development system of ASIC and the FPGA of the 2nd embodiment.Figure 13 is a FBD, and its expression relates to the structure of parallel development system of ASIC and the FPGA of the 2nd embodiment.Shown in figure, the parallel development system 200 of this ASIC and FPGA has: fire wall 210, network server 220, subscriber authentication server 230, subscriber management server 240, logic synthesis server 250, mail server 260, file server 270, application server 280 and monitor server 290.

And the parallel development system 200 of this ASIC and FPGA can be utilized by net client computer 100 through the internet.

Fire wall 210 is a kind of visiting demands to coming from the internet, only accepts to meet the computing machine of the visiting demand of setting signal procedure, and it can prevent from the outside the improper visit to the parallel development system 200 of ASIC and FPGA.

Network server 220 is that the computing machine that information is sent is carried out in the requirement that the net client computer 100 that forms through the internet is sent; It has following each several part: the logicor logic core that only generates logicor logic core by the link information between the port of the port of the functional block that constitutes ASIC and FPGA and functional block generates interface routine 221, the synthetic interface routine 222 of logic, match interface routine 223, situation display interface program 224, logicor logic core and generates necessary formatted file and the synthetic necessary formatted file of logic; This computing machine is according to the requirement of net client computer 100; Carry out these programs, send to the result in the net client computer 100.

Subscriber authentication server 230 is the computing machines that carry out authentification of user, user name and password that based on contract its registration is used.Subscriber management server 240 is the computing machines that carry out user's registration, cancel, and based on contract its register and user name and the following entry name and the addresses of items of mail of use.

Logic synthesis server 250 be have ASIC logicor logic core generator program 251, fpga logic magnetic core generator program 252, ASIC logic synthesis program 253, fpga logic synthesis program 254, as the computing machine of the fit procedure 255 of the programming and distribution of FPGA; Logic in this logic synthesis server 250 is synthesized the program with match; Start by the synthetic interface routine 222 of logic; Read the RTL source of file server 270 stored, the logic of execution ASIC and FPGA is synthesized the match with FPGA.

Mail server 260 is the computing machines with mail transmission/reception software, the process information that it carries out network server 220, distributes to user and system from the information of net client computer 100 with lettergram mode.

File server 270 is mediums of the ROM data of the synthetic result in stored logic synthetic object RTL source, logic, FPGA etc.Figure 14 is the figure that is illustrated in bibliographic structure one example that the file server store data inside uses.With the project (project) the 41st shown in the figure, the catalogue of the entry name of exploitation ASIC and FPGA or the nickname of ASIC, based on contract this title is set.

The 1042nd, be stored as the catalogue of the data that the formation logic magnetic core uses, in the functional block unit that constitutes ASIC, have:

Directory A SIC48, it is deposited logicor logic core and generates the file with table, has wherein narrated the port specification of functional block shown in Figure 15; And

Catalogue FPGA49, wherein by logicor logic core generate interface routine 221 according to the user specify duplicate and storage directory ASIC48 in logicor logic core generate file with table.

And, below catalogue FPGA49, have catalogue, and logicor logic core generates to be narrated after the detailed content that generates interface routine 221 with table and logicor logic core is treated by the number of the FPGA of user's appointment numbering.

Logicor logic core 43 is catalogues of depositing the logicor logic core that is generated by the logicor logic core generator program, and it has: directory A SIC50 that the ASIC logicor logic core that generates is deposited according to the functional block port specification that constitutes ASIC and the catalogue FPGA51 that deposits the fpga logic magnetic core according to the port specification of the functional block that constitutes FPGA.

RTL44 is a catalogue of depositing circuit design data (below be called RTL); HDL (hardware description language) is adopted in its performance; By the user from the synthetic interface dress of following logic, the catalogue FPGA53 that it has the directory A SIC52 that deposits in the functional block unit that constitutes the ASIC logicor logic core and duplicates and deposit the RTL in the ASIC catalogue according to user's appointment.

Comprehensive 45 is to be used to deposit the catalogue of being carried out the synthetic result of logic by 250 couples of RTL of logic synthesis server, and it has:

Directory A SIC54, its have the synthetic result of the logic of ASIC be stored in the functional block unit that constitutes the ASIC logicor logic core catalogue and

Catalogue FPGA55, it has the synthetic result's of logic who is used to deposit each FPGA catalogue.

ROM46 is a catalogue of depositing the ROM data, and the FPGA circuit data of storage wherein generates after the match as the programming and distribution of FPGA according to the synthetic result of fpga logic, has the catalogue of depositing by each FPGA.

Programming and distribution 47 are the job catalogs that carry out ASIC programming and distribution design by the programming and distribution of ASIC design responsible official.

Application server 280 is to have the ASIC layout, and the computing machine of the program of usefulness is verified in programming and distribution design, timing.Utilize this computing machine to carry out floor plan, planning and design, the regularly checking of ASIC by the instrument deviser.

Monitor server 290 is obtained the user name and the entry name of registration in subscriber management server 240; Be arranged in the data of the catalogue of projects name; The collection that comparison, the logic of the data in the data in the catalogue programming and distribution of being in charge of by the instrument designer 47 and other catalogues is synthetic, programming and distribution need the time of instrument in handling; Collected 1 time in 1 day, and divided and carry out for 2 times, the 1st time changing context notification to the instrument designer; The time of collecting for the 2nd time upgrades the schedule of reflection change as the basis.

The following handling procedure of the parallel development system 200 of ASIC and the FPGA of explanation the 2nd embodiment.Figure 16 is the process flow diagram of handling procedure of parallel development system 200 of ASIC and the FPGA of expression the 2nd embodiment.

Shown in figure; If visit the parallel development system 200 of this ASIC and FPGA with net client computer 100; Then network server 220 sends to the demonstration control data of typing picture shown in Figure 17 in the net client computer 100, and net client computer 100 is come display frame according to paid-in data.The user imports the user name and the password of based on contract registering on this typing picture, push the Login button, then nets client computer 100 and sends to user name and password in the network server 220.

Network server 220 is to subscriber authentication server 230 paid-in user name of inquiry and passwords.Whether 230 pairs of subscriber authentication servers have registered user name and password is confirmed (S501 step), and its result is turned back in the network server 220.Network server 220 sends to the demonstration control data of typing refusal picture in the net client computer 100 under situation about being refused by subscriber authentication server 230, and net client computer 100 demonstrates typing and refuses according to the data of receiving on picture, finish (S502 step).

Network server 220 is being accepted from subscriber authentication server 230 under the situation of typing, sends to the demonstration control data of program picture shown in Figure 180 in the net client computer 100, and net client computer 100 demonstrates program picture (S503 step) according to the data of receiving.

The user is according to program picture shown in Figure 180, and choice menus carries out the concurrent development of ASIC and FPGA.The user is if select " form 1 " and " form 2 ", (affirming of S504 step), then be positioned at network server 220 object designing institute need formatted file download to and net client computer 100 (S505 step).

" form 1 " is that the tableau format data are used in logicor logic core generation shown in Figure 15." form 2 " is to be electrically connected the table formateed data that the inputoutput buffer of usefulness defines between terminal title and the distribution of terminal numbering and the ASIC and the external devices of encapsulation of the ASIC that in the logic of following ASIC is synthetic, uses.

The user then nets client computer 100 and delivers in the network server 220 having selected logicor logic core to generate an incident if select logicor logic core to generate (affirming of S506 step), and 220 pairs of logicor logic cores of network server generate interface routine 221 and start (S507 step).

If the user selects logic synthetic (affirming of S508 step), then net client computer having selected the synthetic incident of logic to deliver in the network server 220, the synthetic interface routine 222 of 220 pairs of logics of network server starts (S509 step).

The user then nets client computer 100 having selected match one incident to deliver in the network server 220 if selected match (affirming of S510 step), and 220 pairs of match interface routines 223 of network server start (S511 step).

The user is if choice situation shows (affirming of S512 step), then nets client computer 100 having selected situation to show that an incident delivers in the network server 220.220 pairs of situation display interfaces of network server program 224 is started (S513 step).

Below the explanation logicor logic core generates the handling procedure of interface routine 221.Figure 19 is the process flow diagram that the presentation logic magnetic core generates the handling procedure of interface routine 221.Shown in figure; This logicor logic core generates interface routine 221; The demonstration control data that generates logicor logic core shown in Figure 20 interface screen sends in the network server 220; Network server 220 sends to the demonstration control data that the logicor logic core of receiving generates interface screen in the net client computer 100, and net client computer 100 demonstrates logicor logic core and generates interface screen (S801 step) according to the demonstration control data of paid-in logicor logic core generation interface screen.

User's cuit name; Select to carry out button; Select picture to specify logicor logic core shown in Figure 15 to generate file according to the file that shows by net client computer 100, so that the IO specification of the functional block of the formation ASIC that is used to generate the ASIC logicor logic core is defined with table.

Net client computer 100 transmission project specific data and IO logicor logic core to network server 220 in generate the file that usefulness is shown; Network server 220 is worked out (S802 steps) such as IO42 shown in Figure 14, logicor logic core 43, RTL44, comprehensive 45, ROM46, programming and distribution 47 in file server 270; Deposit logicor logic core in the directory A SIC48 below IO42 and generate file with table; The technical routine name is carried out ASIC logicor logic core generator program 251, is stored in (S803 step) in the storer to implementation ID.

At this, the handling procedure of ASIC logicor logic core generator program 251 is described.Figure 21, Figure 22 are the process flow diagrams of the handling procedure of expression ASIC logicor logic core generator program 251.Shown in figure 21, this ASIC logicor logic core generator program 251 reads logicor logic core shown in Figure 15 and generates with Table X, Y, Z from the directory A SIC48 of Figure 14, carry out file processing singly.

It is the port specification to the functional block of working out according to the circuit structure result of study that logicor logic core generates with Table X, Y, Z, has carried out the table of definition according to " form 1 " that defined.This table must be worked out when the design function piece, and it is by constituting with the lower part: functional block name, Instance Name, port name, scope, output are gone into, the output port name of kind, output place Instance Name, output place instance etc.So-called instance is meant with reference to the functional block that constitutes ASIC, under the situation of the functional block of using a plurality of same functions, changes the instance title and assembles.

At first, read the data (S1001 step) of X, extract the total data of the table of port A out, be stored in the storer (S1002 step), whether inspection port A is output (S1003 step).Its result, port A is input, so, following the having or not of concatenated key " IO " (S1005 step) of inspection package terminal.Its result does not have concatenated key " IO ", so, store the total data of following port B in the storer into.

Because port B is output, so, export (S1004 step) to " XB " with the title of A at the enterprising style of writing part of the directory A SIC50 of Figure 14.Below because there is not the concatenated key " IO " of package terminal, so, store the total data of following port Z in the storer into.Because port Z is output, output to " XZ [2:0] " on the file A.Below because there is not the concatenated key " IO " of package terminal, so store the total data of following port I in the storer into.

Port I is input, below because the concatenated key " IO " of package terminal is arranged, so, store (S1006 step) in the storer to " INPUT, in, 2:0 " into as the port name of logicor logic core.Finish the processing (affirming of S1007 step) of whole ports of X like this, the entity file that has carried out definition with range information is gone in port name, output, export (S1008 step) at the enterprising style of writing part of the directory A SIC50 of Figure 14 with the title of X according to the syntax of HDL.The content of output, if VHDL then is following content:

A：in?std_logic；

B：out?std_logic；

Z：out?std_logic?vector(2?downto?0)；

I：in?std_logic；

And, Y, Z data are also carried out above processing.And, in this stage, the following data of record in file A.

XB、XZ[2:0]、YC[1:0]，YO、ZF

More than if finish the processing (affirming of S1009 step) of all files of X, Y, Z, then read above-mentioned file A (S1010 step) data, store in the storer (S1011 step), handle file one by one, at this, the data instance of showing with X describes.Check at first whether port A is input (S1012 step), its result, because port A is input, so, extract the Y of output place and the C (S1013 step) of port name out.And, with YC [1; 0] come search memory (S1014 step), inspection has or not consistent data (S1016 step).Its result, because consistent data are arranged in storer, so, export (S1018 step) to following link information with the title of B at the enterprising style of writing part of the directory A SIC50 of Figure 14.Under the inconsistent situation of result, the equal error message of port title or scope outputs to the log file interior (S1017 step) of directory A SIC50.

A＝＞YC

Equally, because port B is output, so output to following link information the file B interior (S1015 step) of directory A SIC50.

B＝＞XB

Equally, because port Z is output, so output to following link information in the file B of directory A SIC50.

Z＝＞XZ

Equally, port I is input, can not find " IOINPUT " through retrieval, so, output in the log file of directory A SIC50 as mistake.But, under the situation of the port that is connected with package terminal, not problem, opposite but can confirm which port of which instance with which terminal of encapsulation is connected according to error message to record output.Link information below the following handle outputs in the file B of directory A SIC50.

I＝＞IOINPUT

If (affirming of S1019 step) also carried out and finished in above processing to the table data of Y, Z; The port that then can not work out link information is outputed to (S1020 step) in the log file; If VHDL then outputs to (S1021 step) in the directory A SIC50 to the entity file of the ASIC logicor logic core with following information.

INPUT：in?std_logic

OUT：in?std_logic

And; Combine the entity file of logicor logic core and link information; The entry name that utilizes Figure 17 to indicate is exported the ASIC logicor logic core at the enterprising style of writing part of directory A SIC50, end process turns back to logicor logic core shown in Figure 19 and generates in the interface routine 221 (S1022 steps).

Logicor logic core generates in the log file in the interface routine 221 catalog ASIC50 has inerrancy.If write down wrong (affirming of S804 step); Read error (S805 step) then; Entry name, inquire subscriber management server 240 and the user mail address, error message and the technological process ID that obtain send in the mail server 260, send mail (S806 step) to the user from mail server 260 with entry name.The user confirms wrong contents through this mail, carries out logicor logic core repeatedly and generates processing till error disappearance.

On the other hand; If in log file, there is not misregistration; (S804 step negate); Then entry name, inquire subscriber management server 240 and the user mail address, error message and the technological process ID that obtain and logicor logic core generate ending message and send in the mail server 260 (S807 step), send mail to the user from mail server 260 with entry name.

And; Title with " CORE+ technological process ID+ is during day " in directory A SIC50 is come scheduling; Move to the logicor logic core and the log file that in directory A SIC50, generate in this catalogue with entry name; In this catalogue with IO title scheduling; Move to the table data that had in the directory A SIC48 that in logicor logic core generates, uses in this IO catalogue, the logicor logic core scrutiny program middle finger in logic synthesis server 250 is made the directory name of the logicor logic core of the title establishment that utilizes entry name " CORE+ technological process ID+ time ", and the logicor logic core scrutiny program is started (S808 step).

This logicor logic core scrutiny program is described below the order of logic synthetics: carry out the grammar testing of ASIC logicor logic core, the not connection inspection of the I/O port of each instance of formation logicor logic core, output report.

At this, the handling procedure of logicor logic core scrutiny program is described.Figure 23 is the process flow diagram of the handling procedure of presentation logic magnetic core scrutiny program.This logicor logic core scrutiny program inspection is positioned under the catalogue of the entry name of receiving; In the directory A SIC50 of Figure 14, whether have as the ASIC logicor logic core catalogue of object and check (S1201 step); If have; So just, make the logic synthetics check (S1203 step) WORK catalog compiling (S1202 step) in ASIC catalogue with this logicor logic core catalogue.

When carrying out end; Extract error message out in the report file in the WORD catalogue; User mail address that utilizes entry name to inquire subscriber management server 240 and obtain and the technological process ID that from the logicor logic core directory name, extracts out are fed in the mail server 260 together, send to user's (S1204 step) from mail server 260.According to the Mail Contents of sending, confirm whether error message is expected by the user.

The logicor logic core that utilizes this a succession of flow process and generate can guarantee that the wiring that in user's logical design, needs only between the instance that constitutes ASIC is free from mistakes, and is assembled into ASIC surely with regard to one.This effect can be found out through logic checking.In the functional verification of a plurality of instances that constitute ASIC, under the situation of appearance and expection different actions, can keep the connection between instance, so, can debug to each function that constitutes instance, fix a breakdown.

The user below is described in the program picture of Figure 18, the processing when choice situation shows.If the user is the choice situation demonstration on the program picture of Figure 18, then starting condition display interface program 224.This situation display interface program 224 shows situation shown in Figure 24 selects the demonstration control data of picture to send in the network server 220; Network server 220 shows that the demonstration control data of selecting picture sends in the net client computer 100 to the situation of receiving, net client computer 100 shows according to the situation of receiving selects the demonstration control data of picture to come display frame.

If on this picture, select logicor logic core to make by the user; Then current situation display interface program 224 generates the demonstration control data that a kind of title that does not have a logicor logic core of logicor logic core generating state picture shown in Figure 25 shows; Send in the network server 220; Network server 220 sends to the demonstration control data of the logicor logic core generating state picture of receiving in the net client computer 100, and the net client computer 100 demonstration control datas according to the logicor logic core generating state picture of receiving come display frame.

If draw by user's cuit name at this; Select display button; Then send to entry name in the network server 220 by net client computer 100; Received that from network server 220 the situation display interface program 224 of entry name extracts the directory name of the logicor logic core in the directory A SIC50 of Figure 14 out from the catalogue of the entry name of appointment, upgraded the demonstration control data of logicor logic core generating state picture, sent in the network server 220; Network server 220 sends to the demonstration control data of the logicor logic core generating state pictures of receiving in the net client computer 100, and net client computer 100 is according to the demonstration control data of the logicor logic core generating state picture of receiving and display frame.On this picture, demonstrate the ASIC logicor logic core directory name that generates earlier.

At this, the handling procedure of ASIC logicor logic core generating state display frame is described.Figure 26 is the process flow diagram of the handling procedure of expression ASIC logicor logic core generating state display frame.As shown in the drawing, if some in the logicor logic core that the user selects to have shown selected to download (S1501 step), then can download to net client computer 100 interior (S1502 step) to the object logics magnetic core.The net table that this logicor logic core of having downloaded can be used as the chip-scale of ASIC is used in logic checking, can debug to the function that constitutes instance as stated.

On the other hand; If the user specifies the logicor logic core title; Select FPGAization button (S1503 step); Then net client computer 100 having selected entry name, logicor logic core title and FPGAization one incident to deliver in the network server 220, network server 220 sends to paid-in data in the situation display interface program 224.Situation display interface program 224 extract out the directory A SIC50 that is positioned at Figure 14, be positioned at file name as the table data of the IO catalogue under the catalogue of the logicor logic core title of object; Its result; Work out out the demonstration control data that fpga logic magnetic core shown in Figure 27 generates interface screen, send in the network server 220.

Network server 220 sends to the demonstration control data that paid-in fpga logic magnetic core generates interface screen in the net client computer 100, and net client computer 100 is come display frame (S1504 step) according to the demonstration control data that paid-in fpga logic magnetic core generates interface screen.On this picture, the table of the Instance Name of the entry name of appointment, logicor logic core name, formation logicor logic core is listed in the list box in left side.And, on this picture, also can change the logicor logic core of object, if user's technical routine name and logicor logic core name are then come frame update through the specified same processing of Figure 25.

Moreover this picture is the interface that generates the logicor logic core of FPGA according to the table data of the instance of the logicor logic core that constitutes object ASIC, and the user is given instance from the list box in left side, selects to append button, in the list box on right side, appends instance.The instance of in the list box on this right side, tabulating becomes a FPGA.If the user selects instance; Set out as the FPGA numbering of FPGA name with the integer of the meaning of one more than one of appending numbering of managing usefulness; Select to carry out button; So, net client computer 100 sends the logicor logic core name, FPGA name of entry name, the ASIC of object in network server 220, as the table (inventory) of the Instance Name of FPGA and the numbering of FPGA, in situation display interface program 224, sends paid-in data by network server 220.

And; Situation display interface program 224 according to the FPGA numbering of appointment in the catalogue FPGA49 of Figure 14, is weaved into catalogue according to the table of paid-in Instance Name; IO catalogue under catalogue directory A SIC50, the CORE title that is arranged in Figure 14; The table data consistent title copy in the catalogue of above-mentioned numbering, as independent variable, carry out fpga logic magnetic core generator program 252 to the table of table data name.

At this, the process flow diagram of the handling procedure journey of fpga logic magnetic core generator program 252 is described.Figure 28 and Figure 29 are the process flow diagrams of the handling procedure of expression fpga logic magnetic core generator program 252.

Figure 28 is identical with processing shown in Figure 21, and except that S1717 step went on foot with S1720, Figure 29 was identical with processing shown in Figure 22, so, this 2 steps only are described.

In the S1017 of Figure 22 step, Instance Name and the output port name thereof that is defined as the connection purpose side of definition in the port of input of instance of object is in storer under the situation in institute's canned data, as wrong and do not output in the log file.Can guarantee at the S1717 of Figure 29 former ASIC of being used as logicor logic core of step to connect between the port of instance, so, not wrong in this S1717 step but append as the input terminal information of encapsulation and to be stored in the storer.

And,, output to the final remaining port information that does not connect in the log file in the S1020 step of Figure 22.On the other hand; Go on foot at S1720; Utilize the log file in the object ASIC logicor logic core catalogue of " CORE+ process ID+ date " and establishment under the directory A SIC50 of Figure 14 and compare at the file of S1702 step output, the output port that in the log file of S1020 step output, does not have appends and stores in the storer as the lead-out terminal information of encapsulation.The same with S1020 step then, utilize in the catalogue of numbering of the appointment under the catalogue FPGA51 of Figure 14 specified FPGA title that logicor logic core is carried out file and export.

And; Situation display interface program 224 reads fpga logic magnetic core file; The output number of terminals of going into to as encapsulation is counted, and shared ratio in the IO number in the 2nd row of the table of exchange encapsulation shown in Figure 30 is all calculated the encapsulation that the extraction ratio is maximum and exchange encapsulation of data; Upgrade the encapsulation name of fpga logic magnetic core generation interface screen shown in Figure 27, the picture demonstration control data of IO utilization rate, send in the network server 220.Network server 220 sends to the demonstration control data that paid-in fpga logic magnetic core generates interface screen in the net client computer 100; Net client computer 100 is upgraded the input picture according to the demonstration control data of paid-in fpga logic magnetic core generation interface screen.

The user then regenerates the fpga logic magnetic core once more if can not satisfy this result.If the user selects decision; Then net client computer 100 selecting decision; The data of numbering FPGA, encapsulate name and IO utilization rate send in the network server 220; Receive the catalogue that the situation display interface program 224 of these data is worked out out by the specified numbering of the catalogue FPGA55 of Figure 14 from network server 220, for example the data of receiving are carried out file output with the plist title.

Below the explanation logic is synthesized the handling procedure of interface routine 222.Figure 31 is the process flow diagram of the handling procedure of the synthetic interface routine 222 of presentation logic.As shown in the drawing; The synthetic interface routine 222 of this logic sends the demonstration control data of the synthetic interface screen of logic shown in Figure 32 and also arrives in the network server 220; Network server 220 sends to the demonstration control data of the synthetic interface screen of paid-in logic in the net client computer 100, and net client computer 100 is come display frame (S2001 step) according to the demonstration control data of the synthetic interface screen of paid-in logic.

The object functionality piece name that the logicor logic core name of the object that user's technical routine name, Figure 25 are represented, logic are synthetic and the FPGA numbering of assembling; And specify out be area preferentially or speed preferential; Be debugging (it is synthetic not carry out fpga logic) or Fix (it is synthetic to carry out fpga logic) (S2002 step); If select to carry out button (S2003 step), net client computer 100 demonstrates data and selects picture.

If the user selects the synthetic RTL source of logic according to this picture; Then these data are sent it in the network server 220 by net client computer 100; Receive that from network server 220 synthetic 222 pairs of RTL sources of interface routine of logic of data utilize the functional block name of appointment in the directory A SIC52 of Figure 14 to come scheduling, put into RTL (S2004 step).And; Read the RTL source one by one file; Releasing by user-defined frequency of operation data in the title division of the change resume in the record RTL source, version number etc.; The logic synthesis condition that speed is preferential or area is preferential that the value of having extracted out is increased frequency values and user's appointment after 20% is specified the functional block name of logic synthetic object, the ASIC logic synthesis program 253 (S2005 step) of execution ASIC logic synthetics as the synthetic restriction of logic.

If it is synthetic to finish the ASIC logic; Then the synthetic interface routine 222 of logic exported the catalogue that is positioned at the appointed function piece Figure 14 directory A SIC54 under ASIC logic synthesis program 253 the result port file and utilize entry name to inquire subscriber management server 240 and the user's of acquisition addresses of items of mail and piece name send to mail server 260, send mail (S2006 step) from mail server 260 to the user.

And this processing procedure is carried out in the whole RTL source that exists in the catalogue that the functional block name of appointment is worked out under the directory A SIC52 of the synthetic 222 couples of Figure 14 of interface routine of logic.If the logic end of synthesis of whole RTL (affirming of S2007 step); Then logic is synthesized interface routine 222 (affirming of S2008 step) under the preferential situation of the speed of being appointed as; Retrieve the synthetic result's report of logic of whole RTL, judge and whether satisfy frequency of operation (S2009 step～S2010 step) by the definition of RTL source.Under the situation of paying attention to area, do not carry out whatever.

Then; Investigation Fix specifies (S2011 step), if specify Fix, then the synthetic interface routine 222 of logic utilizes FPGA numbering scheduling under the catalogue FPGA55 of Figure 14 of appointment; Wherein, RTL to the functional block catalogue of the appointment under the directory A SIC52 that is positioned at Figure 14 duplicates storage, as independent variable, carries out the synthetic interface routine (S2012 step) of fpga logic to the entry name of appointment and FPGA numbering.

And logic is synthesized interface routine 222 start-up logic synthetics, from the CORE catalogue of the appointment of the directory A SIC50 that is arranged in Figure 14; Read the ASIC logicor logic core, input command in the logic synthetics is gone up dress by the user for this reason; Being present in the file that the buffer zone of external devices that the ASIC package terminal in the directory A SIC54 of Figure 14 distributes, is connected with ASIC and electric interfaces defined is read; Be input to order in the logic synthetics according to definition, so, be inserted into test circuits such as the buffer zone of ASIC and scanning between the liner of terminal and the chip that is connected with package terminal of logicor logic core of ASIC and be connected; Then; Input command in the logic synthetics reads the functional block data in the whole catalogues under the directory A SIC52 that has accomplished the synthetic Figure 14 of logic, is filled in the logicor logic core; For programming and distribution design with generating ASIC net table, with entry name output file (S2013 step) in Figure 14 directory A SIC54.

Below the explanation fpga logic synthesizes the handling procedure of interface routine 222.Figure 33 is the process flow diagram of the handling procedure of the synthetic interface routine of expression fpga logic.As shown in the drawing; The synthetic interface routine utilization of this fpga logic is made catalogue by the FPGA numbering of the synthetic interface routine appointment of ASIC logic in the catalogue FPGA55 of Figure 14; To the RTL source in the catalogue of the numbering of the appointment under the catalogue FPGA53 of Figure 14; Read file one by one, come out by user-defined frequency of operation data pick-up in the part of the title of putting down in writing the change resume in the RT source, version number etc., the value that extracts is increased the restriction that the frequency values after 20% synthesizes as logic; Specify out the functional block name of logic synthetic object, carry out synthetic 254 (the S2201 steps) of knowledge of fpga logic of the logic synthetics of FPGA.

If the fpga logic end of synthesis, then fpga logic synthesis program 254 usefulness functional block titles are synthesized the catalogue as the numbering of object that the result outputs to the catalogue FPGA55 that is positioned at Figure 14 to logic.So, the user can utilize the synthetic situation of the logic of following Figure 34 to show an affirmation door utilization rate on one side, Yi Bian carry out design project.And; The synthetic interface routine of fpga logic is inquired subscriber management server 240 and the user mail address that obtains sends in the mail server 260 logic end of synthesis information, FPGA numbering, piece title and with entry name, sends to user's (S2202 step) to mail from mail server 260.

Below, synthetic whether being all over (S2203 step) of logic of the functional block of the FPGA of the numbering of the synthetic interface routine affirmation of fpga logic formation appointment.The method of this affirmation is, releases the functional block title as in the catalogue of the numbering of object of the catalogue FPGA51 of Figure 14, compares with the synthetic functional block name that has finished of above-mentioned logic.If there is not difference; The synthetic interface routine of then following fpga logic is released the filename of the logicor logic core of the FPGA name in the object number catalogue in the catalogue FPGA51 of Figure 14; Utilize the match control documents after this title comes in the catalogue FPGA55 of Figure 14 corresponding, the frequency of operation of numbering as the identical package terminal name of the port name of the fpga logic magnetic core FPGA programming and distribution, that use with match and terminal etc. defined; Whether go up dress and exist, check (S2206 step) by the user.

If exist, then the synthetic interface routine of fpga logic specifies fpga logic magnetic core under the catalogue FPGA51 of the global function piece that constitutes FPGA and Figure 14, that be positioned at the object number catalogue out, carries out fpga logic synthesis program 254.And; If the synthetic result of fpga logic; Then the synthetic interface routine of fpga logic starts fit procedure 255, carries out programming and distribution; The ROM data of circuit information that generated a kind of programming and distribution outcome record as FPGA, output to the FPGA name under the catalogue ROM46 of Figure 14 as in the catalogue of the numbering of object (S2207 step).And the ending message that the ROM data generate, FPGA numbering, entry name and inquiry subscriber management server 240 and the user mail address that obtains sends in the mail server 260 send mail (S2208 step).

If difference is arranged, then in the input and execution picture of following fitting data, judge whether non-selected execution button (S2204 step), if non-selected, then finish; If select; Then for the synthetic repertoire piece of logic not; Under the catalogue FPGA51 of Figure 14 to be positioned at each functional block object number catalogue, the fpga logic magnetic core inner; Be connected to trigger circuit on whole I/O ports, be connected to suitable door to whole trigger circuit output ports of input side, for example on the input port of 2 input NAND; Be connected to whole output of NAND doors on the input port of NAND door of 2 new inputs; As stated; Carry out the multistage connection of 2 input NAND repeatedly; Be connected to the output of 2 input NAND of last level on the input port of whole trigger circuit of outgoing side, describe such HDL and insert, the state (S2205 step) that formation can logic be synthesized.

Form processing identical when not having difference then.Though also depend on the checking strategy when exploitation is started; But through circuit structure research can roughly be divided on the function upwards with downward function block structured situation under; Adopted the patch of above-mentioned trigger circuit etc. through insertion, if upwards the function design is accomplished, even then function design is not downwards not accomplished; Also can verify, help very much the high-level efficiency of verifying.

The below synthetic situation display frame of the logic of explanation Figure 34.This picture; If the logic that the user has selected on the client computer 100 to be positioned at net in the situation display frame of Figure 24 is synthetic; Then net client computer 100 having selected the synthetic incident of logic to deliver in the network server 220; Receive the situation display interface program 224 of data from network server 220, the whole entry names that obtain for inquiring subscriber management server 240 with the user's name of typing, the synthetic result of the logic of the catalogue that is arranged in full numbering from the catalogue FPGA55 of Figure 14 under extracts a scale out.

And; Extract packaging information out among the Plist in the same catalogue of from the fpga logic magnetic core generation of above explanation, making; According to this packaging information; The table inside door macro ratio of selecting at Figure 30 is the encapsulation below 75%, generates the demonstration control data of the synthetic situation display frame of logic of Figure 34, sends in the network server 220.Network server 220 sends to the demonstration control data of the synthetic situation display frame of logic in the net client computer 100, and net client computer 100 demonstrates picture according to the demonstration control data of the synthetic situation display frame of the logic of receiving.

At this, simple declaration door scale 75%.Usually, the fpga logic synthetics according to the synthetic result's of logic door scale, is expressed suitable encapsulation and door utilization rate from the database with logic synthetics.Yet, in the FPGA match, in the arrangements of cells process, in order to improve wiring efficient, realizing that with FPGA the units chunk of logic is used in wiring.So, consider that according to the synthetic result of logic a scale increases, be set at 75% to match back door utilization rate, can not surpass 100%.In FPGA, also have differently, therefore, the logic of FPGA that also can carry out above explanation to each functional block effectively is synthetic.

The input of fitting data below is described and is carried out picture.Figure 35 representes the input of fitting data and carries out an example of picture.If utilize net client computer 100 to select the match in the program picture shown in Figure 180 by the user; Then net client computer 100 having selected match one incident to deliver in the network server 220; Received the match interface routine 223 of data from network server 220; The whole entry names that obtain for utilizing registered user's name to inquire subscriber management server 240; The following whole catalog number names of the catalogue FPGA55 that extracts Figure 14 out, be the FPGA name, generate that fitting data shown in Figure 35 is imported and the demonstration control data of execution picture, send in the network server 220 as the filename of the synthetic result's of the logic in each catalogue net table.

Network server 220 sends to the demonstration control data of the input of fitting data and execution picture in the net client computer 100, and net client computer 100 demonstrates picture according to the input of paid-in fitting data and the demonstration control data of execution picture.If select the condition data input of this picture, then come video data to select picture by net client computer 100.

According to this picture, if select above-mentioned match control documents by the user; Then net client computer 100 and send to the FPGA that selected numbering and match control documents in the network server 220, receive that from network server 220 the match interface routine 223 of data stores the match control documents in the catalogue under the catalogue FPGA55 of Figure 14, object number.

And; If select to carry out button by the user; Then net client computer 100 FPGA numbering, the entry name selected and selected to carry out an incident and delivered in the network server 220; The match interface routine 223 of having received data from network server 220 is entry name, and FPGA numbers as independent variable, carries out the synthetic interface routine of fpga logic.The processing that kind as described above of the synthetic interface routine of fpga logic.

ROM data generating state picture below is described.Figure 36 representes an example of ROM data generating state picture.The user then nets client computer 100 having selected one incident of ROM data to deliver in the network server 220 if select situation shown in Figure 24 to show the ROM data of selecting in the picture with net client computer 100.

Whole entry names that the situation display interface program 224 of data obtains for utilizing registered user's name to inquire subscriber management server 240 have been received in the network server 220; The ROM data name as fitting result of extracting the whole catalog number names under Figure 14 catalogue ROM46 out and being positioned at each catalogue is the FPGA name; Generate the demonstration control data of ROM data generating state picture shown in Figure 36, send in the network server 220.

Network server 220 sends to the demonstration control data of ROM data generating state picture in the net client computer 100, and net client computer 100 is come display frame according to the demonstration control data of paid-in ROM data generating state picture.The user then can download the ROM data if on this picture, select the day part as the FPGA of object.

The below processing of explanation monitor server 290.At first monitor server 290 content of keeping watch on is: RTL has that no change, logic are synthetic, the required time is handled in match, planning and design instrument and according to the change scale of the functional block of deviser's definition, be used in required beyond instrument processing time of instrument design, be time of the necessary handwork of change reflection.

In the catalogue planning 47 of Figure 14 that the instrument deviser manages, each project has the catalogue of entry name, wherein, promotes operation.Having the LAY catalogue of memory utilization design data and the RTL catalogue in storage RTL source in the catalogue of projects name, is identical bibliographic structure below the directory A SIC52 with Figure 14 below the RTL catalogue.

Prison server 290 is kept watch in LAY and the RTL catalogue.Be used to reflect the result's of cumulative time schedule, in the catalogue of entry name, under original state, based on contract set the predetermined day of predetermined day of 1stRTL and Sign Off with the Schedule name storage.So-called 1stRTL is meant can set about planning and design, do not estimate big change at that time, and about 80% RTL has been accomplished in functional verification.So-called Sign Off is meant after the ASIC planning and design are accomplished and makes the day that data are transferred device manufacturer to ASIC.

Figure 37 representes figure predetermined and actual achievement picture day one example.This figure is transformed into picture to schedule file and shows control data, is shown by net client computer 100.That is to say,, then net client computer 100 and selected an actual achievement and a predetermined incident to deliver in the situation display interface program 224 through 220 of network servers if the user selects actual achievement with predetermined in the situation display frame of Figure 24.Received the situation display interface program 224 of selecting an actual achievement and a predetermined thing, be transformed into picture to schedule file and show control data, sent to through network server 220 in the net client computer 100.Received that drawing the net client computer 100 that shows control data shows that according to picture control data comes display frame.

And Figure 38 is the figure of expression by an example of the enactment document of the activity duration of planning and design person's setting.The manual name storage of this document utilization is in the catalogue identical with schedule file.

Monitor server 290 is if reach Looking Out Time, then obtains entry name and file address under user names, the user from subscriber management server 240.Then, read schedule file, extract the predetermined day of 1stRTL out.If should predetermined day in the future, be the execution date that is later than supervision, then do not do any action and finish, if this predetermined day in the past, early than the execution date of keeping watch on, then carry out following processing.

At first, if the RTL catalogue of catalogue under the Catalogue Of Programme of instrument deviser management, that be positioned at entry name does not have RTL source, then Interrupt Process.If the RTL source is arranged, then between the RTL source in the catalogue under the directory A SIC52 of Figure 14,, compare at each piece.

If difference is arranged, then send to the piece title that difference is arranged and entry name and instrument deviser's addresses of items of mail in the mail server 260, send to instrument deviser place by mail server 260.The instrument deviser changes the estimation operation of reflection required time according to this mail.The result of estimation, the instrument deviser upgrades or appends, deletes the time data of schedule file where necessary.

Secondly, extract the piece name that constitutes ASIC the monitor server 290 ASIC logicor logic core under the directory A SIC50 of Figure 14, that the establishment time is up-to-date out, store in the storer.Then, the synthetic result's of logic under the directory A SIC54 of Figure 14, that be arranged in each piece catalogue report file is extracted the synthetic processing time of logic out.There is not report file in the piece name that stores into earlier in the storer, under the situation that promptly logic is not synthesized as yet, is being suitable for the averaging time of the time of from the report file that exists, extracting out, calculating the total ascent time, storing in the storer.

And; Specifically; The planning and design result of catalogue under the catalogue planning 47 of Figure 14 of instrument deviser management, that be arranged in entry name; If there is timing checking result's the file of the final engineering of planning and design engineering, extract the processing time out in the result file that the instrument that then from the total travel of planning and design, uses is exported, calculate the total ascent time according to the time of storing into earlier in the storer.Under the situation that does not have the file of regularly verifying the result, be useful in when signing a contract by planning and design person's predefined time in monitor server of interim estimation.

Below obtain the total that is set in the time in the instructions of this total ascent time and above explanation by monitor server 290, calculate number of days according to 12 hours on the one, schedule file is upgraded in case of necessity.That is to say, under initial state, in schedule file, only set the predetermined day of 1stRTL, to this predetermined day adding the total ascent time, shown in figure 37 as the predetermined day of changing of appending reflection beginning day to the instrument design.

In following supervision; If reflection beginning day is the future that is later than the execution date of supervision; Then compare contrast to playing the number of days that ends predetermined day that is set at reflection beginning day from predetermined day of the previous 1stRTL of reflection beginning day; If be longer than the number of days of the instrument design that calculates, then do not upgrade reflection beginning day.In the time of before reflection beginning day is the execution date of keeping watch on; Monitor server 290 sends in the mail server 260 user and instrument deviser's addresses of items of mail with as the information that reflects the beginning chance, sends mail from mail server 260 to user and instrument deviser.At this moment monitor server 290, in the time of before the date that up-to-date reflection begins to carry out for supervision day, if in a few days do not have the date in the actual achievement of reacting beginning day, then do not upgrade schedule file.

At the mail that the conduct reflection is begun the information of chance; When user and instrument deviser both sides deliver to monitor server 290 to the mail of agreeing or refuse; If both sides all agree, the reflection that then is set at schedule file to the date that gets the mail immediately begins a day actual achievement day, in the supervision of next time; If up-to-date reflection predetermined day was to keep watch on before the date of implementing; Reflecting that predetermined purpose actual achievement in a few days has the date,, increase reflection beginning day newly then according to the number of days of actual achievement day computational tool design.If proceed this processing, then reflection beginning day is near Sign Off day.

Calculate the predetermined day of reflection beginning day; Surpassing under the Sign Off purpose situation; Monitor server 290 to can not setting information and user and instrument deviser's the addresses of items of mail of predetermined day date of reflection beginning and send in the mail server 260, sends mail from mail server 260 to both sides.

Under situation about being refused by the user as the information mail of reflection beginning chance; The user sent to mail server 260 in from net client computer 100 be intended to set the information of being scheduled to day and user and instrument deviser's addresses of items of mail, send mail to both sides from mail server 260.

Below explanation is scheduled to and the actual achievement picture.Figure 37 is that the figure routine with of the actual achievement picture is scheduled in expression.The logic Fix button of this figure was arranged in before the supervision execution date of monitor server 290 with the change button, and up-to-date reflection begins the next door of day.If the user specifies the date on the date setting hurdle that is positioned at this button under; Select the change button; Then netting client computer 100 delivers to date of having selected to set and change one incident in the network server 220; From network server 220, received the situation display interface program 224 of data; Begin the up-to-date reflection in the schedule file day to change to date of appointment, send to the information of the meaning of having changed and user and instrument deviser's addresses of items of mail in the mail server 260, send mail to both sides from mail server 260.

Under the selecteed together situation of logic Fix button in Figure 37 and the appointment of date, situation display interface program 224 is being carried out and change button when being selected after the identical processing, the processing that the supervision of monitor server 290 is stopped.So, can make with clearly defined objective between user and instrument deviser both sides' short-term, the tentative number of times of instrument design is many more; Predetermined day probability of change beginning day is high more, to this, and user and the instrument deviser both sides row method of all having an opportunity to take into account; As a result, go far towards to raise the efficiency.

As stated, in the 2nd embodiment,, carry out the ASIC logic by ASIC logic synthesis program 253 and synthesize according to customer requirements from net client computer 100; Carrying out fpga logic by fpga logic synthesis program 254 synthesizes; The synthetic result of logic who on net client computer 100, shows ASIC and FPGA by the synthetic interface routine 222 of logic; Mail server 260 usefulness Emails are to synthetic beginning of the logic of user notification ASIC and FPGA and result; So the user needn't be provided with the synthetic full-time staff of logic, whenever can both carry out logic and synthesize, can, the full-time staff make the synthetic quality of logic even as accomplishing; Simultaneously can be through synthetic beginning of Email RL and result's notice, needn't be termly confirm that with computing machine logic synthesizes situation.

And; In the 2nd embodiment; According to customer requirements from net client computer 100, generate the net table that only constitutes of user's appointment by ASIC logicor logic core generator program 251 from the functional block that constitutes ASIC by the link information between the port of a plurality of functional blocks, fpga logic magnetic core generator program 252 is filled up to the synthetic object piece ability blocks of data of logic in the net table that has generated; Generate a kind of ROM data that write down the PLD circuit; Logicor logic core generates interface routine 221 and shows the generation result of the ROM data that generate on computers, notifies the user by mail server 260 usefulness Emails simultaneously, so; The user does not need the special-purpose development environment of PLD, can reduce the ROM data of record PLD circuit and work out required load, time and cost.

And; In the 2nd embodiment, do not accomplish, under the non-existent situation of circuit data, generate the net table by fpga logic magnetic core generator program 252 in the design of the ASIC of user's appointment structure function piece; This net table is to be inserted into the circuit that adopts interim trigger circuit etc. on the input terminal and lead-out terminal of this functional block; So, in the authentication of the model machine that adopts PLD, even be not the design completion as yet of the functional block of checked object; Also can verify by enough model machines, can improve verification efficiency.

And; In the 2nd embodiment; The change scale that up-to-date circuit data that 290 couples of users of monitor server have and instrument deviser carry out between the instrument designed circuit data is kept watch on, and according to keeping watch on time on date one that result and required time of planning and design draws picture then, sends notice with E-mail mode to the instrument deviser of user and ASIC by mail server 260; Explanation is reflected to change that time is up in the ASIC instrument design; Requirement stops, so that according to this notice, is changed the date of reflection by the user.So, can be reflected to the change that takes place in the ASIC planning and design expeditiously, simultaneously, set the time of reflection change, therefore can judge the user and when can change, can change schedule in early days.

That kind as described above if adopt the present invention, then can obtain following effect.

If adopt the invention of the disclosed program memory medium of the 1st embodiment; Then efficient is to utilize a kind of program to make computing machine carry out the method for formation logic magnetic core of the invention of the 1st embodiment; If adopt the medium of having stored this program; Can in lsi development, guarantee quality as the piece port specification of RTL design input in advance; Even in the exploitation in many designs of functional block source also many large scale integrated circuits, also can confirm the connection of interblock in advance, thereby can guarantee necessarily to assemble chip.

If adopt the invention of the development approach of the disclosed integrated circuit of the 1st embodiment; From the ASIC logicor logic core, cut out under the state that then logicor logic core of PLD connects between maintainance block; So; If adopt the checking of the PLD of this logicor logic core, then can in ASIC, can avoid the repetition of the checking of same formation at least.Therefore, concurrent development ASIC and PLD expeditiously.

And; When inserting inputoutput buffer; Terminal information according to chip generates interim logicor logic core; The alternative of the logicor logic core that utilization generates from piece, can cross-check by the port information of the chip of piece definition and the terminal information of chip, can guarantee the port specification of piece and the quality of chip terminal specification.

If adopt the invention of the disclosed program memory medium of the 1st embodiment, then can generate by the port of the piece of random scale, number and the net table that link information constituted of port.

If adopt the invention of the disclosed program memory medium of the 1st embodiment, then can generate by the port of the piece of random scale, number and the net table that link information constituted of port and generate chip net table.

If adopt the invention of the development approach of the disclosed integrated circuit of the 1st embodiment; If used stored program medium; Its program can make the logic synthetics carry out the method for the logicor logic core that generates PLD; Debugging efficiency such as logic checking reduced when the user name that so, can prevent to be difficult to judge port function became the port title.

As stated; According to design document data formation logic magnetic core; From this logicor logic core under the state that keeps hierarchical structure and link information for PLD with regenerating logicor logic core; So can the common circuit structure, insert circuit data, carried out the circuit data that does not exist with ... device technology and the net between the instance in the instance of functional verification; Under the situation of ASICization, can avoid verifying again, also can avoid owing to the difference between ASIC and the PLD design once more.

Like this,, then can provide a kind of can implementation structure shared, avoid designing again and the development approach of the integrated circuit of checking and the programmable medium of having stored the development approach of integrated circuit more as far as possible if adopt the present invention.

And, if adopt the present invention, then constitute the functional block of ASIC according to link information between port, generate by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

Work out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and use the logic generated data with logic generated data and PLD;

Be filled into by above-mentioned net table with the logic generated data about the PLD of the functional block of combinations thereof and generate in the net table that operation generates, generate the real machine evaluation of having write down the PLD circuit and use the ROM data;

Utilize the ASIC that has worked out to use the logic generated data, the planning chart of ASIC is drawn with regularly checking and real machine evaluation are carried out with the generation of ROM data simultaneously;

The circuit data that utilization is undertaken by the data based real machine evaluation result of above-mentioned ROM is changed, in being reflected in the making of above-mentioned ASIC programming and distribution figure and regularly verifying.

So its effect is: concurrent development ASIC and PLD expeditiously, can shorten time construction cycle of ASIC.

And, if adopt the present invention, then constitute the functional block of ASIC according to link information between port, generate by the net table that link information constituted between the port of the functional block of this combination and port, as the logicor logic core of PLD;

Work out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and use the logic generated data with logic generated data and PLD;

Be filled into by above-mentioned net table with the logic generated data about the PLD of the functional block of combinations thereof and generate in the net table that operation generates, generate the real machine evaluation of having write down the PLD circuit and use the ROM data;

Utilize the ASIC that has worked out to use the logic generated data, the planning chart of ASIC is drawn with regularly checking and real machine evaluation are carried out with the generation of ROM data simultaneously;

So its effect is: concurrent development ASIC and PLD expeditiously, can shorten time construction cycle of ASIC.

And; If adopt the present invention; It is synthetic then to carry out the logic of ASIC according to customer requirements, the speed ability whether synthetic result of the ASIC logic of carrying out can satisfy customer requirements is judged, according to judged result; The logic of carrying out PLD is synthetic; The logic of carrying out result and PLD synthetic the carry out result synthetic the ASIC logic is shown on the computing machine, and the ASIC logic is synthetic begins and beginning of carrying out that the logic of result and PLD synthesizes and carry out the result, notifies the user with E-mail mode.So its effect is:

The user needn't be provided with the synthetic full-time staff of logic; It is synthetic whenever can both to carry out logic; Can, the full-time staff make the synthetic quality of logic even as accomplishing; Simultaneously can be through synthetic beginning of Email RL and result's notice, needn't be termly confirm that with computing machine logic synthesizes situation.

And, if adopt the present invention, then because according to customer requirements; Generate by the link information between the port of a plurality of functional blocks of user's appointment and the net table that constitutes by the functional block that constitutes ASIC; The object piece synthetic logic can be filled up in the net table that has generated by blocks of data, generates a kind of ROM data that write down the PLD circuit, the generation result of the ROM data of generation demonstration on computers; Notify the user with Email simultaneously; So the user does not need the special-purpose development environment of PLD, can reduce the ROM data of record PLD circuit and work out required load, time and cost.

And, if adopt the present invention, then because do not accomplish in the design of the ASIC of user's appointment structure function piece; Under the non-existent situation of circuit data, generate the net table, this net table is to be inserted into the circuit that adopts interim trigger circuit etc. on the input terminal and lead-out terminal of this functional block; So, in the authentication of the model machine that adopts PLD, even be not the design completion as yet of the functional block of checked object; Also can verify by enough model machines, can improve verification efficiency.

And, if adopt the present invention, then because the change scale that up-to-date circuit data that the user is had and instrument deviser carry out between the instrument designed circuit data keep watch on; According to keeping watch on time on date one that result and required time of planning and design draws picture then; E-mail mode is sent notice to the instrument deviser of user and ASIC, explains to be reflected to change that time is up in the ASIC instrument design, requires to stop; So that according to this notice, change the date of reflection by the user.So, can be reflected to the change that takes place in the ASIC planning and design expeditiously, simultaneously, set the time of reflection change, therefore can judge the user and when can change, can change schedule in early days.

If adopt the present invention; Then on the one hand; The 1st layout of describing according to all or part of the terminal information of FPGA of functional block that comprises a plurality of functional blocks and the 2nd layout of describing as the described terminal information identical of subordinate's layer of the 1st layout with this FPGA; Generate between the same terminal in the 1st layout, the 2nd layout and connect; And the FPGA that between this terminal, has inserted the FPGA corresponding buffer region uses layout information; On the other hand; The 3rd layout of describing according to the terminal information of the ASIC that comprises a plurality of functional blocks and the 4th layout of describing as the described terminal information identical with this ASIC of subordinate's layer of the 3rd layout generate between the same terminal between the 3rd layout, the 4th layout and connect, and the ASIC that between this terminal, has inserted the ASIC corresponding buffer region uses layout information.Above-mentioned the 2nd layout, the 4th layout are replaced as the circuit information that the link information according to the included functional block of each layout generates respectively, so, generate the net table of FPGA and ASIC.

So its effect is: concurrent development ASIC and PLD expeditiously, can shorten time construction cycle of ASIC.

As stated; The development approach and the program memory medium of the development approach of having stored integrated circuit and parallel development system, development sequence and the development approach of ASIC and PLD that relate to integrated circuit of the present invention; Be applicable to the exploitation of integrated circuit, be particularly useful for the exploitation of ASIC and PLD.

Claims (4)

1. the concurrent development method of ASIC and PLD is characterized in that, comprising:

The net table generates step; According to link information between port the functional block that constitutes ASIC is divided into groups; As the logicor logic core of PLD, generate the net table that constitutes by link information between the port of the functional block after this groupings and port, this net table generation step comprises:

First step: the device that utilizes any piece of from the logicor logic core of the ASIC that only is made up of the link information of the port of piece and port, selecting to have annexation to divide into groups, generation are only by the logicor logic core of the link information hardware description language form that constitute, that the logic synthetics can read of the port of the piece of random scale, number and port;

Second step: the terminal information according to chip is made layout with the logic synthetics on interim chip, on this layout, terminal takes place;

Third step: the layout identical with above-mentioned second step takes place as the unit in the layout inside processing;

The 4th step: the port that connects the same title between layout and the unit;

The 5th step: the net between the port that has connected is inserted the inputoutput buffer that exists with ... device technology;

The 6th step: logicor logic core and unit to making at above-mentioned first step are replaced, and launch the stratum as the layout of top layer, generate the net table;

The logic synthesis step is worked out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and is used the logic generated data with logic generated data and PLD;

The ROM data generate step, the PLD of the functional block after the relevant above-mentioned grouping is inserted through above-mentioned net table with the logic generated data generate in the net table of step generation, and the ROM data are used in the real machine evaluation of the circuit of generation record PLD;

Lay establishment step, the ASIC that utilization is worked out through above-mentioned logic synthesis step uses the logic generated data, verifies with timing with the laying establishment of carrying out ASIC mutually concurrently with the ROM data through the evaluation of above-mentioned ROM data generation step generation real machine;

Difference reflection step, reflection is to based on having utilized the change of circuit data of real machine evaluation result that generates the ROM data of step generation through above-mentioned ROM data in the laying establishment of above-mentioned ASIC and checking regularly.

2. the concurrent development method of ASIC as claimed in claim 1 and PLD; It is characterized in that: above-mentioned laying establishment step is before above-mentioned ROM data generate step or begin simultaneously with it, above-mentioned difference reflection step the laying establishment of ASIC with regularly be reflected in the change of carrying out after above-mentioned laying establishment step begins in the checking to the foregoing circuit data.

3. according to claim 1 or claim 2 ASIC and the concurrent development method of PLD; It is characterized in that: above-mentioned ROM data generate step to not being compiled into the functional block of PLD with the logic generated data through above-mentioned logic synthesis step in the functional block after the above-mentioned grouping; The PLD that will in input terminal and lead-out terminal, insert mute circuit is filled into through above-mentioned net table with the logic generated data and generates in the net table of step generation, and the ROM data are used in the real machine evaluation that generates the circuit that has write down PLD.

4. the parallel development system of ASIC and PLD is characterized in that comprising with lower device:

The net table creating device; It divides into groups to the functional block that constitutes ASIC according to link information between port; As the logicor logic core of PLD, generate the net table that constitutes by link information between the port of the functional block after this groupings and port, this net table creating device execution:

First step: the device that utilizes any piece of from the logicor logic core of the ASIC that only is made up of the link information of the port of piece and port, selecting to have annexation to divide into groups, generation are only by the logicor logic core of the link information hardware description language form that constitute, that the logic synthetics can read of the port of the piece of random scale, number and port;

Second step: the terminal information according to chip is made layout with the logic synthetics on interim chip, on this layout, terminal takes place;

Third step: the layout identical with above-mentioned second step takes place as the unit in the layout inside processing;

The 4th step: the port that connects the same title between layout and the unit;

The 5th step: the net between the port that has connected is inserted the inputoutput buffer that exists with ... device technology;

The 6th step: logicor logic core and unit to making at above-mentioned first step are replaced, and launch the stratum as the layout of top layer, generate the net table;

The logic synthesizer, it is worked out ASIC according to the circuit data of the functional block that constitutes above-mentioned ASIC and uses the logic generated data with logic generated data and PLD;

The ROM data generating device; The PLD of the functional block after the relevant above-mentioned grouping is filled in the net table that is generated by above-mentioned net table creating device with the logic generated data, and the ROM data are used in the real machine evaluation that generates the circuit that has write down PLD;

Lay scheduling apparatus, utilize the ASIC that works out by above-mentioned logic synthesizer to use the logic generated data, with the laying establishment and regularly checking of carrying out ASIC by the evaluation of above-mentioned ROM data generating device generation real machine with the ROM data mutually concurrently.

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