CN101127528A - Electronic device applicable to current source matrix and its layout method - Google Patents
Electronic device applicable to current source matrix and its layout method Download PDFInfo
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- CN101127528A CN101127528A CNA2006101114132A CN200610111413A CN101127528A CN 101127528 A CN101127528 A CN 101127528A CN A2006101114132 A CNA2006101114132 A CN A2006101114132A CN 200610111413 A CN200610111413 A CN 200610111413A CN 101127528 A CN101127528 A CN 101127528A
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Abstract
The utility model relates to an electronic device suitable for the current source matrix and the layout method, comprising a low byte and a plurality of high bytes, wherein the low byte has a plurality of current source units which are arranged on a center area of a layout area; moreover, each high byte has a plurality of current source units which are respectively arranged on a plurality of peripheral area of the layout area.
Description
Technical field
The invention relates to a kind of electronic installation and its layout method, and particularly about a kind of current source matrix and its layout method that is applicable to current source matrix.
Background technology
Current type numerical digit analogy converter (hereinafter to be referred as the numerical digit analogy converter) is made up of a plurality of current source cell usually, and its conversion bit is high more, and the quantity of required current source cell is also just many more.Therefore, very complicated usually on layout, especially metal connecting line (metal) layout between the current source cell is complicated especially.So in conventional art, the lower numerical digit analogy converter of conversion bit is usually with the arrangement mode layout of matrix form.With the corresponding current sources unit, vertical in regular turn or transversely arranged, the complexity of simplified topology.Yet, when the quantity of current source cell improves, the distance of respective current source unit on wafer strengthens, it is bigger that its characteristic also differs, cause the linearity variation of numerical digit analogy converter easily, i.e. DNL (differential nonlinearity) and INL (integralnonlinearity) variation.
Fig. 1 is the Organization Chart according to the current type numerical digit analogy converter of conventional art.Figure 1 shows that the numerical digit analogy converter of 8 bits, this numerical digit analogy converter can be exported an analogy electric current according to the numerical digit signal of input.Two bit transitions devices 140 are converted to control signal SL01～SL15 to bit driver 150 according to the numerical value of the preceding 4 bits D0～D3 representative of numerical digit signal.150 of bit drivers produce current controling signal SDL01～SDL15, SDL01N～SDL15N according to control signal SL01～SL15, control the output current of low level elementary current source unit 160.And comprise among the low level elementary current source unit 160 and decide it whether to export according to control signal SDL01～SDL15 and SDL01N～SDL15N by 15 groups current source cell respectively.15 groups of current source cells in the low level elementary current source unit 160 can be referred to as the low level tuple.
The electric current of 4 bit D4～D7 output converting structure is then similar with above-mentioned preceding 4 bits behind the numerical digit signal, and main difference is that high-order elementary current source unit 130 comprises 15 groups of high-order tuples, these 15 groups high-order tuples then corresponding to after the numerical value of 4 bit D4～D7.Wherein, each is organized high-order tuple and has 16 current source cells.Therefore, the highest electric current output that equals 16 times of low level elementary current source units 160 of the output current of high-order elementary current source unit 130.In other words, just have 240 current source cells.Therefore, suitable complexity and layout area are bigger on layout, make the linearity decline of numerical digit analogy converter easily because of the processing procedure difference (processvariation) and the influence of Temperature Distribution (temperature distribution).
Fig. 2 is the circuit diagram according to the low level elementary current source unit of conventional art.Below explanation please be simultaneously with reference to shown in Figure 1, and low level elementary current source unit 160 can be made up of 201～215 of 15 current source cells, current source cell 201～215 can be referred to as a low level tuple.Current source cell 201～215 decides the path of its electric current output according to current controling signal SDL01～SDL15, SDL01N～SDL15N.Therefore, on layout, need 15 groups of repeated configuration independently connecting line control the output of respective current source unit 201～215.High-order elementary current source unit 130 then has 240 current source cells, is a high-order tuple with per 16 current source cells, and then high-order elementary current source unit can have 15 groups of high-order tuples.The output of above-mentioned 15 groups of high-order tuples is then corresponding to current controling signal SDH01～SDH15, SDH01N～SDH15N.Merge high-order elementary current source unit 130 and export with the electric current of low level elementary current source unit 160, then can be corresponding to the numerical digit signal of 8 bits.
Below explanation please be simultaneously with reference to Fig. 1,2.Fig. 3 is the layout according to the current source matrix of the current type numerical digit analogy converter of conventional art.Zone T1,16～T16,16 in order to configuration low level tuple (comprise current source cell L1～L15), regional T1,1～T16,1 in order to disposing high-order tuple M1, regional T1,2～T16,2 form high-order tuple M2, and the rest may be inferred, amount to 15 groups of high-order tuple M1～M15.The low level tuple (comprises that current source cell L1～L15) forms low level elementary current source unit 160, high-orderly then forms high-order elementary current source unit 130 in set of currents M1～M15.
On layout, as shown in Figure 3, (current source cell that comprises current source cell L1～L15) comprised is arranged in vertical mode, though this kind arrangement mode layout complexity is low, does not consider the influence for circuit of processing procedure difference and Temperature Distribution for high-order tuple M1～M15 and low level tuple.Only can be applicable to the layout of the numerical digit analogy converter circuit of low bit.
Fig. 4 is for (please refer to U.S. Patent number: US6954164 B2) according to the layout of the electric crystal array of conventional art.(comprise that current source cell L1～L15) is distributed on the diagonal in four quadrants of wafer, the distance of its integral body is far away for low level tuple in this layout type.Therefore, (it is bigger to comprise that other current source cell is produced among the current source cell L1～L15) electric current is subjected to the influence of processing procedure difference, and when hang down bit and being worth conversion, the linearity of its conversion is relatively poor, and its layout complexity comparatively for the low level tuple.
Fig. 5 is for (please refer to U.S. Patent number: 6157333) according to the layout of the electric crystal array of the numerical digit analogy converter of conventional art.Though the restricted path difference of this kind layout type is different lower with the Temperature Distribution influence, its element quite disperses.Therefore, the layout type of Fig. 5 is more complicated.Particularly the layout aspect of connecting line needs more complicated layout type or uses more multi-layered metal wire, significantly increases the degree of difficulty of configuration.
Comprehensively above-mentioned, though can utilize complicated layout type to reduce processing procedure difference and the influence of Temperature Distribution to the numerical digit analogy converter in the conventional art, its layout is complexity quite.
Summary of the invention
Purpose of the present invention one of them for a kind of electronic installation is provided, utilize the adjustment of layout type, reduce the influence of processing procedure difference and Temperature Distribution to electronic installation.Above-mentioned electronic installation can be a current source matrix.
Purpose of the present invention one of them for a kind of layout method of electronic installation is provided, electronic installation is divided into first layout and second layout units, be disposed at the central area and the outer peripheral areas of layout areas respectively, reduce the influence of processing procedure difference and Temperature Distribution by this electronic installation.
Purpose of the present invention one of them for provide a kind of on wafer the method for a plurality of electronic installations of layout.According to each zone of wafer, define suitable layout reference line.Electronic installation on each zone, according to pairing layout reference line, the arrangement angles when adjusting the electronic installation layout is to reduce the influence to electronic installation of processing procedure difference and Temperature Distribution.
Purpose of the present invention one of them for a kind of electronic installation is provided, according to the layout areas that electronic installation disposed and the relative position of wafer, adjust the arrangement angles of electronic installation, to reduce the influence of processing procedure difference and Temperature Distribution to electronic installation.
Purpose of the present invention one of them for a kind of layout method of electronic installation is provided, according to the layout areas at electronic installation place and the relative position of wafer, the element of balanced configuration electronic installation is to reduce the influence to electronic installation of processing procedure difference and Temperature Distribution.
Purpose of the present invention one of them for a kind of electronic installation is provided, be applicable to the current source matrix of a current type numerical digit analogy converter.Current source matrix is divided into low level tuple and high-order tuple, and the low level tuple is disposed at the middle position of layout areas, is symmetrical centre with the current source cell in the high-order tuple with the layout areas central point, be disposed at respectively in the peripheral block of layout areas, use the influence of reduction processing procedure difference and Temperature Distribution numerical digit analogy converter transfer characteristic.
For reaching above-mentioned and other purposes, the present invention proposes a kind of electronic installation, and this electronic installation comprises first layout units and most second layout units.First layout units is disposed at the center block of layout areas.And most second layout units then are disposed at a plurality of peripheral block of layout areas respectively.
In another embodiment of the present invention, above-mentioned electronic installation is a current source matrix, and this current source matrix comprises low level tuple and a plurality of high-order tuple.The low level tuple has a plurality of current source cells, is disposed at the center block of layout areas, and above-mentioned center block is positioned at the middle position of layout areas.Layout areas more comprises a plurality of peripheral blocks, be positioned at the center block around, in order to dispose the current source cell of above-mentioned high-order tuple.
For reaching above-mentioned and other purposes, the present invention proposes a kind of layout method of electronic installation, and this electronic installation is to comprise first layout units and a plurality of second layout units.Above-mentioned first layout units and second layout units have a plurality of elements respectively, and this layout method comprises the following steps: at first, first layout units is disposed at the center block of layout areas.Then, the element of above-mentioned each second layout units is disposed at a plurality of peripheral block of layout areas respectively.
For reaching above-mentioned and other purposes, the present invention propose a kind of on wafer the method for a plurality of electronic installations of layout, comprise the following steps: at first, central point with wafer is a benchmark, wafer area is divided into N configuring area, and be positioned at the position of this wafer according to above-mentioned configuring area, in each configuring area, define at least one layout reference line.Then, electronic installation is disposed in the configuration block, and the electronic installation in each configuring area, be layout reference line according to configuring area, adjust the arrangement angles of electronic installation.
For reaching above-mentioned and other purposes, the present invention proposes a kind of electronic installation, is disposed at a layout areas, and this layout areas is divided into first area and second area.Above-mentioned electronic installation comprises one first layout units and most second layout units.Above-mentioned first layout units has at least one element, is disposed at the first area.Above-mentioned second layout units is disposed at second area, and wherein each second layout units has at least one element.Wherein, layout areas has a datum line, the rough center of datum line by above-mentioned layout areas, and the first area has a long axis parallel with this datum line, and this first area comprises the center of layout areas.
For reaching above-mentioned and other purposes, the present invention proposes a kind of layout method of electronic installation.Above-mentioned electronic installation is to comprise first layout units and a plurality of second layout units, and above-mentioned first layout units has a plurality of first elements, and each second layout units has a plurality of second elements.Above-mentioned layout method comprises the following steps: at first, and according to the first area of the datum line decision layout areas of layout areas, wherein the first area comprises the center of layout areas.First layout units is disposed at the first area.Next, second layout units is disposed at other zones of layout areas.
Comprehensively above-mentioned, the present invention is divided into first layout units and second layout units with electronic installation, and to be symmetrical in the mode at layout areas center, disposes first layout units and second layout units respectively.If when being disposed at electronic installation on the wafer,, adjust its layout angle then according to the zone that electronic installation disposed.Above-mentioned electronic installation can be a current source matrix, the current source cell of the low bit of its first layout units representative, its second layout units is represented the current source cell of high bit, and when configuration, the current source cell of lower bit then is disposed at the position at more close layout areas center.
Therefore,, not only can reduce processing procedure difference and Temperature Distribution influence and reduction layout complexity, more can reduce the layout complexity of current source matrix the numerical digit analogy converter if when applying the present invention to the current source matrix of numerical digit analogy converter.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment of the present invention cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the Organization Chart according to the current type numerical digit analogy converter of conventional art.
Fig. 2 is the circuit diagram of the low level elementary current source unit of conventional art.
Fig. 3 is the layout according to the current source matrix of the current type numerical digit analogy converter of conventional art.
Fig. 4 is the layout type of United States Patent (USP) (US6954164 B2).
Fig. 5 is the layout type of United States Patent (USP) (6157333).
Fig. 6 is the schematic layout pattern according to the current source matrix of a preferred embodiment of the present invention.
Fig. 7 is the schematic layout pattern of the current source matrix of another preferred embodiment according to the present invention.
Fig. 8 is wafer layout configurations figure according to another embodiment of the present invention.
D0～D7:8 bit numerical digit signal
SL01～SL15: control signal
SDL01～SDL15, SDL01N～SDL15N: current controling signal
SDH01～SDH15, SDH01N～SDH15N: current controling signal
T1,1～T16,16: layout areas
M1～M15: high-order tuple
L1～L15: the current source cell of low level tuple
M1,16～M15,16: the current source cell of high-order tuple
C: the central point D of layout areas: emulation element
ZD: datum line
CD1～CD4: layout reference line
110,140: two bit transitions devices
120,150: the bit driver
130: high-order elementary current source unit
160: low level elementary current source unit
201～215: current source cell
600,700: layout areas
Z610～Z640: peripheral block
Z650: center block
S611～S641: sub-block
Z710: first area
S711, S712, S713, S714: sub-block
800: wafer
800C: the central point of wafer
810～840: configuring area
Embodiment
See also shown in Figure 6ly, be the schematic layout pattern of the electronic installation of preferred embodiment according to the present invention.The electronic installation of present embodiment is a current source matrix, can be applicable to a numerical digit analogy converter, in the present embodiment, is illustrated with the numerical digit analogy converter of 5 bits.
This numerical digit analogy converter can be according to a numerical digit signal, to export an analogy electric current.Wherein, the current value that one low level tuple of this numerical digit analogy converter is exported is corresponding to (the Least Significant Bits of least significant bit unit of numerical digit signal, be called for short LSB), and the electric current that a high-order tuple of numerical digit analogy converter is exported is corresponding to the highest significant position unit (Most SignificantBits is called for short MSB) of above-mentioned numerical digit signal.In the present embodiment, LSB represents preceding 2 bits of numerical digit signal, and MSB represents back 3 bits of numerical digit signal.
As shown in Figure 6, the current source matrix of present embodiment is to be disposed at a layout areas 600, and this layout areas 600 is to comprise center block Z650 and a plurality of peripheral block, in the present embodiment then with four peripheral block Z610～Z640 be example as an illustration.Wherein, current source matrix is to comprise a low level tuple and a plurality of high-order tuple.In the present embodiment, the low level tuple is first layout units, and high-order tuple then is second layout units.First layout units is disposed at the center block Z650 of layout areas 600, and second layout units then is disposed at the peripheral block Z610～Z640 of layout areas 600 respectively.
Center block Z650 is positioned on the middle position of layout areas 600, and in order to configuration low level tuple, this low level tuple is to comprise a plurality of current source cell L1～L3, and it is that central point according to layout areas 600 is symmetrical distribution.Above-mentioned each current source cell is all a current source circuit.In the present embodiment, the low level tuple is responsible for the conversion of the least significant bit unit of 2 bits in the above-mentioned numerical digit signal.Therefore, current source cell L1～L3 can correspond respectively to the numerical value (for example current source cell L1 is corresponding to 01) of the least significant bit unit of the numerical digit signal of importing.Aspect configuration, the corresponding numerical value little current source cell (as L1, the promptly low bit of meaning) of healing, configurable in zone more near the central point C of layout areas 600, and in the mode corresponding to central point C, configuration from inside to outside.
In addition, if the center block Z650 of layout areas 600 comprises the untapped residual area of low level tuple, then dispose a simulation unit (dummy cell) D in residual area, to fill up the remaining area of center block Z650.Utilize above-mentioned configuration mode, not only can simplify the layout of low level tuple.And,, can reduce the influence of processing procedure difference and Temperature Distribution for the numerical digit analogy converter so its element characteristic is also close because of the allocation position of current source cell L1～L3 is close.
In the present embodiment, the low level tuple is an example with 3 current source cells only, and technological means of the present invention is described, but is not disposed at the current source cell number of central area Z650 with above-mentioned restriction the present invention.In addition, configuration mode of the present invention is not limited to the configuration mode of above-mentioned current source cell L1～L3, only needs that the low level tuple is disposed at the central area and gets final product.Have in the present technique field and to know the knowledgeable usually, should know configuration modes that all the other are suitable for easily by inference, do not add tired stating at this via exposure of the present invention.
In addition, the high-order tuple M1～M7 of present embodiment is responsible for the conversion of the highest significant position unit of 3 bits in the above-mentioned numerical digit signal.High-order tuple M1～M7 is corresponding to the numerical value of the highest significant position unit of 3 bits in the above-mentioned numerical digit signal.Wherein, each high-order tuple M1～M7 all is made up of a plurality of current source cell, and in present embodiment, each high-order tuple M1～M7 all has 4 current source cells.In other words, then represent the numerical value of highest significant position unit with the least significant bit unit of the numerical digit signal of being imported with the magnitude of current.The current value that the low level tuple is exported is corresponding to the least significant bit unit of numerical digit signal, and the current value that high-order tuple is exported is corresponding to the highest significant position unit of numerical digit signal.
In the configuration of high-order tuple,, be disposed at peripheral block Z610～Z640 in the mode that is symmetrical in central point C respectively with each high-order tuple M1～M7 quadrisection.As shown in Figure 6, be example with high-order tuple M1, being divided into is four parts, is disposed at respectively among sub-block S611～S641 of peripheral block Z610～Z640, wherein each sub-block S611～S641 disposes the current source cell of high-order tuple M1 respectively.And the position of sub-block S611～S641 is symmetrical in central point C.The configuration mode of all the other high-order tuple M2～M7 is analogized, and please refer to shown in Figure 6ly, does not add tired stating at this.
In addition, a plurality of emulation element D more can be set, so that the element characteristic of current source cell behind processing procedure can be more consistent among high-order tuple M1～M7 in the periphery of high-order tuple M1～M7.In the present embodiment, emulation element D can be consistent with the circuit framework of current source cell.Above-mentioned low level tuple and each current source cell of high-order tuple all comprise a current source circuit, and its current source circuit can be with reference to the explanation of Fig. 2, and certainly, the current source cell of low level tuple and high-order tuple can be identical or different current source circuit.
Certainly, the present invention also is not limited to the circuit of Fig. 2 current source circuit as present embodiment, has in the present technique field and knows the knowledgeable usually, via exposure of the present invention, should know current source circuits that all the other are suitable for easily by inference, does not add tired stating at this.
In the present embodiment, the configuration mode of high-order tuple M1～M7, only need consider that (selected sub-block need lay respectively at four peripheral block Z610～Z640 for the position of the pairing sub-block of other high-order tuple, and be symmetrical in central point C) get final product, need not consider high-order tuple M1～M15 relativeness to each other.Because high-order tuple M1～M7 all on average is disposed at four peripheral blocks, so the mean value of the element characteristic of each high-order tuple M1～M7 should be similar, its output current also should be similar.So, just, can reduce the influence of processing procedure difference and Temperature Distribution to circuit output.
Fig. 6 only is one embodiment of the invention, and configuration mode of the present invention does not exceed with Fig. 6.Wherein, high-order tuple M1～M7 is the interchangeable position also, can reduce processing procedure difference and Effect on Temperature Distribution equally.Have in the present technique field and to know the knowledgeable usually,, should know all the other feasible configuration modes easily by inference, do not add tired stating at this via exposure of the present invention.
In addition, in the present embodiment, because of high-order tuple M1～M7 all is divided into tetrameric current source cell, so it is all identical to form the unit of high-order tuple M1～M7,4 current source cells just.On layout, can utilize the layout type of hierarchy type framework (hierarchy), increase the convenience and the efficient of layout, and reduce the complexity of connecting line.
Though present embodiment only with the least significant bit units of the highest significant position of 3 bits unit and 2 bits be example as an illustration, so do not limit technological means of the present invention with this.Technological means of the present invention also is applicable to the current source matrix of different bits (as 10 bits).And do not limit layout type of the present invention,, all can use technological means of the present invention, reduce the influence of processing procedure difference and Temperature Distribution circuit output as long as layout areas has the central point of symmetry with foursquare layout type.
In addition, technological means of the present invention also is not limited to the layout of a plurality of current source cells, also have matrix form framework (for example a plurality of repeat element applicable to all the other, the voltage source matrix) circuit layout only needs to get final product desiring the circuit matrix of layout or the current source matrix in the element matrix replacement present embodiment.Have in the present technique field and to know the knowledgeable usually, should know remaining application mode of the present invention easily by inference, do not add tired stating at this via exposure of the present invention.
Fig. 7 is the layout of the electronic installation of another preferred embodiment according to the present invention.Electronic installation is to comprise one first layout units and a plurality of second layout units.First layout units has at least one element, and is disposed at first area Z710.Second layout units is to be disposed at second area, and wherein each second layout units has at least one element.
Equally with the current source matrix of the numerical digit analogy converter that is applied to 5 bits, be illustrated the major technique means of present embodiment at the electronic installation of present embodiment.Fig. 7 and the main different configuration modes that are current source cell of Fig. 6 embodiment.
In present embodiment, layout areas 700 is divided into first area Z710 and second area, and layout areas 700 has a rough datum line ZD who passes through the center of layout areas 700.In addition, first area Z710 has a long axis parallel with datum line, and first area Z710 comprises the central point C of layout areas, and second area then is the zone behind the layout areas 700 deduction first area Z710.
Wherein, first layout units comprises the low level tuple, current source cell L1～L3 just, and a plurality of second layout units is high-order tuple M1～M7.The explanation of current source cell L1～L3 and high-order tuple M1～M7 please refer to the explanation of Fig. 6 embodiment, does not add tired stating at this.Above-mentioned element is current source cell.
First area Z710 forms according to datum line ZD, and in the present embodiment, the long axis of first area Z710 and datum line ZD are positioned at same position.And current source cell L1～L3 is disposed in the Z710 of first area, and benchmark line ZD arranges.In addition, if first area Z710 comprises the untapped residue block of current source L1～L3, then dispose a simulation unit D.
Then be configured in second area respectively as for high-order tuple M1～M7, wherein a plurality of second layout units are that benchmark line ZD is symmetrically distributed.In addition, high-order tuple M1 more can be divided into four parts, is disposed at sub-block S711～S714 respectively.All the other high-order tuple M2～M7 all are divided into four parts then as shown in Figure 7, are that benchmark line ZD is symmetrical distribution.
In the present embodiment, more can be at high-order tuple M1～M7 zone then configurable several emulation elements D in addition, so that the element characteristic of current source cell behind processing procedure is more consistent among high-order tuple M1～M7.
Fig. 7 only for a kind of configuration mode of explanation present embodiment technological means, does not limit configuration mode of the present invention with this.As long as first layout units and second layout units are benchmark line arranged distribution, all belong to technological means category of the present invention.Have in the present technique field and to know that usually the knowledgeable should know layout type that all the other are suitable for by inference easily via exposure of the present invention, do not add tired stating at this.
In another embodiment of the present invention, if (for example need with a plurality of electronic installations, when the electronic installation shown in Fig. 7) being in the layout of on the wafer, can be according to the relative position of wafer and layout areas, adjust the arrangement angles of layout areas, make the processing procedure difference between the current source cell in the layout areas drop to minimum.In the present embodiment, electronic installation can be according to the shape of layout areas, obtain the datum line ZD of a diagonal, and datum line ZD is rough vertical with the center line connecting direction of wafer with the central point C of layout areas, as Fig. 6 and datum line ZD shown in Figure 7 as layout areas.Below explanation please refer to Fig. 6,7, and Fig. 8 is wafer layout configurations figure according to another embodiment of the present invention.
The layout method of present embodiment comprises the following steps: at first, central point 800C with wafer 800 is a benchmark, wafer 800 is divided into N configuring area, and according to the relative position of the central point 800C of configuring area and wafer, define at least one layout reference line at each configuring area, meaning is promptly set N layout reference line, and N is a positive integer.
Then, those current source matrixes are disposed in those configuring areas, and the current source matrix in each configuring area is an arrangement angles of adjusting current source matrix according to the layout reference line of this configuring area.For example, according to the layout areas 600 of current source matrix and the corresponding relation of configuring area,, adjust the arrangement angles of the layout areas of current source matrix according to corresponding layout angle.In the present embodiment, equaling 4 with N is that example is as follows as an illustration.
As shown in Figure 8: when N equals 4, then the central point 800C with wafer 800 is a datum mark, and on the circumference of wafer 800, set 4 points, wafer 800 is divided into 4 configuring areas 810～840, and line according to the central point of the central point 800C of wafer 800 and electronic installation, determine the layout reference line, this layout reference line is perpendicular to this line.In present embodiment, connect 2 adjacent on circumference points respectively, set 4 layout reference line C D1～CD4.
Then, if layout areas 600 is disposed at configuring area 810, the datum line ZD that then makes layout areas 600 is (in the present embodiment, the diagonal of layout areas 600 is datum line) parallel arrangement reference line C D1, if layout areas 600 is disposed at configuring area 820, then make the datum line ZD parallel arrangement reference line C D2 of layout areas 600, the rest may be inferred by analogy for it, do not add tired stating at this.Utilize this layout type, then can reduce the influence of processing procedure difference and Temperature Distribution the current source matrix in the layout areas 600.600 of layout areas in the present embodiment do not add tired stating at this as shown in Figure 6.
If in the time of need being in the layout of the current source matrix of Fig. 7 on one wafer 800,, adjust the layout angle of layout areas 700 then according to the layout reference line C D1～CD4 of layout areas 700 pairing configuring areas 810～840.When for example layout areas 700 being disposed at configuring area 810, then with the datum line ZD parallel arrangement reference line C D1 of layout areas 700.The rest may be inferred by analogy for it, is not repeated.
Comprehensively above-mentioned, by another viewpoint, in another embodiment of the present invention, the present invention proposes a kind of layout method of electronic installation, this electronic installation is to comprise first layout units and a plurality of second layout units, first layout units and second layout units have a plurality of elements respectively, comprise the following steps: at first, first layout units are disposed at a center block of a layout areas.Then, the element of each second layout units is disposed at a plurality of peripheral block of layout areas respectively.
Wherein, the layout method in the present embodiment is also applicable to the current source matrix of a numerical digit analogy converter.This current source matrix comprises a low level tuple and a plurality of high-order tuple, and above-mentioned low level tuple is first layout units, and high-order tuple is second layout units.Wherein, the low level tuple has a plurality of first current source cells (and above-mentioned element), high-order tuple has a plurality of current source cells respectively, its configuration mode is a benchmark with the central point of layout areas, layout area is divided into four peripheral blocks and center block, and above-mentioned center block is positioned at the middle position of layout areas.The low level tuple is disposed at a center block of a layout areas; And a plurality of peripheral block that second current source cell of each high-order tuple is disposed at this layout areas respectively.
Again from another viewpoint, the present invention also propose a kind of on wafer the method for a plurality of electronic installations of layout, simultaneously, a kind of datum line that utilizes is proposed also, with the layout method of the electronic installation that is symmetrical in central point.All the other details of above-mentioned layout method have been specified among above-mentioned Fig. 6,7,8 the embodiment all, have in the present technique field and know the knowledgeable usually, via exposure of the present invention, should know remaining implementation detail of layout method of present embodiment easily by inference, do not add tired stating at this.
Comprehensively above-mentioned, in the application of current source matrix, the current source cell that the foregoing description will be responsible for low bit is disposed at the middle position of layout areas, and the current source cell that will be responsible for higher bit on average is disposed among the layout areas to be symmetrical in the mode of central point.Use the electrical influence of reduction processing procedure difference and Temperature Distribution to the current source matrix of current type numerical digit analogy converter.
Though the foregoing description only illustrates major technique means of the present invention with the current source matrix that is applied to the numerical digit analogy converter.So, electronic installation of the present invention is also applicable to the layout architecture of different matrix kenels.Electric crystal matrix for example, the layout of element (electric capacity, resistance or inductance) matrix or circuit matrix etc.Can reduce the influence of processing procedure difference and Temperature Distribution equally to circuit itself.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any affiliated technical field has knows the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (28)
1. electronic installation is characterized in that it comprises:
One first layout units is a center block that is disposed at a layout areas; And
A plurality of second layout units are a plurality of peripheral blocks that are disposed at this layout areas respectively.
2. electronic installation as claimed in claim 1, it is characterized in that wherein this electronic installation is a current source matrix, this first layout units is a low level tuple, this low level tuple has a plurality of current source cells, this second layout units is a high-order tuple, and this high position tuple has a plurality of current source cells.
3. electronic installation as claimed in claim 2 is characterized in that those peripheral blocks wherein are that central point according to this layout areas is symmetrical distribution.
4. electronic installation as claimed in claim 2 is characterized in that wherein this current source cell has a current source circuit.
5. electronic installation as claimed in claim 2 is characterized in that those current source cells of this low level tuple wherein are that central point according to this layout areas is symmetrical distribution.
6. electronic installation as claimed in claim 2 is characterized in that then disposing a simulation unit in this residual area if this center block comprises a residual area.
7. electronic installation as claimed in claim 2 is characterized in that those current source cells of each high-order tuple wherein are that central point according to this layout areas is symmetrical distribution.
8. electronic installation as claimed in claim 2 is characterized in that wherein those peripheral blocks, distinctly has most sub-block.
9. electronic installation as claimed in claim 8 is characterized in that wherein each high-order tuple is to be arranged in this sub-block of those peripheral blocks, and those sub-block that high-order tuple is set are that central point according to this layout areas is symmetrical distribution.
10. electronic installation as claimed in claim 2 is characterized in that wherein this current source matrix is to be applied to a numerical digit analogy converter.
11. electronic installation as claimed in claim 2 is characterized in that it more comprises a plurality of simulation unit, those simulation unit are positioned at the periphery of those high-order tuples.
12. the layout method of an electronic installation is characterized in that this electronic installation is to comprise one first layout units and a plurality of second layout units, this first layout units and this second layout units have a plurality of elements respectively, and this layout method comprises the following steps:
This first layout units is disposed at a center block of a layout areas; And
Those elements of each second layout units are disposed at a plurality of peripheral block of this layout areas respectively.
13. the layout method of electronic installation as claimed in claim 12 is characterized in that wherein this electronic installation is a current source matrix, this element is a current source cell.
14. the layout method of electronic installation as claimed in claim 12 is characterized in that those peripheral blocks wherein are that central point according to this layout areas is symmetrical distribution.
15. the layout method of electronic installation as claimed in claim 12, it is characterized in that wherein this first layout units being disposed in the step of this center block of this layout areas, those elements of this first layout units are that the central point according to this layout areas is symmetrical distribution.
16. the layout method of electronic installation as claimed in claim 12 is characterized in that wherein then disposing a simulation unit in this residual area if this center block comprises a residual area.
17. the layout method of electronic installation as claimed in claim 12, it is characterized in that wherein those elements with each second layout units are disposed at respectively in the step of those peripheral blocks of this layout areas, those elements are that the central point according to this layout areas is symmetrical distribution.
18. the layout method of electronic installation as claimed in claim 12 is characterized in that wherein those peripheral blocks, distinctly has most sub-block.
19. the layout method of electronic installation as claimed in claim 18, it is characterized in that wherein those elements with each second layout units are disposed at respectively in the step of those peripheral blocks of this layout areas, each second layout units is to be arranged in this sub-block of those peripheral blocks, and those sub-block that second layout units is set are that central point according to this layout areas is symmetrical distribution.
20. the layout method of electronic installation as claimed in claim 12 is characterized in that it more comprises the following steps:
Dispose the periphery of a plurality of simulation unit in those second layout units.
21. an electronic installation is characterized in that being disposed at a layout areas, this layout areas is divided into a first area and a second area, and this electronic installation comprises:
One first layout units has at least one element, is disposed at this first area; And
A plurality of second layout units are disposed at this second area, and wherein each second layout units has at least one element;
Wherein, this layout areas has a datum line, the rough center of this datum line by this layout areas, and this first area has a long axis parallel with this datum line, and this first area comprises the center of this layout areas.
22. electronic installation as claimed in claim 21 is characterized in that wherein this electronic installation is positioned on this layout areas of a wafer, this datum line is rough vertical with the center line connecting direction of this wafer with the center of this layout areas.
23. electronic installation as claimed in claim 21 is characterized in that wherein this layout areas is positioned on the configuring area of a wafer, this configuring area has a layout reference line, and this datum line is parallel with this layout reference line.
24. electronic installation as claimed in claim 23 is characterized in that wherein this layout reference line is based on this configuring area and is positioned at the position of this wafer and determines.
25. electronic installation as claimed in claim 21 is characterized in that wherein this electronic installation is a current source matrix, this first layout units is a low level tuple, and this second layout units is a high-order tuple.
26. electronic installation as claimed in claim 25 is characterized in that wherein this element is a current source cell, it is to have a current source circuit.
27. electronic installation as claimed in claim 21 is characterized in that wherein those second layout units are to be symmetrical distribution according to this datum line.
28. electronic installation as claimed in claim 21 is characterized in that more comprising a plurality of simulation unit, those simulation unit are positioned at the periphery of those second layout units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101114132A CN101127528A (en) | 2006-08-16 | 2006-08-16 | Electronic device applicable to current source matrix and its layout method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101114132A CN101127528A (en) | 2006-08-16 | 2006-08-16 | Electronic device applicable to current source matrix and its layout method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101127528A true CN101127528A (en) | 2008-02-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101114132A Pending CN101127528A (en) | 2006-08-16 | 2006-08-16 | Electronic device applicable to current source matrix and its layout method |
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| Country | Link |
|---|---|
| CN (1) | CN101127528A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356882A (en) * | 2015-12-04 | 2016-02-24 | 上海兆芯集成电路有限公司 | Current source apparatus |
| CN105448963A (en) * | 2015-12-04 | 2016-03-30 | 上海兆芯集成电路有限公司 | Transistors and current source device |
-
2006
- 2006-08-16 CN CNA2006101114132A patent/CN101127528A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356882A (en) * | 2015-12-04 | 2016-02-24 | 上海兆芯集成电路有限公司 | Current source apparatus |
| CN105448963A (en) * | 2015-12-04 | 2016-03-30 | 上海兆芯集成电路有限公司 | Transistors and current source device |
| CN105356882B (en) * | 2015-12-04 | 2019-03-15 | 上海兆芯集成电路有限公司 | Current-source arrangement |
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