CN101123117B

CN101123117B - Non volatile memory device and its operation method

Info

Publication number: CN101123117B
Application number: CN2006101093598A
Authority: CN
Inventors: 陈宗仁; 汪若瑜
Original assignee: MOSED TECHNOLOGY Co Ltd
Current assignee: Examine Vincent Zhi Cai Management Co
Priority date: 2006-08-10
Filing date: 2006-08-10
Publication date: 2010-07-07
Anticipated expiration: 2026-08-10
Also published as: CN101123117A

Abstract

The invention discloses a nonvolatile memory with the page buffer provided with two resisters, and the memory comprises a memory unit matrix, a selector circuit and a page buffer circuit. The selector circuit is coupled with an outer data bus, the page buffer circuit comprising a first resister and a second resister is coupled between the memory unit matrix and the selector circuit, and the first and the second registers are coupled together via a sensing node. The first and the second registers alternately write the data into the memory unit matrix through programming. When programmed write is carried out for one of the first and the second resisters, the other register is used for storing the data from the data bus at the same time. In other words, when programmed write is being carried out by the first resister, the second memory is used for storing the data from the data bus, and when programmed write is being carried out by the second resister, the first memory is used for storing the data from the data bus.

Description

Non-volatile memory device and method of operating thereof

Technical field

The present invention relates to a kind of semiconductor memory system, relate in particular to a kind of page buffer (page buffer) circuit and have non-volatile (non-volatile) storage arrangement and the method for operating thereof of pair register (dual register).

Background technology

Denomination of invention is the United States Patent (USP) the 6th of " page buffer has the non-volatile memory device and the method for operating thereof of pair register ", describe for 671, No. 204 and a kind ofly have the cache programming and write (cache program) and copy back the page buffer design of depositing (copy-back) function.Fig. 1 is the synoptic diagram of an explanation page register (page register) and sensor amplifier (sense amplifier) block 120.Described page register and sensor amplifier block 120 are coupled between a memory cell array (memory cell array) the 110 and one Y grid controlling circuit 130.Described page register and sensor amplifier block 120 comprise a bit line (bit line) control circuit 140 and a page buffer 122.Described page buffer 122 has one and is connected to the line of induction 125 of described bit line control circuit 140 via sense node E.

Described bit line control circuit 140 comprises four NMOS transistors 141,142,143 and 144.Described nmos pass transistor 141 and 142 in series is coupled between bit line BLE and the BLO, and respectively by control signal VBLE and VBLO control.Described transistor 141 and 142 drain electrode jointly are coupled to a signal wire VIRPWR.Described nmos pass transistor 143 is coupled between described bit line BLE and the described sense node E, and is controlled by a control signal BLSHFE.Described nmos pass transistor 144 is coupled between described bit line BLO and the described sense node E, and is controlled by a control signal BLSHFO.

Described page buffer 122 has a master register 150 and a background register 170; Described register all is connected to the described line of induction 125.Described master register 150 comprises two nmos pass transistors 151 and 152, two phase inverters 153 and 154, and a PMOS transistor 155.Data storage is in a main latch 156 that is formed by phase inverter 153 and 154.One PMOS transistor 155 is as precharge (pre-charge) circuit of described main latch 156.Described background register 170 comprises two nmos pass transistors 171 and 172, two phase inverters 173 and 174, and a PMOS transistor 175.Described phase inverter 173 and 174 forms an auxiliary lock storage 176.Described PMOS transistor 175 is as the pre-charge circuit of described auxiliary lock storage 176.As a switch, be used to control between described background register 170 and the described master register 150 data transmission by a nmos pass transistor 181 of control signal PDUMP control via the described line of induction 125.Nmos pass transistor 182 and 183 is controlled from described data line 131 data storage to described background register 170 via external control signal DI and nDI respectively.-PMOS transistor 148 provides electric current to described bit line BLE and BLO via the described line of induction 125 during reading (read).Described PMOS transistor 148 is connected between a supply voltage and the described line of induction 125, and is controlled by a control signal PLOAD.

When the data that write to be programmed when described master register 150 is sent to selected bit line BLE or BLO, open a nmos pass transistor 184 to connect described master register 150 and described selected bit line BLE or BLO.Nmos pass transistor 185 by control signal PBDO control exports sense data to described page buffer 122 outsides from described selected bit line.The state that one transistor 186 may be programmed in order to inspection, and provide programming to write at the Node B place of described master register 150 be by or the information of failure.

Described Y grid controlling circuit 130 is between described page register and sensor amplifier block 120 and described data line 131.Described Y grid controlling circuit 130 is made of two nmos pass transistors 132 and 133, is controlled by signal YA and YB respectively.

During cache programming write operation, outer input data at first is stored in the described background register 170, and then transfers to described master register 150 via the described line of induction 125.During copy restore operation, at first read the data in the described memory cell array 110, and be stored to described background register 170, after new data inputed to described background register 170, whole page data was sent to described master register 150 and writes and verify (verification) as programming.Because data must transmit between described master register 150 and described background register 170, thus its programming write-in program relative complex, and data transmit between described two registers and also need expend the more time.

Summary of the invention

The object of the present invention is to provide a kind of page buffer circuit to have the non-volatile memory device of pair register, it can be omitted in programming and write the operation that fashionable data transmit between described two registers, and making programming write efficient can significantly improve.In addition, write fashionablely copying back the programming of depositing, only a register can be finished, and makes that operation is simplified.

For reaching above purpose, the present invention discloses the non-volatile memory device that a kind of page buffer has pair register, for example a quickflashing (flash) storer.Described non-volatile memory device comprises a memory cell array, a selector circuit and one page buffer circuit, described selector circuit is coupled to an external data line and selects to be used for the page buffer, the page buffer circuit that comprises one first register and one second register is coupled between described memory cell array and the described selector circuit, and described first register and described second register are jointly via a sense node and a back end and coupled in parallel.Write in programming fashionable, described first and described second register alternately with the writing data into memory cell array, when described first and described second register one of them carry out programming and write fashionablely, another register is stored the data from described data line simultaneously.In other words, write fashionablely when described first register carrying out programming, described second register-stored is from the data of described data line, and writes fashionablely when described second register carrying out programming, and described first register-stored is from the data of described data line.

Described memory cell array comprises at least two unit strings (cell string), and described two unit strings are coupled to described page buffer circuit via two bit lines.In first embodiment, described unit strings comprises one and is electrically connected to first end of described page buffer circuit via a bit line, and one is electrically connected to second end with common source (commonsource) line of a ground voltage.

Described two bit lines link to each other with the transistor of a bit line control circuit, and described bit line control circuit is selected one of described two bit lines, and make described selected bit line and sense node be connected.In addition, described bit line control circuit provides suitable bias voltage to described bit line, with the memory cell in the described memory cell array of access.

Described first and second register all comprises: a latch, and it is used for keeping (hold) data; One first read control circuit, it is used for writing checking or copying back and during the programming of depositing writes verification operation bit line data is latching to described latch reading or programme; One first programming write control circuit, it is used for during the programming write operation data of described data line being sent to described latch; One second programming write control circuit, it is used to control the data transmission to sense node from described latch; And one first preset (pre-set) control circuit, its be used for programming write or copy restore operation during described latch is set at a predetermined value.

For a flash memory, there are four kinds of operator schemes, i.e. programming writes, reads, copies back and deposit and erase verification (erase verification).The three kinds of operator schemes in back all relate to the induction of flash memory cells, and the programming write operation relates to from register driving flash memory cells.Described first and second register is alternately carried out the programming write operation, but is reading, copying back and deposit or erase verification only first register startup of operating period.Therefore, described first register further comprises: one second read control circuit, its be used for copy back deposit read or erase verification operating period with the data latching of described data line to described latch; One the 4th read control circuit, it is used for during read operation the data of described latch are sent to described data line; And one second preset control circuit, and it is used for during read operation described latch being set at a predetermined value.

During a programming write operation, the memory cell that non-programming is write needs its corresponding bit-line pre-charge to a supply voltage, and the memory cell that programming is write is pulled low to a ground voltage with its corresponding bit line.During read operation, described bit line at first is discharged to a ground voltage and then is precharged to a certain voltage level.When the memory cell of institute's access is in an erase status (erased state), ground voltage on common source (common cource) line is pulled to a ground voltage level with corresponding bit line, and the memory cell of institute's access is when being in the state (programmedstate) that may be programmed into, and its corresponding bit line is in a certain voltage level.Therefore, can distinguish the state of the memory cell of institute's access.

In addition, second embodiment of the invention discloses a kind of nonvolatile memory that can operate in the opposite direction, a side-looking that is about to be connected to the memory cell strings of a bit line is the one source pole node, and the opposite side of described unit strings is considered as a drain side, and described drain side is electrically connected to common drain (common drain) line that is coupled to a supply voltage.

Similarly, during the programming write operation, its corresponding bit line bias of memory cell to the ground voltage that programming writes writes to programme, and the memory cell that non-programming is write needs its corresponding bit line bias to a supply voltage is write to suppress programming.The programming writing mechanism can be F-N tunnelling (F-N tunneling) transmission or source side is injected (injection).Yet, during read operation, bit line discharges to a ground voltage, and omission bit-line pre-charge handling procedure subsequently.When then, the supply voltage on the common drain line is pulled to the corresponding bit line in the unit that is read one mains voltage level and is in erase status because of the described memory cell that reads because of unlatching.On the contrary, bit-line voltage will the described memory cell that reads be in one may be programmed into state the time keep ground voltage level.

For reaching above-mentioned functions, need to revise the page buffer circuit of this type nonvolatile memory.The nmos pass transistor of one source pole ground connection is added into described bit line control circuit to be used for bit line discharges during read operation.Add one by the phase inverter of sense node control so that the logic state of described sense node is opposite.Because there be not anti-phase reading (inverse read) in this type nonvolatile memory when copy restore operation, so compare with first embodiment, described second read control circuit is connected to the opposite side of described latch.

As mentioned above, described first and second register of described page buffer circuit is alternately carried out programming and is write.And carry out programming at described first register and write fashionablely, described second register is stored the data that write to be programmed simultaneously.Therefore, the data that can omit between described two registers of described page buffer transmit, and can simplify relevant control signal.In addition,, during read operation, do not need precharge to handle, therefore can reduce memory access time and power consumption for the memory cell array of operating in the opposite direction.

Description of drawings

Fig. 1 is the synoptic diagram of the page buffer circuit of routine;

Fig. 2 (a) is a flash memory device of the present invention;

Fig. 2 (b) is the synoptic diagram of the memory cell array of first embodiment of the invention;

Fig. 2 (c) is the circuit diagram of the page buffer circuit of first embodiment of the invention;

Fig. 3 is the sequential chart of the programming write operation of first embodiment of the invention;

Fig. 4 is the data flow synoptic diagram of the programming write operation of first embodiment of the invention;

Fig. 5 is the sequential chart of the read operation of first embodiment of the invention;

Fig. 6 is the data flow synoptic diagram of the read operation of first embodiment of the invention;

Fig. 7 is the sequential chart of the copy restore operation of first embodiment of the invention;

Fig. 8 is the data flow synoptic diagram of the copy restore operation of first embodiment of the invention;

Fig. 9 (a) is the synoptic diagram of the memory cell array of second embodiment of the invention;

Fig. 9 (b) is the circuit diagram figure of the page buffer circuit of first embodiment of the invention;

Figure 10 is the sequential chart of the programming write operation of second embodiment of the invention;

Figure 11 is the data flow synoptic diagram of the programming write operation of second embodiment of the invention;

Figure 12 is the sequential chart of the read operation of second embodiment of the invention;

Figure 13 is the data flow synoptic diagram of the read operation of second embodiment of the invention;

Figure 14 is the sequential chart of the copy restore operation of second embodiment of the invention; And

Figure 15 is the data flow synoptic diagram of the copy restore operation of second embodiment of the invention.

Embodiment

Fig. 2 (a) is the synoptic diagram of flash memory device 200 of the present invention, described storage arrangement 200 comprise a memory cell array 210, a plurality of page buffers circuit 220,221 ... and 2NN, an and selector circuit 230.Described page buffer circuit 220,221 ... and 2NN is coupled between described memory cell array 210 and the described selector circuit 230.

Fig. 2 (b) is the synoptic diagram of the described memory cell array 210 of first embodiment of the invention.Described memory cell array 210 comprises a plurality of unit strings 2101, each described unit strings 2101 comprises one first end P and one second end Q, the described first end P via bit line BLE or BLO be electrically connected to corresponding described page buffer circuit 220,221 ... or 2NN; The described second end Q is electrically connected to a common source line CSL.Described unit strings 2101 comprises ground connection selection transistor (the ground selection transistor) ST2 that string select transistor (string selection transistor) ST1, who is coupled to described bit line BLE is coupled to common source line CSL, and the memory cell M1-Mm of coupled in series between described string select transistor ST1 and described ground connection selection transistor ST2.Described bit line BLE is connected to the drain node of described memory cell M1 via described transistor ST1, and described common source line CSL is connected to the source node of described memory cell Mm via described transistor ST2.Described string select transistor ST1, described memory cell M1-Mm and described ground connection select transistor ST2 to be coupled to a string selection wire (string selection line) SSL, word line (word line) WL1-WLm and a ground connection selection wire (ground selection line) GSL respectively.Lines such as described SSL, described WL1-WLm and described GSL are electrically connected to a row decoder circuit 22, described common source line CSL is connected to ground voltage, two adjacent described bit line BLE and BLO form be connected to described page buffer circuit 220 a bit line to (bit line pair), and other bit line to be connected to respectively described page buffer circuit 221,222 ... and 2NN.

Fig. 2 (c) is the circuit diagram of described page buffer circuit 220, and described page buffer circuit 220 comprises a bit line control circuit 240, a pre-charge circuit 290, one first register 250 and one second register 270.

Described bit line control circuit 240 comprises four NMOS transistors 241,242,243 and 244.Described

nmos pass transistor

241 and 242 coupled in series are between bit line BLE and BLO, and by its control signal corresponding VBLE and VBLO control.Described

transistor

241 and 242 drain electrode are coupled to a signal wire VIRPWR jointly.Described nmos pass transistor 243 is coupled between a described bit line BLE and the sense node SO, and is controlled by a control signal BLSHFE.Described nmos pass transistor 244 is coupled between described bit line BLO and the described sense node SO, and is controlled by a control signal BLSHFO.

Described pre-charge circuit 290 comprises a PMOS transistor 292, and it is coupled between a supply voltage and the described sense node SO, and is controlled by a control signal PLOAD.Described PMOS transistor 292 provides electric current to described bit line BLE and BLO via described sense node SO.

Described first register 250 comprises: a latch L1 who is made up of phase inverter 253a and phase inverter 253b, one one first read control circuit of forming by nmos pass transistor 251a and 251b 251, one one second read control circuit of forming by

nmos pass transistor

256a and 256b 256, one one the 4th read control circuit of forming by nmos pass transistor 257, one by

nmos pass transistor

252a and 252b form one first the programming write control circuit 252, one by nmos pass transistor 255 form one second the programming write control circuit, one one first is preset control circuit and and one second presets control circuit by what PMOS transistor 258 was formed by what PMOS transistor 254 was formed.

Described nmos pass transistor 255 is coupled between one second latch node B and the described sense node SO, and is controlled by a control signal BLSLT1.Described nmos pass transistor 252a is coupled between the one first latch node A and a back end DI of described latch L1, and is controlled by a control signal DI1; And described nmos pass transistor 252b is coupled between the described second latch node B and described back end DI of described latch L1, and is controlled by a control signal NDI1.Described nmos pass transistor 251a and 251b coupled in series, and respectively by described sense node SO and control signal PBLCHM1 control.Described

nmos pass transistor

256a and 256b coupled in series, and respectively by described sense node SO and control signal CPLCHM control.Described PMOS transistor 254 is coupled between a supply voltage and the described second latch node B, and is controlled by a control signal CPRST1.Described PMOS transistor 258 is coupled between a supply voltage and the described first latch node A, and is controlled by a control signal PBRST.Described nmos pass transistor 257 is coupled between described second latch node B and the described back end DI, and is controlled by a control signal PBDO.

Described second register 270 comprises: the third reading that a latch L2 who is made up of

phase inverter

273a and 273b, is made up of nmos pass transistor 271a and 271b is got one the 3rd programming write control circuit 272 that control circuit 271, is made up of

nmos pass transistor

272a and 272b, one the 4th write control circuit of being made up of nmos pass transistor 275 and of programming one the 3rd presets control circuit by what PMOS transistor 274 was formed.

Described nmos pass transistor 275 is coupled between one the 3rd latch node C and the described sense node SO, and is controlled by control signal one BLSLT2.Described nmos pass transistor 272a is coupled between a quad latch node D and the described back end DI, and is controlled by a control signal DI2; And described nmos pass transistor 272b is coupled between described the 3rd latch node C and the described back end DI, and is controlled by a control signal NDI2.Described nmos pass transistor 271a and 271b coupled in series, and respectively by described sense node SO and control signal PBLCHM2 control.Described PMOS transistor 274 is coupled between a supply voltage and the described sense node SO, and is controlled by a control signal CPRST2.

Fig. 3 and Fig. 4 describe the cache programming wiring method of the first embodiment of the present invention.Figure 3 shows that the command signal of the circuit that is applied to Fig. 2 (c).Abscissa is divided into 9 sections, is denoted as 1 to 9.Figure 4 shows that how data transmit in the circuit of Fig. 2 (c), its should according to mark and Fig. 3 simultaneously referring to.

At first (period 1), described latch L1 and L2 are predisposed to predetermined value, be that logic low is opened described

PMOS transistor

254 and 274 by start described control signal CPRST1 and CPRST2 in selected interim.

In the period 2, the described latch node B of described first register 250 is in logic high.The first group of data storage that writes to be programmed is in the described first latch L1.Therefore data " 1 " or " 0 " among the described data line DL is that logic high is stored to described latch L1 by starting described control signal DI1 or NDI1 respectively.In other words, DI1 and NDI1 are in inverse state.

In the period 3, described sense node SO is logic low and precharge by start described control signal PLOAD during selected short time interval.In the period 4, all do not change on all signals.

In the period 5, described bit line BLE and BLO are by drawing described signal VIRPWR for logic high and starting described control signal VBLE and VBLO is logic high precharge, and this prevents non-selected memory cell maloperation.If described BLE is selected bit line, then described signal VBLE is a logic high in the period 5, and switches to logic low in subsequent periods of time 6, and described signal VBLO then keeps logic high in subsequent periods of time 6.

In period 6 and 7, two actions take place simultaneously, the data that write to be programmed are logic high and be sent to selected described bit line BLE from described first register 250 by starting described signal BLSLT1 and BLSHFE, and then data are sent to described memory cell array 110 from selected described bit line BLE.Simultaneously, from the second group of data storage that writes to be programmed of described data line DL in described second register 270.Data " 1 " among the described data line DL or " 0 " are that logic high is stored (or being written into) in the described second latch L2 by starting described control signal DI2 or NDI2 respectively.Data programing writes and described second register is written into data simultaneously because described first register is carried out, and this is the cache memory operation, is written into and programmes the write time so can reduce significantly.

In the period 8, the checking that programming writes begins.Read operation in the time of hereinafter will describing checking in more detail.

In the period 9, described bit line VBLE and VBLO once more precharge to be written into/to programme write operation next time.

Similarly, in the write operation of cache programming next time, the data that write to be programmed are sent to selected described bit line BLE or BLO by the similar operations that starts described BLSLT2 signal and described bit line control circuit 240 from described second register 270, and simultaneously from the 3rd group of data storage that writes to be programmed of described data line DL in described first register 250.

In other words, write fashionablely when just carrying out programming from the data of a register, next data that writes to be programmed are written in another register, and vice versa.In addition, data directly write to described memory cell strings from register programming, make the present invention no longer need as in the prior art mentioned from a register intermediate treatment of data transmission to another register.

Fig. 5 and Fig. 6 describe the normal read operation of page buffer circuit 220, and wherein data are read from described memory cell array 210, and the grid control signal of memory cell to be read applies appropriate voltage via word line.

Figure 5 shows that the command signal of the circuit that is applied to Fig. 2 (c), abscissa is divided into 6 sections, is denoted as 1 to 6.Figure 6 shows that how data transmit in the circuit of Fig. 2 (c), its should according to mark and Fig. 5 simultaneously referring to.

In the period 1, described bit line BLE and BLO be at first by making zero described signal VIRPWR and start described control signal VBLE and VBLO is a logic high, and via described

nmos pass transistor

241 and 242 discharges.Simultaneously, described PBRST signal switches to logic low to open described transistor 258 in selected interim from logic high, makes the latch node A of described first register 250 transfer logic high to, is about to latch L1 and is set at predetermined value.

In the period 2, described PLOAD signal transfers logic low to open described PMOS transistor 292.To be similar to voltage and (for example, 1.5V) be applied to the described control signal BLSHFE of described nmos pass transistor 243, so that described bit line BLE is precharged to pre-charge voltage.Therefore, the voltage of described sense node SO will equal pre-charge voltage.

In the period 3, described signal BLSHFE transfers the logic low of ground voltage to, and described subsequently signal PLOAD switches to logic high, and described

transistor

243 and 292 will be closed.

The pre-charge voltage of bit line changes according to the state of selected memory cell.Be under the situation of the state that may be programmed at selected memory cell, bit line keeps pre-charge voltage.Be under the situation of erase status at selected memory cell, the pre-charge voltage of bit line is pulled to ground voltage gradually.Therefore, the voltage of described sense node SO is to be in to may be programmed into or erase status is decided according to memory cell.

In the period 4, the described grid control signal PBLCHM1 of described nmos pass transistor 251b transfers logic high to, and described signal BLSHFE is biased in 1.0V during selected short time interval, and described nmos pass transistor 251a opens or closes according to the state of described sense node SO.Described transistor 251a opens when being in the state that may be programmed in the word-select memory unit, and closes when being in erase status in the word-select memory unit.As a result, the state storage of described sense node SO is in latch L1.In other words, the data mode of word-select memory unit is stored in described first register 250.

In the period 5, described nmos pass transistor 241,242,243 and 244 is opened, be that described control signal VBLE, VBLO, BLSHFE and BLSHFO are in logic high, make described bit line BLE and BLO and described sense node SO via described signal VIRPWR discharge with logic low.

In the period 6, the data that are stored in described first register 250 are sent to described data line DL via being subjected to described control signal PBDO to control described nmos pass transistor 257.

Fig. 7 and Fig. 8 describe copy restore operation, and wherein data read out in described first register 250 from a unit of described memory cell array 210, and copy back and deposit to another unit.

Figure 7 shows that the command signal of the circuit that is applied to Fig. 2 (c), abscissa is divided into 11 sections, is denoted as 1 to 11, and the

period

1,2,3 and 4 is read operation period, and the

period

5,6,7,8,9,10 and 11 is programming write operation period.

At first (period 1), control signal and identical shown in Fig. 5 (being read operation), except that described PMOS transistor 254 is logic low is opened by start described control signal CPRST1 in one period short-term, make the described latch node B of described first register 250 transfer logic high to, and described signal PBRST remain on logic high.

In

period

2 and 3, all control signals with before identical described in the read operation.

In the period 4, identical described in the read operation, the described grid control signal CPLCHM that removes described nmos pass transistor 256b transferred logic high to control signal in one period short-term, and described signal PBLCHM1 signal remains on beyond the logic low with before.Described nmos pass transistor 256a opens or closes according to the logic state of sense node SO.Therefore, described transistor 256a opens when selected memory cell is in the state that may be programmed into, and closes when selected memory cell is in erase status.As a result, the state storage of described sense node SO is in latch L1.In other words, the data mode of word-select memory unit is stored in described first register 250.Described second read control circuit of being made up of described

transistor

256a and 256b 256 is used for so-called reverse read (inverse read) operation.

In the

period

5,6,7,8,9,10 and 11, the control signal in the

period

3,4,5,6,7,8 and 9 of all control signals and Fig. 3 of explanation programming write operation is identical.The data that read in the period 1 to 4 write another unit in the described memory cell array 210 through programming.

About the third reading of second register 270 get control circuit 271, the 3rd programming write control circuit 272, the 4th programming write control circuit 275 and the 3rd preset the function of control circuit 274 and first register 250 related device function class seemingly.Yet, when normal read operation and copy restore operation, only carry out by described first register 250, make described third reading get control circuit 271 and only during programming writes checking, start, and the described the 3rd presets control circuit 274 and only start during the write operation in programming.

In addition, there are two PMOS transistors 259 and 279.Described

transistor

259 and 279 grid are connected to described second latch node B and described the 3rd latch node C respectively.Signal NWDD1 and NWDD2 are used to indicate the checking result of described first register 250 and described second register 270.

Described second read control circuit 256 also is used for the erase verification operation, and behind erase operation, described sense node SO should be in logic low, and described transistor 256b closes.If handle failure but wipe, then described sense node SO should be in logic high, and described transistor 256b will open.When the pulse of described CPLCHM is in logic high, follow the described second latch node B and be pulled to logic low, and described transistor 259 will open, therefore described signal NWDD1 will be pulled to logic high.

The programming that described first read control circuit 251 also is used for described first register 250 writes checking and copies back the programming of depositing and writes checking.After writing or copy back the programming write operation of depositing in programming, described sense node SO should be in logic high and described transistor 251a will open.When the pulse of described PBLCHM1 is in logic high, follow the described first latch node A and be pulled to logic low, the described second latch node B is pulled to logic high, therefore described transistor 259 will be closed, described signal NWDD1 will not be pulled to logic high, therefore if signal NWDD1 is pulled to logic high, then programming writes or copies back the programming of depositing and writes processing and promptly belong to failure.Similarly, if signal NWDD2 is pulled to logic high, the programming of then described second register 270 writes processing and also is failure.

The page buffer circuit and the method thereof of Fig. 9 (a), 9 (b) and 10 to the 15 explanation second embodiment of the present invention, wherein the unit of NAND flash memory is operated in the opposite direction.With reference to figure 9 (a), one memory cell array 910 has a plurality of unit strings 9101, each unit strings 9101 comprises one and is electrically connected to the first end P of corresponding page buffer circuit 920 via bit line BLE or BLO, and second an end Q who is electrically connected to common drain line (CDL).Described unit strings 9101 comprises the supply voltage selection transistor ST2 that a string select transistor ST1, who is coupled to bit line BLE is coupled to common drain line CDL, and coupled in series is selected the memory cell M1-Mm of transistor ST2 to described string select transistor ST1 and described supply voltage.Described bit line BLE is connected to the source node of described memory cell M1 via described transistor ST1, and described common drain line CDL is connected to the drain node of memory cell Mm via described transistor ST2.Described string select transistor ST1, memory cell M1-Mm and supply voltage select transistor ST2 to be coupled to a string selection wire SSL, word line WL1-WLm and a supply voltage selection wire PSL respectively.Lines such as described SSL, WL1-WLm and PSL are electrically connected to a row decoder circuit 92, and described common drain line CDL is connected to supply voltage.

Fig. 9 (b) illustrates page buffer circuit 920 according to a second embodiment of the present invention.Compare with the circuit among Fig. 2 (c), nmos pass transistor 945 by signal DIS control is added into a bit line control circuit 940, one second read control circuit of being made up of nmos pass transistor 956a and 956b 956 is placed and is approached described latch node A place but not approach described latch node B place, between described first read control circuit 251 of described sense node SO and described first register 950, add a phase inverter 9500, get in the described third reading of described sense node SO and described second register 970 and add a phase inverter 9700 between the control circuit 271.One nmos pass transistor 9501 and a PMOS transistor 9502 coupled in series are to form described phase inverter 9500.Described transistor 251a is by the output node P1 control of phase inverter 9500, because the control signal MP of described transistor 9502 is in logic low, so described node P1 is in the opposite logic states of described sense node SO.Similarly, a nmos pass transistor 9701 and a PMOS transistor 9702 coupled in series are to form described phase inverter 9700.Described transistor 271a is by the output node Q1 control of described phase inverter 9700, and the control signal MP of transistor 9702 is in logic low, and therefore described node Q1 is in the opposite logic states of described sense node SO.

Figure 10 and Figure 11 describe the cache programming wiring method of second embodiment, Figure 10 shows that the command signal of the circuit that is applied to Fig. 9 (b), abscissa is divided into 9 sections, be denoted as 1 to 9, Figure 11 shows that how data transmit in the circuit of Fig. 9 (b), its should according to mark and Figure 10 simultaneously referring to.

In the period 1, described first register 950 and described second register 970 are predisposed to predetermined value, described

PMOS transistor

254 and 274 is that logic low is opened by described control signal CPRST1 of startup and CPRST2 in one period short-term respectively.Therefore, described

register

950 and 970 latch node B and C are in logic high.

In the period 2, described

transistor

252a and 252b are that logic high is opened by described start-up control signal DI1 or NDI1 respectively, and therefore data " 1 " or " 0 " among the described data line DL is stored among the described first latch L1.

In the period 4, described

transistor

241 and 242 is that logic high is opened by starting described control signal VBLE and VBLO, with to described bit line BLE and BLO precharge.

Take place simultaneously in period 5 and 6, two actions.The data that write to be programmed are logic high (being turn-on transistor 255) and be sent to selected described bit line BLE from described first register 950 by starting described signal BLSLT1 and BLSHFE, and then data are sent to described memory cell array 910 from selected described bit line BLE.Simultaneously, described

transistor

272a or 272b are that logic high is opened by starting described control signal DI2 or NDI2 respectively, and for example, described DI2 is logic high in this embodiment.Therefore, the data " 1 " among the described data line DL or " 0 " are stored among the described second latch L2, that is, from next data storage that writes to be programmed of described data line DL in described second register 970.In case described signal BLSLT1 is back to logic low in the period 6, the checking that programming writes promptly begins.Described nmos pass transistor 945 is that logic high is opened by starting described control signal DIS, makes described bit line BLE discharge.

In the period 7, read operation continues, and the pulse of described PBLCHM1 is used to latch bit line signal.Then (period 8), described bit line BLE and BLO once more precharge to carry out next cache programming write operation.

With reference to Figure 12 and Figure 13, illustrate the normal read operation of described page buffer circuit 920.

At first (period 1), described bit line BLE at first by start described control signal BLSHFE and DIS be logic high and via described

nmos pass transistor

243 and 945 the discharge.Described transistor 242 is that logic high is opened by start-up control signal VBLO, so that when described signal VIRPWR is in logic high described bit line BLO is pulled to logic high, to prevent non-selected memory cell maloperation.Simultaneously, described PBRST signal switches to logic low to open described transistor 258 from logic high in one period short-term, and therefore the latch node A of described first register 950 is set to logic high.

Compare with the read operation of first embodiment, do not have the bit line precharge operation among second embodiment, therefore on all signals, there is no conversion in period 2 and period 3.

Be under the situation of the state that may be programmed at selected memory cell, the voltage of bit line keeps logic low.Be under the situation of erase status at selected memory cell, the voltage of bit line is pulled to logic high.In other words, described sense node SO has the state opposite with memory cell.Therefore, described phase inverter 9500 is used to make the opposite states of SO, with the correct status of the unit of attempting to indicate institute's access.

In the period 4, the pulse of described PBLCHM1 is used for bit line signal is latching to the described latch L1 of described first register 950.

In the period 5, described bit line BLE and BLO and described sense node SO are logic high and via 945 discharges of described nmos pass transistor by starting described control signal DIS, BLSHFE and BLSHFO.

In the period 6, the data that are stored in described first register 950 are sent to data line DL via the described nmos pass transistor 257 that is subjected to described control signal PBDO control.

Figure 14 and Figure 15 are the copy restore operation of the device of key diagram 9 (b), Figure 14 shows that the command signal of the circuit that is applied to Fig. 9 (b).Abscissa is divided into 11 sections, is denoted as 1 to 11, and the

period

1,2,3 and 4 is read operation period, and the

period

5,6,7,8,9 and 10 is programming write operation period.

In the

period

1,2 and 3, all control signals promptly are read operation with identical shown in Figure 12.

In the period 4, control signal is identical with read operation, and the pulse that substitutes PBLCHM1 except that the pulse of a CPLCHM is used for bit line signal is latching to the described latch L1 of described first register 950.Because in copy restore operation, during read operation, there is no anti-phase reading, so compare with described

circuit

256a and 256b among Fig. 2 (c), described second read control circuit 956 that comprises described

transistor

956a and 956b is positioned on the opposite side of described latch L1.

In the

period

5,6,7,8,9 and 10, all control signals are identical with the control signal of the

period

3,4,5,6,7 shown in Figure 10 and 8, promptly are the programming write operation.

Described in first embodiment, described second read control circuit 956 also is used for the erase verification operation, and after the erase verification operation, if described signal NWDD1 is pulled to logic high, then erase verification is handled and promptly belonged to failure.

The programming that described first read control circuit 251 also is used for described first register 950 writes checking and copies back the programming of depositing and writes checking.After writing or copy back the programming write operation of depositing in programming, if described signal NWDD1 is pulled to logic high, then programming writes or copies back the programming of depositing and writes processing and promptly belong to failure.Similarly, if described signal NWDD2 is pulled to logic high, the programming of then described second register 970 writes processing and also belongs to failure.

As mentioned above, first and second register of page buffer circuit is alternately carried out the programming write operation, and storage is from the data that write to be programmed of data line, and these data that can omit between two registers of page buffer transmit, and therefore device can more effectively be worked.In addition, second embodiment of the invention discloses the memory cell array that can operate in the opposite direction, does not need precharge to handle during read operation, therefore can reduce memory access time and power consumption.

Technology contents of the present invention and technical characterstic disclose as above, yet the those skilled in the art still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appending claims.

Claims

1. the programming wiring method of a non-volatile memory device is characterized in that comprising following steps:

In will one first register from first data storage to a page buffer of a data line;

Described first data programing is write in the memory cell of a memory cell array, and simultaneously will be from second data storage of described data line to one second register of described page buffer; And

Described second data programing is write in another memory cell of described memory cell array, and simultaneously will be from the 3rd data storage of described data line in described first register of described page buffer.

2. the programming wiring method of non-volatile memory device as claimed in claim 1 is characterized in that described first data are a whole page data.

3. the programming wiring method of non-volatile memory device as claimed in claim 1, it is characterized in that described first and described second data be coupled to the sense node between described first and described second register in parallel via one and be programmed and write in the described memory cell.

4. the programming wiring method of non-volatile memory device as claimed in claim 1 is characterized in that comprising in addition step: with before described first data storage is to described first register, preset described first and described second register.

5. the programming wiring method of non-volatile memory device as claimed in claim 3, described first data that write in the described memory cell that it is characterized in that programming comprise following steps:

To described sense node precharge; And

To being coupled to the bit-line pre-charge between described page buffer circuit and the memory cell array, to prevent non-selected memory cell maloperation.