CN101122697A - Double sided grid drive type liquid crystal display and its driving method - Google Patents
Double sided grid drive type liquid crystal display and its driving method Download PDFInfo
- Publication number
- CN101122697A CN101122697A CNA2007101482497A CN200710148249A CN101122697A CN 101122697 A CN101122697 A CN 101122697A CN A2007101482497 A CNA2007101482497 A CN A2007101482497A CN 200710148249 A CN200710148249 A CN 200710148249A CN 101122697 A CN101122697 A CN 101122697A
- Authority
- CN
- China
- Prior art keywords
- signal
- driving
- driving signal
- gate
- shift registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
Abstract
A bilateral grid-driven LCD and drive method modulates the drive signal received by a first shift register and a second shift register, so that the first shift register and the second shift register respectively output a first grid-driven signal and a second grid-driven signal with 1/4 cycle pulse width, thus further controlling the conduction time of a plurality of membrane transistors and avoiding the issue of power consumption caused by pixel charging at the same time.
Description
Technical Field
The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a double-sided gate driving type liquid crystal display and a driving method thereof.
Background
FIG. 1 is a schematic circuit diagram of a TFT-LCD driven by a double-sided gate shift register. As shown in fig. 1, the number of data lines 31 (data lines) of the double-sided gate shift register-driven tft-lcd is half of that of the conventional single-sided gate-driven tft-lcd.
The first gate line 11 (odd gate line) is driven by the first shift register 10 on the left side, the second gate line 21 (even gate line) is driven by the second shift register 20 on the right side, and the gate driving signals on the left and right sides are arranged alternately. Each stage of shift register has four inputs and one output, which are respectively defined as follows: VSS is the DC reference voltage, ST is the input start pulse signal, CK is the input clock signal, XCK is the input inverse clock signal, and N is the output signal.
FIG. 2 is a timing diagram of input signals and output signals of a shift register of a dual gate driver. As shown in fig. 2, STL is a start pulse signal of a left bus (bus line), CKL is a clock signal of the left bus, XCKL is an inverted clock signal of the left bus, STR is a start pulse signal of the right bus, CKR is a clock signal of the right bus, and XCKR is an inverted clock signal of the right bus. The duty ratios of CKL, XCKL, CKR, and XCKR are all 50%, STR, CKR, and XCKR are delayed by 1/4 clock cycle compared to STL, CKL, and XCKL, the output gate driving signals are sequentially a first gate driving signal (left) G1L, a second gate driving signal (right) G1R, a first gate driving signal (left) G2L, a second gate driving signal (right) G2R, a first gate driving signal (left) G3L, a second gate driving signal (right) g3r. Since there are two output pulse signals at any time, each data line 31 charges two adjacent pixels at the same time, resulting in that the charging current supplied to one-side pixel is partially distributed to adjacent pixels, so that the charging current required by each pixel to achieve a high charging rate is larger than that of the previous one, and thus the power consumption is higher.
Therefore, how to provide a driving method with less power consumption is one of the problems to be solved by researchers.
Disclosure of Invention
In view of the above problems, the present invention provides a dual-side gate driving type lcd and a driving method thereof, which uses a signal modulation technique to prevent the overlapping of the timing sequences of the gate driving signals outputted from the shift register, thereby avoiding the problem of power consumption caused by the simultaneous charging of two pixels when the gate driving signals are overlapped, and further reducing the power consumption of the dual-side gate driving type lcd.
The invention discloses a bilateral grid drive type liquid crystal display, which comprises a plurality of first shift registers, a plurality of second shift registers, a plurality of first shift registers and a plurality of second shift registers, wherein the first shift registers receive a driving signal and generate a first grid driving signal corresponding to the time sequence of the driving signal; the plurality of second shift registers receive the driving signals and generate a second grid driving signal corresponding to the time sequence of the driving signals; the driving signals received by each first shift register and each second shift register have 1/4 period pulse width, and each first shift register and each second shift register generate a first gate driving signal and a second gate driving signal having 1/4 period pulse width according to the time sequence of the driving signals so as to control the conduction time of the plurality of thin film transistors.
In the dual gate driving type lcd, the driving signals include a dc reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
In the above-described liquid crystal display of the double-sided gate drive type, the duty ratio of the drive signal is 25%.
In the above-described liquid crystal display of the double-sided gate driving type, the duty ratio of the driving signal is greater than 25% so that the overlapping time of the first gate driving signal and the second gate driving signal is less than 1/2 of the periodic pulse width.
According to the driving method of the double-sided gate driving type liquid crystal display disclosed by the invention, the liquid crystal display comprises a plurality of thin film transistors, a first gate driver with a plurality of first shift registers and a second gate driver with a plurality of second shift registers, the driving method comprises the following steps: modulating the duty ratio of the driving signal to be 1/4, and inputting the modulated driving signal to each first shift register and each second shift register; each first shift register and each second shift register generate a first grid driving signal and a second grid driving signal with 1/4 period pulse width according to the time sequence of the input driving signal; and the first grid driving signal and the second grid driving signal output by each first shift register and each second shift register are transmitted to each thin film transistor so as to control the conduction time of each thin film transistor.
In the driving method of the dual gate driving type liquid crystal display, the driving signal includes a dc reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
In the method for driving the dual gate driving type lcd, the timing of the start pulse signal, the clock signal and the inverted clock signal input to the second gate driver is delayed by 1/4 cycle from the timing of the start pulse signal, the clock signal and the inverted clock signal input to the first gate driver.
The duty ratio of the signal input to the shift register is modulated to 25 percent through the driving method of the double-side grid driving type liquid crystal display, so that the time sequence of the grid driving signal output by the shift register is not overlapped, the problem of power consumption caused by simultaneous charging of two pixels when the grid driving signal is overlapped is avoided, the power consumption of the double-side grid driving type liquid crystal display is further reduced, in addition, the duty ratio of the signal input to the shift register is modulated to be more than 25 percent but less than 50 percent, the grid driving signal output by the shift register can start to charge the pixels at a time ahead of time, and the problem of insufficient charging rate caused by distortion generated in the transmission process of the grid driving signal is solved.
The features and embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Drawings
FIG. 1 is a circuit diagram of a TFT-LCD driven by a double-sided gate shift register in the prior art;
FIG. 2 is a timing diagram of input signals and output signals of a shift register of a dual edge gate driver according to the prior art;
FIG. 3 is a timing diagram of input signals and output signals of a shift register of a dual-sided gate driver according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a comparison of the charging time of the gate signal and the data signal;
FIG. 5 is a timing diagram of input signals and output signals of a shift register of a dual-sided gate driver according to a second embodiment of the present invention;
FIG. 6 is a flowchart illustrating the steps of a driving method according to the first embodiment of the present invention;
FIG. 7 is a flowchart illustrating steps of a driving method according to a second embodiment of the present invention; and
fig. 8 is a circuit diagram of a thin film transistor according to the present invention.
Further, the reference numerals in the drawings are explained as follows:
10 first shift register
11 first gate line
20 second shift register
21 second gate line
30 data driver
31 data line
32 data signal
40 thin film transistor
110 ideal gate drive signal
120 distorted gate drive signal
C P Liquid crystal capacitor
C S Pixel capacitance
Clock signal of CKL left side bus
Clock signal of CKR right side bus
G1L first Gate drive Signal (left)
G1R second Gate drive Signal (Right)
G2L first Gate drive Signal (left)
G2R second Gate drive Signal (Right)
G3L first Gate drive Signal (left)
G3R second Gate drive Signal (Right)
Length of time H
H1 first effective charging time
H2 second effective charging time
I DS Charging current
Start pulse signal of STL left side bus
Starting pulse signal of STR right side bus
Period T
V D Potential of data line
V G Potential of gate line
V P Potential within a pixel
Inverted clock signal of XCKL left side bus
Inverted clock signal of XCKR right side bus
Δ H overlap time
Δ tc time duration
Detailed Description
FIG. 1 is a circuit diagram of a TFT-LCD driven by a double-sided gate shift register. As shown in fig. 1, the lcd includes a plurality of first shift registers 10, a plurality of second shift registers 20, a data driver 30, a plurality of data lines 31, a plurality of first gate lines 11, a plurality of second gate lines 21, and a plurality of tfts 40.
The plurality of first shift registers 10 receive the driving signals of the left bus line, and generate first gate driving signals (e.g., G1L, G2L, G3L, G4L, G5l.. Etc.) corresponding to timings of the driving signals. The driving signal includes a DC reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
The plurality of second shift registers 20 receive the driving signals of the right bus line, and generate second gate driving signals (e.g., G1R, G2R, G3R, G4R, G5r.. Etc.) corresponding to timings of the driving signals. The driving signal includes a DC reference voltage, a start pulse signal, a clock signal and an inverted clock signal. The driving signals received by each of the first shift registers 10 and each of the second shift registers 20 have a pulse width of 1/4 period, and each of the first shift registers 10 and each of the second shift registers generate the first gate driving signal and the second gate driving signal having a pulse width of 1/4 period according to the timing of the received driving signals, so as to control the on-time of the plurality of thin film transistors 40.
Fig. 3 is a timing diagram of input signals and output signals of a shift register of a dual-sided gate driver according to a first embodiment of the invention. As shown in fig. 3, the period of CKL, XCKL, CKR, and XCKR is T, the time duration of the gate driving signal is H, and CKR and XCKR are delayed by 1/4 clock period from CKL and XCKL, respectively. STL, STR, CKL, XCKL, CKR and XCKR have a pulse width of 1/4 cycle.
By modulating the duty ratio of CKL, XCKL, CKR, and XCKR to 25%, the timings of any two gate driving signals (e.g., the first gate driving signal (left) G1L, the second gate driving signal (right) G1R, the first gate driving signal (left) G2L, the second gate driving signal (right) G2R, the first gate driving signal (left) G3L, and the second gate driving signal (right) G3R) are not overlapped. The timing sequence of the gate driving signals can avoid the problem of power consumption caused by simultaneous charging of two pixels when the gate driving signals are overlapped.
Fig. 4 is a diagram comparing the charging time of the gate signal and the data signal. As shown in fig. 4, although the first effective charging time H1 formed by the ideal gate driving signal 110 and the data signal 32 is actually distorted (distortion) due to signal delay during transmission of the gate driving signal, the second effective charging time H2 formed by the distorted gate driving signal 120 and the data signal 32 is shorter than the first effective charging time H1 by a period of time Δ tc, so that the pixel may be insufficiently charged for a large pixel capacitance.
Therefore, by advancing the turn-on time of the gate driving signal by a time length Δ tc, the maximum charging time can be achieved. Since different gate signal impedances have different signal delays, the time length Δ tc is variable, and the on-time of the gate driving signal needs to be arbitrarily adjustable to achieve the maximum charging efficiency in order to maximize the charging time of the pixel and reduce the power waste caused by the overlap of the gate signal timing sequences.
Fig. 5 is a timing diagram of input signals and output signals of a shift register of a dual-sided gate driver according to a second embodiment of the invention. As shown in FIG. 5, the cycle of CKL, XCKL, CKR and XCKR is T, and CKR and XCKR are delayed by 1/4 clock cycle compared to CKL and XCKL, respectively.
The duty ratios of CKL, XCKL, CKR and XCKR are adjusted to be more than 25% but less than 50%, the phase difference between CKL and CKR is 1/4, the phase difference between XCKL and XCKR is 1/4, the overlapping time of two adjacent gate driving signals is delta H, and the relationship between the overlapping time delta H and the duty ratio is as the following formula (1):
Δ H = duty cycle T-T/4.
Where T is the period and has the maximum pixel charging efficiency when the overlap time Δ H is equal to the time length Δ tc. Therefore, by adjusting the time sequence overlapping time of the output grid driving signal of the shift register, the problem of insufficient charging rate caused by pixel charging time delay caused by waveform distortion of the grid driving signal can be solved, and excessive power consumption can be still avoided because the time sequence overlapping time of the grid driving signal is shorter.
Fig. 6 is a flowchart illustrating a driving method according to a first embodiment of the present invention. The double-side grid drive type LCD of the invention comprises a plurality of thin film transistors, a first grid driver with a plurality of first shift registers and a second grid driver with a plurality of second shift registers, and the drive method comprises the following steps:
first, the duty ratio of the modulation driving signal is 25%, and the modulated driving signal is input to each first shift register and each second shift register, in step 200, wherein the driving signal includes a dc reference voltage, a start pulse signal, a clock signal, and an inverted clock signal.
Then, each of the first shift registers and each of the second shift registers generate a first gate driving signal and a second gate driving signal having a pulse width of 1/4 period according to the timing of the input driving signal, in step 201.
Each of the first shift registers and each of the second shift registers outputs a first gate driving signal and a second gate driving signal to each of the tfts to control the on-time of each of the tfts, as shown in step 202.
Fig. 7 is a flowchart illustrating a driving method according to a second embodiment of the present invention. As shown in fig. 7, the dual-sided gate driving lcd of the present invention includes a plurality of tfts, a first gate driver having a plurality of first shift registers, and a second driver having a plurality of second shift registers, and the driving method includes the following steps:
first, the duty ratio of the modulation driving signal is greater than 25% but less than 50%, and the modulation driving signal is inputted to each stage of the first shift register and each stage of the second shift register, as shown in step 300. The driving signal includes a DC reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
Then, each of the first shift registers and each of the second shift registers generate a first gate driving signal and a second gate driving signal having an overlap time less than 1/2 and greater than 1/4 of the pulse width according to the timing of the driving signals, in step 301.
Each of the first shift registers and each of the second shift registers transmit the first gate signal and the second gate signal to the plurality of thin film transistors to control the turn-on time of each of the thin film transistors, as shown in step 302.
In addition, assume that the ideal resistance-capacitance delay time (RC delay time) of the gate driving signal 110 is td. To achieve a charge rate of 99%, the following equation (2) must be satisfied:
wherein V G Is the potential of the gate line, V D Is the potential of the data line, V P Is the potential within the pixel, I DS For charging current, C p Is a liquid crystal capacitor, C S Is the pixel capacitance (as shown in fig. 8), and therefore, if it is desired to achieveThe charging rate is 99%, the on-time tg of the gate driving signal required by the thin film transistor 40 is the first effective charging time H1 plus the resistor-capacitor delay time td.
In summary, the present invention provides a dual-side gate driving lcd and a driving method thereof, which can modulate the duty ratio of the signal input to the shift register to 25% preferably, so that the timings of the gate driving signals output by the shift register are not overlapped, thereby preventing the problem of power consumption caused by the simultaneous charging of two pixels when the gate driving signals are overlapped, and further reducing the power consumption of the dual-side gate driving lcd, and in addition, modulate the duty ratio of the signal input to the shift register to be greater than 25% but less than 50%, so that the gate driving signal output by the shift register can start to charge the pixels at a time earlier, thereby solving the problem of insufficient charging rate caused by distortion of the gate driving signal in the transmission process.
Although the foregoing description of the preferred embodiments of the present invention has been provided, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A liquid crystal display of a double-sided gate driving type includes:
the first shift registers receive a driving signal and generate a first grid driving signal corresponding to the time sequence of the driving signal; and
a plurality of second shift registers for receiving the driving signal and generating a second gate driving signal corresponding to the timing of the driving signal;
the driving signals received by the first shift registers and the second shift registers are smaller than 1/2 period pulse width, and the first shift registers and the second shift registers generate first grid driving signals and second grid driving signals with the pulse width smaller than 1/2 period according to the time sequence of the driving signals so as to control the conduction time of the thin film transistors.
2. The liquid crystal display of claim 1, wherein the driving signals comprise a DC reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
3. The liquid crystal display of a dual edge gate driving type as claimed in claim 2, wherein the duty ratio of the driving signal is equal to 25%.
4. The liquid crystal display of dual edge gate driving type as claimed in claim 1, wherein the duty ratio of the driving signal is more than 25% so that the overlapping time of the first gate driving signal and the second gate driving signal is less than 1/2 of a period pulse width.
5. A driving method of a liquid crystal display of a dual gate driving type, the liquid crystal display including a plurality of thin film transistors, a first gate driver having a plurality of first shift registers, and a second driver having a plurality of second shift registers, the driving method comprising:
modulating a duty ratio of a driving signal to be less than 1/2, and inputting the modulated driving signal to the plurality of first shift registers and the plurality of second shift registers;
the plurality of first shift registers and the plurality of second shift registers generate a first gate driving signal and a second gate driving signal with a pulse width less than 1/2 period according to the time sequence of the input driving signal; and
the first shift registers and the second shift registers output the first gate driving signal and the second gate driving signal to the thin film transistors to control the on-time of the thin film transistors.
6. The method according to claim 5, wherein the driving signals include a DC reference voltage, a start pulse signal, a clock signal and an inverted clock signal.
7. The method according to claim 6, wherein the timing of the start pulse signal, the clock signal and the inverted clock signal inputted to the second gate driver is delayed by 1/4 cycle than the timing of the start pulse signal, the clock signal and the inverted clock signal inputted to the first gate driver.
8. The method of driving the liquid crystal display of the dual edge gate driving type as claimed in claim 5, wherein the duty ratio of the driving signal is equal to 25%.
9. The method as claimed in claim 5, further comprising modulating the duty ratio of the driving signal to be greater than 25% to make the overlap time between the first gate driving signal and the second gate driving signal less than 1/2 and greater than 1/4 of the period pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101482497A CN100562780C (en) | 2007-09-04 | 2007-09-04 | The Liquid Crystal Display And Method For Driving of double sided grid drive type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101482497A CN100562780C (en) | 2007-09-04 | 2007-09-04 | The Liquid Crystal Display And Method For Driving of double sided grid drive type |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101122697A true CN101122697A (en) | 2008-02-13 |
| CN100562780C CN100562780C (en) | 2009-11-25 |
Family
ID=39085094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101482497A Active CN100562780C (en) | 2007-09-04 | 2007-09-04 | The Liquid Crystal Display And Method For Driving of double sided grid drive type |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100562780C (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546534B (en) * | 2008-03-26 | 2012-11-21 | 统宝光电股份有限公司 | Device and method for driving displays |
| US8427081B2 (en) | 2009-09-16 | 2013-04-23 | Novatek Microelectronics Corp. | Driving apparatus of light emitting diode and driving method thereof |
| CN103489406A (en) * | 2013-10-08 | 2014-01-01 | 京东方科技集团股份有限公司 | Pixel drive unit, drive method thereof and pixel circuit |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| CN103744206A (en) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | Array base-plate drive circuit, array base-plate and corresponding liquid crystal display |
| CN102026439B (en) * | 2009-09-23 | 2014-11-05 | 联咏科技股份有限公司 | Driving device and driving method for light emitting diode |
| CN105788508A (en) * | 2016-05-24 | 2016-07-20 | 京东方科技集团股份有限公司 | Grid electrode driving circuit and display panel |
| WO2017181700A1 (en) * | 2016-04-18 | 2017-10-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive device, display device and driving method |
| CN107393461A (en) * | 2017-08-30 | 2017-11-24 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method and display device |
| WO2019090908A1 (en) * | 2017-11-07 | 2019-05-16 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and gate drive circuit |
| US10475408B2 (en) | 2017-11-07 | 2019-11-12 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | Liquid crystal display panel with a polarity reversion and gate driving circuit thereof |
| CN111785231A (en) * | 2020-07-09 | 2020-10-16 | 深圳市华星光电半导体显示技术有限公司 | Light sensing driving circuit and driving method thereof, display panel and display device |
| CN114005366A (en) * | 2021-05-27 | 2022-02-01 | 友达光电股份有限公司 | Display device |
| WO2022036844A1 (en) * | 2020-08-19 | 2022-02-24 | 惠科股份有限公司 | Display device and driving method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3535067B2 (en) * | 2000-03-16 | 2004-06-07 | シャープ株式会社 | Liquid crystal display |
-
2007
- 2007-09-04 CN CNB2007101482497A patent/CN100562780C/en active Active
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546534B (en) * | 2008-03-26 | 2012-11-21 | 统宝光电股份有限公司 | Device and method for driving displays |
| US8427081B2 (en) | 2009-09-16 | 2013-04-23 | Novatek Microelectronics Corp. | Driving apparatus of light emitting diode and driving method thereof |
| USRE46330E1 (en) | 2009-09-16 | 2017-02-28 | Novatek Microelectronics Corp. | Driving apparatus of light emitting diode and driving method thereof |
| CN102026439B (en) * | 2009-09-23 | 2014-11-05 | 联咏科技股份有限公司 | Driving device and driving method for light emitting diode |
| CN103489406B (en) * | 2013-10-08 | 2015-11-25 | 京东方科技集团股份有限公司 | A kind of pixel drive unit and driving method, image element circuit |
| CN103489406A (en) * | 2013-10-08 | 2014-01-01 | 京东方科技集团股份有限公司 | Pixel drive unit, drive method thereof and pixel circuit |
| CN103744206B (en) * | 2013-12-27 | 2016-08-17 | 深圳市华星光电技术有限公司 | A kind of array base palte drive circuit, array base palte and corresponding liquid crystal display |
| CN103744206A (en) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | Array base-plate drive circuit, array base-plate and corresponding liquid crystal display |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| CN103700358B (en) * | 2013-12-31 | 2016-06-15 | 合肥京东方光电科技有限公司 | A kind of GIP type liquid crystal indicator |
| US10140938B2 (en) | 2013-12-31 | 2018-11-27 | Boe Technology Group Co., Ltd. | GIP type liquid crystal display device |
| WO2017181700A1 (en) * | 2016-04-18 | 2017-10-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive device, display device and driving method |
| US10204585B2 (en) | 2016-04-18 | 2019-02-12 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving device, display device and driving method |
| US10546519B2 (en) | 2016-05-24 | 2020-01-28 | Boe Technology Group Co., Ltd. | Gate driving circuits and display panels |
| CN105788508A (en) * | 2016-05-24 | 2016-07-20 | 京东方科技集团股份有限公司 | Grid electrode driving circuit and display panel |
| CN107393461A (en) * | 2017-08-30 | 2017-11-24 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method and display device |
| US10475408B2 (en) | 2017-11-07 | 2019-11-12 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | Liquid crystal display panel with a polarity reversion and gate driving circuit thereof |
| WO2019090908A1 (en) * | 2017-11-07 | 2019-05-16 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and gate drive circuit |
| CN111785231A (en) * | 2020-07-09 | 2020-10-16 | 深圳市华星光电半导体显示技术有限公司 | Light sensing driving circuit and driving method thereof, display panel and display device |
| WO2022036844A1 (en) * | 2020-08-19 | 2022-02-24 | 惠科股份有限公司 | Display device and driving method therefor |
| CN114005366A (en) * | 2021-05-27 | 2022-02-01 | 友达光电股份有限公司 | Display device |
| CN114005366B (en) * | 2021-05-27 | 2023-12-08 | 友达光电股份有限公司 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100562780C (en) | 2009-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101122697A (en) | Double sided grid drive type liquid crystal display and its driving method | |
| EP3086312B1 (en) | Shift register unit, gate drive circuit and display device | |
| JP4713246B2 (en) | Liquid crystal display element | |
| JP6240787B2 (en) | GOA circuit structure | |
| CN202838908U (en) | Grid driving circuit, array substrate and display device | |
| KR101143531B1 (en) | A gate drive device for a liquid crystal display | |
| CN104050935B (en) | Shift register, bi-directional shift apparatus for temporary storage and apply its display panels | |
| CN102456331B (en) | Liquid crystal display | |
| CN104485065A (en) | Shifting register, driving method and gate driving circuit | |
| CN103280201B (en) | Gate drive apparatus and display device | |
| JP5346741B2 (en) | Shift register, gate driver having the shift register, liquid crystal display device, and method for generating pulse as gate drive signal | |
| CN110956919A (en) | Shift register circuit, driving method thereof, gate driving circuit and display panel | |
| US20110157148A1 (en) | Circuit driving for liquid crystal display device | |
| JP4109186B2 (en) | Driving circuit for liquid crystal display gate driver | |
| WO2017124731A1 (en) | Shift register, drive method thereof, goa circuit, and display device | |
| CN105741744A (en) | Shifting register unit, grid driving circuit and display device | |
| KR102199930B1 (en) | Gate driver ic and control method thereof | |
| US11081033B2 (en) | Shift register unit and driving method thereof, gate driver, display panel and display device | |
| JP2009258733A (en) | Method and device for driving liquid crystal display | |
| CN111583880B (en) | Shift register unit circuit, driving method, gate driver and display device | |
| US9318218B2 (en) | Shift register and driving circuit for liquid crystal display | |
| WO2019223754A1 (en) | Shift register unit and driving method therefor, and gate driver, display panel and display apparatus | |
| EP3916712A1 (en) | Driving method for display device, and display device | |
| US20080231329A1 (en) | Differential signal output circuit for timing controller of display device | |
| CN103514840A (en) | Integrated gate driving circuit and liquid crystal panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |