CN101120562A - Context-based operation reconfigurable instruction set processor and method of operation - Google Patents
Context-based operation reconfigurable instruction set processor and method of operation Download PDFInfo
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Abstract
A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a-b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output which are respectively equal to one of: 1) the sum (a+b) multiplied by one of +1 and -1 and 2) the difference (a-b) multiplied by one of +1 and -1.
Description
Background technology
Almost all using data processor in every type the modern electronic equipment, comprise consumer electronics, industrial machinery, science device and communication network.Yet the performance and the complexity of the data processor that uses in different application (or microprocessor) may be very different.The speed of application-specific and Capability Requirement are very important for the type of determining employed data processor.
The type particular importance of employed data processor in software-defined radio (SDR) is realized.SDR equipment uses can be from the reconfigurable hardware of aerial programming to work under different wireless protocols.For example, the SDR transceiver in the wireless laptop computer can be configured to work in the IEEE-802.11x wireless network by first software load, also can is configured to work in the CDMA2000 wireless network by second software load.
Data processor commonly used has six kinds of main types: ASIP application-specific integrated circuit (ASIC) and 6 complex instruction set computer (CISC), 4 Reduced Instruction Set Computer, 3 1) digital signal processor, 2))) field programmable gate array, 5)).In the data processor of these types each all has specific advantage and specific deficiency.
Digital signal processor (DSP) is to optimize the general processor that is used for carrying out expeditiously such as the Digital Signal Processing operation of the multiplication that is used for finite impulse response (FIR) (FIR) filtering-add up operation and fast Fourier transform (FFT) operation.DSP realizes the exquisite addressing mode of many complexity to tackle many kinds of DSP calculation requirements, such as the bit reversal addressing mode that is used for FFT, be used for indexed addressing of FIFO equipment or the like.The example of DSP comprises: 1) Motorola 56000,56300, SC81xx and MRC6011 processor; 2) C55 of Texas Instrument (TI), C6203, C6416 and C67xx processor; 3) ADI (Analog Devices Inc) Sharc and TigerSharc processor; And 4) the reconfigurable DSP of the MS1-64 of Morpho.
Reduced Instruction Set Computer (RISC) is the general processor (GPP) that is primarily aimed at the control application of using such as medium access control (MAC).The main advantage of RISC machine is its simplicity.As its name, risc processor has the small instruction collection, and it provides higher code density and the reaction of stream change faster.The example of RISC device comprises: 1) arm processor (for example, ARM926, ARM1136J); 2) MIPS processor (for example, MIPS32, MIPS64); 3) IBM (International Business Machines Corporation) PowerPC 405 and 750FX; And 4) PowerPC of Motorola 603.
Complex instruction set computer (CISC) (CISC) device is the general processor of using at the many-side of using from the multimedia application to PC (GPP).The example of cisc processor comprises: 1) intel pentium; And 2) Motorola 68000.
Field programmable gate array (FPGA) is based on the reconfigurable hardware device of the array of the hardware cell that is connected with local bus by long bus.The FPGA device is very commonly used in wireless network base station application and prototype (prototype).The example of FPGA device comprises: 1) Xilinx Virtex IV; And 2) Altera Stratix II.
Application-specific integrated circuit (ASIC) (ASIC) is to be the custom-designed hardware device of application-specific.The power efficiency of ASIC is very high usually.Use the ASIC device in many wireless devices (that is cell phone or the like).ASIP (ASIP) is to have added the more ASIC device of the enhanced edition of plurality of programmable performance to ASIC hardware.
In the above-mentioned processor each all has specific advantage and specific deficiency is arranged.From the software angle, in order to satisfy software-defined radio (SDR) requirement, digital signal processor is the processor of flexible type.Yet the DSP device does not have enough MIPS performances and framework is handled to satisfy 3G and 4G bit rate processing requirements in the position.Risc processor is used at control, but is not enough to exceed the base-band application that is used for the wireless network realization.Cisc processor can have flexibility and the MIPS performance that is used to handle base-band application, but their low power efficiencies make them be not suitable for the Power Limitation of handheld device.The same with cisc processor, the FPGA device can satisfy needed MIPS performance, but their low power efficiencies make them be not suitable for handheld device design.
The ASIC device extremely meets the power and the cost restriction of handheld device design.Yet their flexibility is too limited so that make them be not suitable for the SDR realization.The ASIP device is by adding more programmability and realizing the flexibility higher than ASIC device by introducing instruction set processor to described hardware to described specialized hardware.Yet because ASIP is a general-purpose device, their processor core cardiac efficiency depends on handled application.Control routine in the described application is many more, and the efficient of ASIP will be low more.This causes low performance and higher power consumption.
The other deficiency of prior art processor is scalability and modularity.The purpose of creating software-defined radio (SDR) method is for cost (design time, TTM) with power consumption minimizes and with maximum flexibility.The prior art processor realizes failing providing the combination of the optimization of scalability and modularity.
Because must make compromisely between the Consideration of vying each other of energy efficiency, computing capability and flexibility comprising, there be intrinsic difficulty in the data processor that is designed in the mobile station.Most current multistandard wireless equipment comprise discrete and ASIC device blocks independently to a great extent, and wherein each relates to different wireless standards.With the ASIC device stack of separating together so that the support to several wireless standards to be provided simultaneously.Because increased tube core (die) size, increased power and lacked flexibility, this clumsy method causes serious unfavorable result.On the other hand, general dsp and similar framework have many flexibilities.Yet these devices have high power consumption and can not satisfy the real-time calculation requirement of most wireless standards usually.
Because the consideration of power and performance, traditional mobile station (or wireless terminal) is based on a plurality of ASIC devices.Notice that these ASIC devices only are exclusively used in the specific function in the described system usually.For example, in the traditional Wideband Code Division Multiple Access (WCDMA) of majority (WCDMA) mobile station, use ASIC piece separately usually for correlator function and Cell searching function, even two pieces are very similar.If can use identical reconfigurable hardware to realize two kinds of functions as much as possible, then such scheme will more have power efficiency and will use littler die-size.
Thereby this area needs a kind of cost and minimized improved software-defined radio (SDR) framework that keeps flexibility simultaneously of power consumption of making.Especially, need a kind of reconfigurable associative cell that is used for software-defined radio (SDR) wireless device.
Summary of the invention
The invention provides reconfigurable associative cell, it can be to realize based on the reconfigurable instruction set processor of contextual operation.Associative cell according to principle of the present invention meets the framework of application domain (domain) and optimizes performance and power jointly.Therefore, the present invention satisfies the real-time processing requirements and the low power requirements at radio mobile station station simultaneously.Advantageously, described associative cell is highly reconfigurable, and can be used for CRISP and be operated in different functional block under the various criterion, comprise that cdma system separates spread spectrum, IEEE-802.11b CCK demodulation, WCDMA and separate spread spectrum, Cell searching, HSDPA and separate spread spectrum or the like.
In order to tackle above-mentioned deficiency of the prior art, primary and foremost purpose of the present invention provides a kind of reconfigurable associative cell that is used for the sequence of related chip sample.According to an advantageous embodiment of the invention, described associative cell comprises: 1) memory is used to store the sequence of described chip sample; 2) a plurality of adding-subtract element, wherein, each described adding-subtract element can first chip sample from described memory receive a plurality of real parts position a and receive a plurality of imaginary parts position b from described first chip sample; And 3) processing unit comprises a plurality of symbol selected cells.Second the importing of poor (a-b) that each described symbol selected cell equals first input described a plurality of real parts position a and described a plurality of imaginary parts position b and (a+b) and equals described a plurality of real parts position a and described a plurality of imaginary parts position b from described a plurality of adding-subtract one of them reception of element.Each symbol selected cell generates real part output and imaginary part output, wherein, each of output of described real part and the output of described imaginary part equal following one of them: 1) multiply by+1 and-1 one of them and (a+b) and 2) multiply by+1 with-1 one of them poor (a-b).
According to one embodiment of present invention, described associative cell further comprises code generator, it is used for the sequence of generated code position, wherein, described each symbol selected cell receives real part sign indicating number position and the imaginary part sign indicating number position from described sequence, and wherein, the real part output valve and the imaginary part output valve of described each symbol selected cell determined in described real part and imaginary part sign indicating number position.
According to another embodiment of the invention, described processing unit further comprises the first adder level, and it comprises more than first real part adder and more than first imaginary part adder.
According to another embodiment of the invention, each described more than first real part adder receives from first real part output of one of them output of described a plurality of symbol selected cell and from wherein second real part output of another output of described a plurality of symbol selected cells, and produces real part and output.
According to another embodiment of the invention, each described more than first imaginary part adder receives from first imaginary part output of one of them output of described a plurality of symbol selected cell and from wherein second imaginary part output of another output of described a plurality of symbol selected cells, and produces imaginary part and output.
According to another embodiment of the invention, described processing unit further comprises the second adder level, and it comprises at least one real part adder and at least one imaginary part adder.
According to another embodiment of the invention, in at least one real part adder in the described second level each receives from first real part of one of them output of described more than first real part adder and output and from wherein second real part and the output of another output of described more than first real part adder, and produces real part and output.
According to another embodiment of the invention, in at least one imaginary part adder in the described second level each receives from first imaginary part of one of them output of described more than first imaginary part adder and output and from wherein second imaginary part and the output of another output of described more than first imaginary part adder, and produces imaginary part and output.
According to another embodiment of the invention, a kind of reconfigurable unit that is used to handle a plurality of contexts instructions comprises: a plurality of processors are used to carry out each predetermined specific context instruction; Program storage is used for the control program of storage from outside CONTROL (control) line; Serial device is used for obtaining program command from described program storage, sends to corresponding processor in described a plurality of processor with the context ordering and with described context through ordering as reconfiguring the position; And be connected interconnect fabric between each and outside DATA (data) bus of described a plurality of processors, be used for data are sent to the corresponding processor of described a plurality of processor from described data/address bus.
Below carrying out before the detailed description of the present invention, the definition of setting forth some words that this patent file uses in full and phrase is with helpful: term " comprise " and " comprising " with and derivative mean hard-core comprising; Term " or " comprise, mean and/or; Phrase " with ... contact " and " getting in touch " with it with and growth can mean and comprise, be included in ... interior, with ... interconnect, hold, be contained in ... interior, be connected to or with ... connect, be couple to or with ... couple, with ... communication, with ... cooperate, interweave, side by side, approach, be attached to or with ... combination, have, have ... attribute or the like; And term " controller " means any equipment, system or its part of controlling at least one operation, and such equipment can be implemented as hardware, firmware or software, perhaps at least wherein certain combination of two.Should be noted that the function of getting in touch with any specific controller can be concentrate or distribute, no matter local ground or remotely.This patent file provides the definition of some words and term in full, it should be understood by one skilled in the art that under many (if not great majority) situation, such definition can be applied to the words of definition like this and phrase in the past with the use in future.
Description of drawings
In order more completely to understand the present invention and advantage thereof, the explanation below setting forth in conjunction with the accompanying drawings now, the wherein similar similar part of reference numerals designate:
Fig. 1 is the block diagram according to the conventional data processor of the one exemplary embodiment of prior art;
Fig. 2 illustrates finite state machine (FSM) table of data processor;
Fig. 3 be with Fig. 2 in the corresponding bubble diagram of described finite state machine table;
Fig. 4 is the bubble diagram based on contextual grouping that illustrates according to the state in the described finite state machine table among Fig. 2 of one exemplary embodiment of the present invention;
Fig. 5 is the high level block diagram based on the reconfigurable instruction set processor of contextual operation according to one exemplary embodiment of the present invention;
Fig. 6 is the high level block diagram according to comprising of one exemplary embodiment of the present invention of a plurality of reconfigurable treatment systems based on the reconfigurable instruction set processor of contextual operation;
Fig. 7 is the high level block diagram that comprises a plurality of many standard softwares defined radio (SDR) systems based on the reconfigurable instruction set processor of contextual operation according to an embodiment of the invention;
Fig. 8 is the block diagram of associative cell according to an embodiment of the invention;
Fig. 9 is the block diagram of the memory in the described associative cell according to an embodiment of the invention;
Figure 10 A illustrates in greater detail and adds-subtract element according to one exemplary embodiment of the present invention;
Figure 10 B illustrates in greater detail the symbol selected cell according to one exemplary embodiment of the present invention;
Figure 10 C is the flow chart of explanation according to the operation of the described associative cell of principle of the present invention;
Figure 11 explanation data of the described associative cell among Fig. 8 output during selected operational cycle according to one embodiment of present invention;
Figure 12 explanation data of the described associative cell among Fig. 8 output during the WCDMA cell search according to one embodiment of present invention.
Embodiment
The various embodiment that are used to illustrate principle of the present invention below in Fig. 1 to 12 that discusses and this patent file should not be read as in any form as just the explanation demonstration scope of the present invention is limited.It will be understood by those skilled in the art that principle of the present invention can realize with any treatment system of suitably arranging.
Fig. 1 is the high level block diagram according to the conventional data processor 100 of the one exemplary embodiment of prior art.Fig. 1 has described the general realization of the application in the hardware and software.Data processor 100 comprises memory 110 and control circuit 120.Control circuit 120 further comprises mixing controls finite state machine (FSM) circuit and data-path circuit.Memory 110 further comprises N memory block, comprises demonstrative memorizer piece 111-113, and it is labeled as memory 1, memory 2 and memory N randomly.
Any data processor is used one group of data path that can be counted as by finite state machine (FSM) control and scheduling, as shown in Figure 1.Finite state machine receives incoming event, and migration and/or generation output between state in response.Described FSM decides which state of moving to based on current state and the incoming event that is received.
Fig. 2 illustrates finite state machine (FSM) table 200 of exemplary data processor.FSM table 200 is described the NextState migration carried out based on current state (that is one of state S1-S10) and the incoming event (that is one of incident E1-E7) that received by FSM.Originally, described FSM is in state S1.The row indicating status S1 of state S1 is in response to the state transition of incident E1 to E4.
During state S1, in response to the incident E1 that is received, described FSM is moved to state S9 from state S1.During state S1, in response to the incident E2 that is received, described FSM is moved to state S2 from state S1.During state S1, in response to the incident E3 that is received, described FSM is moved to state S2 from state S1.During state S1, in response to the incident E4 that is received, described FSM is moved to state S10 from state S1.
Can be clear that have many in the FSM table 200 not by the cavity of assignment from Fig. 2.For example, for state S1, be not incident E5-E7 assignment.In the prior art data processor, these cavities must be provided, although they are to the not contribution of stream of described finite state machine, otherwise described finite state machine can not correctly be worked.In the prior art data processor, can't further optimize described finite state machine to eliminate these cavities.
Fig. 3 illustrates bubble diagram 300, and it is corresponding with described finite state machine table among Fig. 2.Represent each state S1-S10 with bubble, and incident E1-E7 causes the migration between the state.Represent these migrations with the arrow line that connects described state bubble.Described arrow is determined the direction of described migration.
Notice, in bubble diagram 300, can be according to the context of performance element with status packet.For the disclosure, context is the one group operation relevant with same function and/or instructs.Fig. 4 illustrates bubble diagram 400, and principle wherein according to the present invention is divided into groups the state with same context-sensitive in the described finite state machine table among Fig. 2.The described grouping of state forms context C0, C1, C2, C3 and C4.
Each of status packet among Fig. 4 can be used for creating based on the reconfigurable instruction set processor of contextual operation (CRISP) according to principle of the present invention.Each context C0-C4 comprises incoming event and one group of possible operation of minimum number.Each context has the data path of himself equally, and it can comprise parallel execution unit, and described instruction set is carried out and can be carried out with VLIW, SIMD, microcode or other known implementation, to improve overall performance.
Fig. 5 is the high level block diagram based on the reconfigurable instruction set processor of contextual operation (CRISP) 500 according to one exemplary embodiment of the present invention.CRISP 500 comprises memory 510, division of programmable data path circuitry 520, programmable finite state machine 530 and optional procedure memory 540.CRISP500 is designed to only to realize in the best way the subclass of instruction of the context-sensitive of Fig. 4.Each context C0-C4 among Fig. 4 can use the CRISP realization similarly independent with CRISP 500.The typical hardware piece of more senior hardware processor piece is formed in 500 definition usually based on the reconfigurable instruction set processor of contextual operation (CRISP).To CRISP 500 favourable principles is that CRISP 500 is decomposed into two main territories with required application: control domain and data path domain, and optimize each territory separately.By using CRISP 500 (for example to realize such as the mobile station handheld device, cell phone, wireless laptop computer) data processor use, the present invention has overcome at least in part on the spot influencing " flexibility is to power " problem that conventional data processor is used.
Described control domain realizes that by programmable finite state machine 530 it can comprise DSP, MCU or other prior art device.Utilization comes configurating programmable FSM 530 from the position that reconfigures that the peripheral control unit (not shown) receives.FSM 530 able to programme can carry out the program that is stored in the relevant optional procedure memory 540.Described program can be stored in the program storage 540 via data wire from the peripheral control unit (not shown).Memory 510 is used to store the application data of being used by data-path circuit 520.
Division of programmable data path circuitry 520 is divided into one group of building block (for example, register, multiplexer, multiplier or the like) of carrying out specific function.Each building block be reconfigurable be again programmable, to allow maximum flexibility.The criterion that is used for division of programmable data path circuitry 520 is divided into functional block depends on the required reconfigurable property of application-specific and the degree of programmability.
Because each the context C0-C4 among Fig. 4 realizes that by the independent CRISP 500 that works alone with other CRISP the invention provides a kind of high efficiency power management scheme, it can close described CRISP when not needing CRISP to carry out.This guarantees only to have those to activate at the needed CRISP of given time, and other idle CRISP consumed power not substantially.
CRISP according to principle of the present invention can include, but are not limited to base-band application and multimedia application in the wireless device at many application.In many application, these contexts can be the independent contexts of loosely coupling, its can with minimum or do not have dependence to move concomitantly.
Fig. 6 is the high level block diagram according to the reconfigurable treatment system 600 of one exemplary embodiment of the present invention.Reconfigurable treatment system 600 comprises that N comprises exemplary CRISP 500a, 500b and 500c based on the reconfigurable instruction set processor of contextual operation (CRISP), is labeled as CRISP 1, CRISP 2 and CRISP N randomly with it.Reconfigurable treatment system 600 further comprises real-time serial device 610, sequencer program memory 620, programmable interconnect structure 630 and buffer 640 and 645.
Can be loaded into CRISP 500a, 500b and the 500c via real-time serial device 610 and buffer 640 from CONTROL (control) line reconfiguring the position.Control program can also be loaded into the sequencer program memory 620 via buffer 640 from the CONTROL line.In real time serial device reconfigures the position and to being sorted by the described context that each CRISP 500a-500c carries out by obtaining program command from program storage 620 and sending to CRISP 500a-500c.In an exemplary embodiment, in real time serial device 610 can comprise stack processor, and it is suitable as the work of Real-Time Scheduling device owing to its low latency and simplicity.
In an exemplary embodiment, reconfigurable treatment system 600 can be for example cell phone or similarly wireless device or be used for the data processor of laptop computer.In the wireless device embodiment that realizes according to software-defined radio (SDR) principle, each CRISP 500a-500c is responsible for carrying out the subclass with the instruction of the context-sensitive of specific reconfigurable functional cohesion.For example, CRISP 500a can be configured to carry out the instruction of the context-sensitive of handling CDMA baseband signal or OFDMA baseband signal.CRISP 500b can be configured to carry out the instruction of the context-sensitive of serving as Memory Controller.CRISP 500c can be configured to the instruction of the context-sensitive that the complete MPEG-4 that is used for multimedia application handles.
CRISP according to principle of the present invention provides a kind of new way that realizes the reconfigurable hardware speed technology.The present invention provides reconfigurable property and programmability with minimal power efficient sacrifice.Because described CRISP is highly independent and can move simultaneously, the present invention has the performance advantage of concurrency and don't causes and move the relevant unfavorable result of high power of parallel work-flow.The loose couplings of CRISP allows them to be arranged to different systems and the function that can be closed separately with independence.
Fig. 7 is the high level block diagram that comprises a plurality of many standard softwares defined radio (SDR) systems 700 based on the reconfigurable instruction set processor of contextual operation according to an embodiment of the invention.SDR system 700 can comprise the wireless terminal (or mobile station) of access of radio network, such as, for example GSM or cdma cellular telephone, have PDA of WCDMA or IEEE-802.11x ability or the like.
Many standards SDR system 700 comprises baseband subsystems 701, application subsystem 702, memory interface (IF) and peripheral subsystem 765, main control unit (MCU) 770, memory 775 and connectors (interconnect) 780.MCU 770 can comprise for example traditional microcontroller or microprocessor (for example, x86, ARM, RISC, DSP or the like).Memory I and peripheral subsystem 765 can be connected to SDR system 700 the external memory storage (not shown) and be connected to the external peripheral (not shown).Memory 775 storage is from other assembly in the SDR system 700 and from the data of external equipment (not shown).For example, memory 775 can be stored the input sample of data stream that receives from the exterior antenna system that gets in touch with SDR system 700 and RF low-converter.Connectors 780 provides transfer of data between subsystem 701,702, memory I and peripheral subsystem 765, MCU 770 and memory 775.
In such one exemplary embodiment, conversion CRISP 500d can receive the sample of intermediate frequency (IF) signal that is stored in the memory 775, and carries out the FFT function that generates the chip sample sequence with base band speed.Then, spreading rate CRISP 500e receives the described chip sample of transformation into itself CRISP 500d, and carries out the correlation function that generates data symbol sequence.Next, character rate CRISP 500f receives the described symbol data from spreading rate CRISP 500e, and carries out Veterbi decoding to restore described baseband user data.Described baseband user data can then be used by application subsystem 702.
In one exemplary embodiment of the present invention, character rate CRISP 500f can comprise two or more CRISP of parallel running.Equally, as example, BMU CRISP 500g can realize such as variable length code, Cyclic Redundancy Check, convolutional encoding or the like function.Connectors 725 provides transfer of data between RT serial device 705, memory 710, base band DSP subsystem 715 and CRISP 500d-500g.
In the one exemplary embodiment shown in Fig. 7, the use of CRISP device makes it possible to the application subsystem 702 of many standards SDR system 700 is reconfigured to support to have multiple a plurality of video standards of joining type and size.In addition, the use of CRISP device makes it possible to the baseband subsystems 701 of many standards SDR system 700 is reconfigured to support a plurality of aerial (air) interface standards.Therefore, SDR system 700 can work in dissimilar wireless network (for example, CDMA, GSM, 802.11x or the like), and can play dissimilar videos and audio format.Yet principle according to the present invention makes SDR system 700 to carry out these functions with the power consumption more much lower than the legacy wireless devices with similar ability to the use of CRISP.
More specifically, the invention provides a kind of can be with the reconfigurable associative cell of realizing based on the reconfigurable instruction set processor of contextual operation.Advantageously, associative cell according to principle of the present invention is highly reconfigurable, and can be used to be operated in different substandard different functions and determine, comprise that CDMA separates spread spectrum, IEEE-802.11b CCK demodulation, WCDMA and separates spread spectrum, Cell searching, HSDPA and separate spread spectrum or the like.
Fig. 8 is the block diagram of reconfigurable associative cell 800 according to an embodiment of the invention.For example, associative cell 800 can be embodied as the part of spreading rate CRISP 500e.Associative cell 800 comprises three major parts: data storage 830, code generator (CG) 835 and processing unit.In described one exemplary embodiment, described processing unit is implemented as two sub-pieces of essentially identical processing, promptly descends processing unit (PU) 801 and last processing unit (PU) 802.Associative cell 800 comprises that further yard bus 840, data/address bus 845 and four add-subtract (+/-) element (cell) (that is, adding-subtract element 850a-850d).
Following processing unit 801 comprises four symbol selected cells (promptly, symbol selected cell 805a-805d), four first order adders (promptly, adder 810a-810d), multiplexer (MUX) 815a and 815b, two second level adders (that is, adder 820a and 820b), accumulator 825a and 825b and output bus 830.Last processing unit 802 comprises four symbol selected cells (promptly, symbol selected cell 855a-855d), four first order adders (promptly, adder 860a-860d), multiplexer (MUX) 865a and 865b, two second level adders (that is, adder 870a and 870b), accumulator 875a and 875b and output bus 880.
Following processing unit 801 and last processing unit 802 are worked independently.According to one exemplary embodiment of the present invention, sign indicating number bus 840, data/address bus 845 and output bus 830 and 880 are one-way bus.Further, in advantageous embodiment of the present invention, output bus 830 and output bus 880 can be same buses.Reason for this reason below only is called " output bus 830 " with output bus 830 and output bus 880.Data/address bus 830 will send to processing unit 801 and 802 via element 850a-850d from the described chip sample data of data storage 830.Output bus 830 will be write data storage 830 from the dateout of accumulator 825a and 825b and accumulator 875a and 875b.The described code data that sign indicating number bus 840 will generate in code generator 835 is sent to processing unit 801 and 802.
It should be noted that, processing unit 801 and 802, memory 830, code generator 835 and bus 830,840,845 can be arranged to different standards and function with 880, comprise that CDMA separates spread spectrum, IEEE-802.11b CCK demodulation, WCDMA and separates spread spectrum, Cell searching, HSDPA and separate spread spectrum or the like.Further, can close each functional unit and each bus independently.Shown in Fig. 8 and the quantity of the width of the quantity of the element of describing 850, data storage 830 and symbol selected cell 805 and 855 as just example.As below seeing, under the prerequisite that does not deviate from scope of the present invention, the size of processing unit 801 and 802 quantity and element 850, data storage 830 and symbol selected cell 805 and 855 can change (increase or reduce) to some extent.
Fig. 9 is the block diagram of the data storage 830 in the associative cell 800 according to an embodiment of the invention.From described receiver front end (not shown) through the RF of down-conversion signal capture chip sample, and it is stored in four memory banks (that is, memory bank 0, memory bank 1, memory bank 2 and memory bank 3) in the memory 830.With dashed lines arrow indication is stored in order and mode in the memory 830 with described chip sample.Described order and mode are according to the amount of the over-sampling of described chip data and change to some extent.
Among Fig. 9, suppose each chip samples of CDMA walsh code four times, and with four samples write memory 830 successively.So, with from N chip C (0) altogether to 4 * N the chip sample write memory 830 of C (N-1).To the first chip C (0) sampling four times, and four sample C (0,0), C (0,1), C (0,2) and C (0,3) are write address AD D0, ADD4, ADD8 and ADD 12 in the memory bank 0 of entry data memory 830 respectively.Similarly, to the second chip C (1) sampling four times, and four sample C (1,0), C (1,1), C (1,2) and C (1,3) are write address AD D1, ADD5, ADD9 and ADD13 in the memory bank 1 of entry data memory 830 respectively.To the 3rd chip C (2) sampling four times, and four sample C (2,0), C (2,1), C (2,2) and C (2,3) are write address AD D2, ADD6, ADD10 and ADD14 in the memory bank 2 of entry data memory 830 respectively.At last, to the 4th chip C (3) sampling four times, and four sample C (3,0), C (3,1), C (3,2) and C (3,3) are write address AD D3, ADD7, ADD11 and ADD15 in the memory bank 3 of entry data memory 830 respectively.
Like this, will the forth day of a lunar month chip C (0), 16 samples of C (1), C (2) and C (3) write 16 addresses from ADD0 to ADD15.Repeat this process, next 16 samples of four chip C (4), C (5), C (6) and C (7) write next 16 addresses from ADD16 to ADD31.This process continues, up to writing entry data memory 830 from 16 samples of last four chip C (N-4), C (N-3), C (N-2) and C (N-1).
In the top example, suppose that over-sampling rate is four.Yet described over-sampling rate can change between different wireless standards to some extent.In different configurations, described over-sampling rate can be eight, wherein with the similar mode shown in Fig. 9 will be from eight samples of each chip with the degree of depth eight write memories 830.In other configuration, described over-sampling rate can be two, wherein with the similar mode shown in Fig. 9 will be from two samples of each chip with the degree of depth two write memories 830.In other configuration, described over-sampling rate can be every chip once, wherein with the similar mode shown in Fig. 9 will be from a sample write memory 830 of each chip.
The width of each chip sample can be according to employed wireless standard (for example, QPSK, 16QAM) and change to some extent, and each chip sample can comprise real part and imaginary data position the two.For example, in the first embodiment of the present invention, each chip sample can be eight positions, comprises four real part positions and four imaginary part positions.In the second embodiment of the present invention, each chip sample can be four positions, comprises two real part positions and two imaginary part positions.
In the time will in processing unit 801 and 802, handling described chip sample, four chip sample are read on the data/address bus 845 from memory 830 at every turn.For example, read cycle period first, the address AD D0 to ADD3 from memory bank 0, memory bank 1, memory bank 2 and memory bank 3 reads chip sample C (0,0), C (1,0), C (2,0), C (3,0) concurrently respectively.In second reading cycle period, the address AD D4 to ADD7 from memory bank 0, memory bank 1, memory bank 2 and memory bank 3 reads chip sample C (0,1), C (1,1), C (2,1), C (3,1) concurrently respectively.So, four chip sample are outputed on the bus 845, up to having read whole chip sample at every turn.
After reading each chip sample from memory 830, it is loaded into-subtracts in one of them of element 850a-850d.For example read cycle period, chip sample C (0,0) is input to adds-subtract element 850a first, chip sample C (1,0) is input to adds-subtract element 850b, with chip sample C (2,0) is input to and adds-subtract element 850c, and chip sample C (3,0) is input to adds-subtract element 850d.In second reading cycle period, chip sample C (0,1) is input to adds-subtract element 850a, chip sample C (1,1) is input to adds-subtract element 850b, with chip sample C (2,1) is input to and adds-subtract element 850c, and chip sample C (3,1) is input to adds-subtract element 850d.So, four chip sample are input at every turn and add-subtract element 850a-850d, up to having loaded whole chip sample.
Figure 10 A illustrates in greater detail exemplary adding according to one exemplary embodiment of the present invention-subtract element 850.Add-subtract element 850 and comprise adder unit and subtrator.Add-subtract element 850 and receive two input a and b, and produce described two inputs and (a+b) and poor (a-b).Among Fig. 9, each a input that adds-subtract element 850a-850d receives the real part position of chip sample, and each adds-and the b input that subtracts element 850a-850d receives the imaginary part position of chip sample.
Then will add from each-subtract element 850a-850d's and (a+b) output and poor (a-b) output be applied to down in the processing unit 801 the first symbol selected cell 805 and on the input of the second symbol selected cell 855 in the processing unit 802.For example, will from add-subtract element 850a's and (a+b) output and poor (a-b) output all be applied to down in the processing unit 801 symbol selected cell 805a and on the input of symbol selected cell 855a in the processing unit 802.Each symbol selected cell also receives two sign indicating number positions that generated by code generator 835 from sign indicating number bus 840.The sequence of described yard position can dispose wireless standard and the change to some extent that is used for according to associative cell 800.
In one exemplary embodiment of the present invention, code generator 835 can comprise two assemblies: two local circulation (1ocal circular) memories 1) scrambled code maker and 2).Described scrambled code maker is used for some system, as CDMA.Described local circulating memory is preserved the spreading code in the cdma system.These assemblies also can be used to store some predefined pattern, as in the WCDMA Cell searching.When not using described scrambled code maker, it can be stopped using (disable).For example, according to one exemplary embodiment of the present invention, can in the following manner 16 sign indicating number positions from code generator 835 be applied to eight symbol selected cell 805a-805d and 855a-855d:
U
r0U
i0L
r0L
i0U
r1U
ilL
r1L
i1U
r2U
i2L
r2L
i2U
r3U
i3L
r3L
i3，
Wherein, U
RjBe j real part sign indicating number position at last processing unit 802, U
IjBe j imaginary part sign indicating number position at last processing unit 802, L
RjBe j real part sign indicating number position at following processing unit 801, and L
IjBe j imaginary part sign indicating number position at following processing unit 801.So, for example, with initial two sign indicating number position U
R0And U
I0Be applied to symbol selected cell 855a, and incite somebody to action next two sign indicating number position L
R0And L
I0Be applied to symbol selected cell 805a.
Figure 10 B illustrates in greater detail the truth table according to the operation of the symbol selected cell 805a-805d of one exemplary embodiment of the present invention and 855a-855d.Each symbol selected cell 805a-805d and 855a-855d receive from add-subtract unit 850a-850d one of them and (a+b) input and poor (a-b) import.Each symbol selected cell 805a-805d and 855a-855d also receive real part code generator position CG (Re) and imaginary part code generator position CG (Im).In response, each symbol selected cell 805a-805d and 855a-855d produce real part output Output (Re) and imaginary part output Output (Im) according to the value of described real part and imaginary part code generator position.
For example, if symbol selected cell 855a receives input CG (Re)=U
R0=1 and the input CG (Im)=U
I0=0, the real part of then symbol selected cell 855a and imaginary part are output as Output (Re)=(a+b) and Output (Im)=(a-b).In essence, each element 850a-850d produce and and difference (a+b) and (a-b), follow each symbol selected cell 805a-805d and 855a-855d and depend on the value CG (Re) of corresponding real part and imaginary part code generator position and CG (Im) and multiply by+1 or-1 with (a+b) with (a-b).
Then will be applied to first order adder 810a-810d and 860a-860d from the real part of each symbol selected cell 805 and 855 and each among imaginary part output Output (Re) and the Output (Im).For example, the first input end of real part (Re) adder 810a will be applied to from the real part output Output (Re) of symbol selected cell 805a, and the first input end of imaginary part (Im) adder 810b will be applied to from the imaginary part output Output (Im) of symbol selected cell 805a.Similarly, second input of real part (Re) adder 810a will be applied to from the real part output Output (Re) of symbol selected cell 805b, and second input of imaginary part (Im) adder 810b will be applied to from the imaginary part output Output (Im) of symbol selected cell 805b.
The then real part and the imaginary part that will produce by first order adder 810a-810d and 860a-860d and be applied to multiplexer 815a-815b and 865a-865b.For example, MUX 815a receive the real part that produces by adder 810a and, and receive the imaginary part that produces by adder 810b and.Multiplexer 815a, 815b and 865a, 865b are then with described real part and or described imaginary part and be applied to second level adder 820a, 820b and 870a, 870b.For example, real part (Re) adder 820a receives by the real part of adder 810a generation with as first input from MUX 815a, and receives by the real part of adder 810c generation with as second input from MUX 815b.Similarly, imaginary part (Im) adder 820b receives by the imaginary part of adder 810b generation with as first input from MUX 815a, and receives by the imaginary part of adder 810d generation with as second input from MUX 815b.
In following processing unit 801, will produce by real part adder 820a and be added on the value among the real part accumulator 825a, and will produce by imaginary part adder 820b and be added on the value among the imaginary part accumulator 825b.In last processing unit 802, will produce by real part adder 870a and be added on the value among the real part accumulator 875a, and will produce by imaginary part adder 870b and be added on the value among the imaginary part accumulator 875b.
Figure 10 C describes flow chart 1000, and it has been summarized according to processing unit 801 in the associative cell 800 of principle of the present invention and 802 operation.For for purpose of brevity, will suppose in Figure 10 C, discuss under processing unit 801.Originally, four chip sample are read in processing unit 801 (treatment step 1005) from memory 830.Then, add-subtract that element 850a-850d produces and (a+b) value and poor (a-b) value (treatment step 1010).According to revising described from the sign indicating number position of code generator 835 and and the symbol of difference.Then, first order addition (treatment step 1015) takes place.Described first order addition will be reduced to two real parts and value from four real part inputs of symbol selected cell 810a-810d, and will be reduced to two imaginary parts and value from four imaginary part inputs of symbol selected cell 810a-810d.
Then, second level addition (treatment step 1020) takes place.Described second level addition will and be reduced to a real part and value from two real parts of first order adder, and will and be reduced to an imaginary part and value from two imaginary parts of first order adder.The described real part and imaginary part and (treatment step 1025) that then add up individually and produce by second level adder.At last, when the whole chips in the symbol being added to accumulator 825a and 825b, with the value among accumulator 825a and the 825b via bus 830 write memories 830.
Notice,, can have the spreading factor of change according to the type of employed wireless standard and handled signal.For example, if down processing unit 801 is being handled among the WCDMA embodiment from the signal of DPCH (DPCH), then eight (8) chips can only be arranged to each symbol.Under these circumstances, per 8 chips write out a secondary data from accumulator 825a and 825b.Meanwhile, last processing unit 802 may be handled Common Pilot Channel (CPICH) signal that uses among the WCDMA embodiment.Described CPICH signal uses spreading code 0, and it has 256 chips to each symbol.Under these circumstances, per 256 chips write out a secondary data from accumulator 875a and 875b.Described this scheme among Figure 11.
Figure 11 explanation is according to one embodiment of present invention in the data output of separating associative cell 800 during the spread spectrum of WCDMA signal.Among Figure 11, following processing unit 801 is being handled DPCH (DPCH) signal that uses the 8-chip symbol, is handling Common Pilot Channel (CPICH) signal that uses the 256-chip symbol and go up processing unit 802.During cycle of treatment 1, following processing unit 801 and last processing unit 802 are dealt with the forth day of a lunar month chip separately: chip 0 is to chip 3.
If each chip is done once sampling, then cycle of treatment 1 only needs to do primary memory from memory 830 and reads circulation.If each chip is done double sampling (over-sampling rate=2), then cycle of treatment 1 need be made the twice storage device from memory 830 and read circulation.If each chip is done four samplings (over-sampling rate=4), then cycle of treatment 1 need be done four external memories from memory 830 and read circulation, and the rest may be inferred.In the ending of cycle of treatment 1, processing unit 801 is stored in described result among accumulator 825a and the 825b, but also not output, because the 8-chip symbol that still is untreated complete.Similarly, in the ending of cycle of treatment 1, processing unit 802 is stored in described result among accumulator 875a and the 875b, but also not output, because the 256-chip symbol that still is untreated complete.
2 of cycle of treatment, following processing unit 801 and last processing unit 802 are dealt with next four chips separately: chip 4 is to chip 7.In the ending of cycle of treatment 2, processing unit 801 with the result among accumulator 825a and 825b output as data 1, because the 8-chip symbol of processes complete.Similarly, in the ending of cycle of treatment 2, processing unit 802 continues described result is stored among accumulator 875a and the 875b,, but also not output, because the 256-chip symbol that still is untreated complete.
This process continues 64 cycle of treatment altogether, and processing unit 801 is whenever intact one group of eight chip of two circular treatment are just exported the result.After handling whole 256 chips, processing unit 802 is only exported once result in cycle of treatment 64, that is: pilot tone 1.
Figure 12 explanation data of the described associative cell among Fig. 8 output during the WCDMA cell search according to one embodiment of present invention.Processing unit 801 falls behind 4 chips in processing unit 802.In other words, processing unit 802 starts to be handled, and processing unit 801 falls behind its predetermined process circulation at least, i.e. 4 chips.In the ending of cycle of treatment 1, treated initial four chips of processing unit 802, chip 0 is to chip 3, and processing unit 801 is deactivated (free time).In the ending of cycle of treatment 2, treated altogether 8 chips of processing unit 802, and treated altogether 4 chips of processing unit 801.In the ending of cycle of treatment 3, treated altogether 12 chips of processing unit 802, and treated altogether 8 chips of processing unit 801.In the ending of cycle of treatment 4, treated altogether 16 chips of processing unit 802, and treated altogether 12 chips of processing unit 801.
In the ending of cycle of treatment 64, treated altogether 256 chips of processing unit 802 are also exported result's (promptly exporting 1).Meanwhile, treated altogether 252 chips of processing unit 801.In the ending of cycle of treatment 65, treated altogether 256 chips of processing unit 801 are also exported result's (promptly exporting 2).During cycle of treatment 65, processing unit 802 is deactivated (free time).In other words, shift to an earlier date the described circulation of predetermined process at least (promptly, 4 chips) start the processing unit 802 of handling operation and be deactivated (free time), handle sub-piece (promptly up to another, processing unit 801) after finishing, the described processing operation of handling sub-piece (that is, processing unit 802) finishes the processing operation.
Advantageously, because memory 830, code generator 835 and processing unit 801 and 802 are loosely-coupled, these arrangement of components can be used for different systems and/or function.And, can when not using, close memory 830, code generator 835 and processing unit 801 and 802 separately with saving power.In addition, above-mentioned associative cell framework is easily flexible and is easy to duplicate to realize required performance.
Though described the present invention with reference to one exemplary embodiment, those skilled in the art can figure out various changes and modification.The invention is intended to contain such change and modification, as long as it falls into the scope of described claims.
Claims (25)
1. reconfigurable associative cell is used for the sequence of related chip sample, and described reconfigurable associative cell comprises:
Memory is used to store the sequence of described chip sample;
A plurality of adding-subtract element, wherein, each described adding-subtract element can first chip sample from described memory receive a plurality of real parts position a and receive a plurality of imaginary parts position b from described first chip sample; And
Processing unit comprises:
A plurality of symbol selected cells, in described a plurality of symbol selected cell each can equal described a plurality of real parts position a and described a plurality of imaginary parts position b and first input a+b from described a plurality of adding-subtract one of them reception of element, and second input that equals the poor a-b of described a plurality of real parts position a and described a plurality of imaginary parts position b, and wherein, described each symbol selected cell generates real part output and imaginary part output, wherein, each of output of described real part and the output of described imaginary part equal following one of them: 1) multiply by+1 with-1 one of them described and a+b, and 2) multiply by+1 and-1 one of them described poor a-b.
2. the associative cell described in claim 1, further comprise code generator, it is used for the sequence of generated code position, wherein, described each symbol selected cell receives real part sign indicating number position and the imaginary part sign indicating number position from described sequence, and wherein, the real part output valve and the imaginary part output valve of described each symbol selected cell determined in described real part and imaginary part sign indicating number position.
3. the associative cell described in claim 2, wherein, described processing unit further comprises the first adder level, it comprises more than first real part adder and more than first imaginary part adder.
4. the associative cell described in claim 3, wherein, each described more than first real part adder receives from first real part output of one of them output of described a plurality of symbol selected cell and from wherein second real part output of another output of described a plurality of symbol selected cells, and produces real part and output.
5. the associative cell described in claim 4, wherein, each described more than first imaginary part adder receives from first imaginary part output of one of them output of described a plurality of symbol selected cell and from wherein second imaginary part output of another output of described a plurality of symbol selected cells, and produces imaginary part and output.
6. the associative cell described in claim 5, wherein, described processing unit further comprises the second adder level, it comprises at least one real part adder and at least one imaginary part adder.
7. the associative cell described in claim 6, wherein, in described at least one real part adder in the described second level each receives from first real part of one of them output of described more than first real part adder and output and from wherein second real part and the output of another output of described more than first real part adder, and produces real part and output.
8. the associative cell described in claim 7, wherein, in described at least one imaginary part adder in the described second level each receives from first imaginary part of one of them output of described more than first imaginary part adder and output and from wherein second imaginary part and the output of another output of described more than first imaginary part adder, and produces imaginary part and output.
9. the associative cell described in claim 8, wherein, described processing unit further comprises first accumulator, its can receive and accumulative total from the real part and the output of described at least one the real part adder in the described second level.
10. the associative cell described in claim 9, wherein, described processing unit further comprises second accumulator, its can receive and accumulative total from the imaginary part and the output of described at least one the imaginary part adder in the described second level.
11. the associative cell described in one of claim 1 to 10 wherein, is applied to the described reconfigurable associative cell that is used for the sequence of related chip sample to comprise the software-defined radio SDR system of reconfigurable data processor.
12. the associative cell described in claim 1, wherein, described processing unit comprises that two are handled sub-piece, is used to carry out identical processing operation.
13. the associative cell described in claim 12 wherein, handle one of sub-piece startup processing operation for described two, and another is handled the backward circulation of predetermined process at least of sub-piece.
14. the associative cell described in claim 13, wherein, describedly shift to an earlier date the described loop start of predetermined process at least and handle a processing unit of operation and be deactivated, handle sub-piece up to another and after described one the described processing operation of handling sub-piece is finished, finish to handle and operate.
15. a reconfigurable unit is used to handle a plurality of context instructions, described reconfigurable unit comprises:
A plurality of processors are used to carry out each predetermined specific context instruction;
Program storage is used to store the control program from the external control line;
Serial device is used for obtaining program command from described program storage, sends to corresponding processor in described a plurality of processor with the context ordering and with described context through ordering as reconfiguring the position; And
Be connected the interconnect fabric between each and the external data bus of described a plurality of processors, be used for data are sent to the corresponding processor of described a plurality of processor from described data/address bus.
16. the reconfigurable unit described in claim 15 further comprises between described control line and the described program storage and the buffer between described control line and the described serial device.
17. the reconfigurable unit described in claim 15 further comprises the buffer between described data/address bus and described interconnect fabric.
18. described reconfigurable unit wherein, is carried out in the reconfigurable unit described in claim 15 in software-defined radio SDR system.
19. the reconfigurable unit described in claim 18, wherein, one of them carries out the instruction of the context-sensitive of handling baseband signal described a plurality of processors.
20. the reconfigurable unit described in claim 18, wherein, the instruction of the context-sensitive of Memory Controller is served as in described one of them execution of a plurality of processors.
21. the reconfigurable unit described in claim 18, wherein, the instruction of the context-sensitive that one of them complete MPEG-4 that is used for multimedia application of described a plurality of processors handles.
22. a method that is used in the sequence of the related chip sample of software-defined radio SDR system comprises:
First chip sample from be stored in memory reads a plurality of real parts position a and reads a plurality of imaginary parts position b from described first chip sample;
Utilize a plurality of adding-subtract element to generate described a plurality of real parts position a and described a plurality of imaginary parts position b and poor a-b a+b and described a plurality of real parts position a and described a plurality of imaginary parts position b;
Utilize a plurality of adding-subtract element to generate and equal difference a-b to be multiply by one of them imaginary part output of sign indicating number position+1 and-1 with multiply by from sign indicating number position+1 and-1 that code generator generates the real part output of one of them with a+b and equaling;
As first order addition, to doing addition by first real part output of the described real part output of described a plurality of adding-subtract each generation in the element, to doing addition by first imaginary part output of the described imaginary part output of described a plurality of adding-subtract each generation in the element, to doing addition, to doing addition by second imaginary part output of described a plurality of adding-subtract described imaginary part output of each generation in the element by second real part output of the described real part output of described a plurality of adding-subtract each generation in the element;
As second level addition, second real part output that first real part output that described addition is obtained and described addition obtain is done addition and is generated final real part output, and second imaginary part that obtains of first imaginary part output that described addition is obtained and described addition is exported to do addition and generate final imaginary part and exported; And
To whole chip sample of forming predetermined symbol each in exporting of described final real part output and described final imaginary part that adds up individually, and export the described result who adds up as association results.
23. the method described in claim 22, wherein, described chip sample is to form 8 chip sample of the symbol that receives by DPCH DPCH.
24. the method described in claim 22, wherein, described chip sample is to form 256 chip sample of the symbol that receives by Common Pilot Channel CPICH.
25. the method described in claim 23 or claim 24, wherein, described a plurality of adding-subtract element is 4 elements.
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| US11/123,313 | 2005-05-06 | ||
| US11/123,313 US7668992B2 (en) | 2005-02-17 | 2005-05-06 | Context-based operation reconfigurable instruction set processor and method of operation |
| US11/150,511 US7483933B2 (en) | 2005-02-17 | 2005-06-10 | Correlation architecture for use in software-defined radio systems |
| US11/150,511 | 2005-06-10 | ||
| PCT/KR2006/000553 WO2006088329A1 (en) | 2005-02-17 | 2006-02-17 | Correlation unit for use in software-defined radio systems and therefor method |
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