CN101118533A - Algorithm entity verification system and method - Google Patents
Algorithm entity verification system and method Download PDFInfo
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- CN101118533A CN101118533A CNA2007100457159A CN200710045715A CN101118533A CN 101118533 A CN101118533 A CN 101118533A CN A2007100457159 A CNA2007100457159 A CN A2007100457159A CN 200710045715 A CN200710045715 A CN 200710045715A CN 101118533 A CN101118533 A CN 101118533A
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Abstract
The present invention provides an arithmetic entity verifying system and a verifying method. The method uses a PC host computer as a main data verifying controller, uses a sub-controller as a bridge, to connect with the arithmetic physical entity and the main controller; by controlling the input clock of the arithmetic physical entity, the running process of the arithmetic physical entity is controlled, and the contradiction, that the data processing of the PC host computer is slow but the running speed of the arithmetic physical entity is fast, is solved, at the same time, the arithmetic physical entity verifying method has the advantage of low cost.
Description
Technical field
The present invention relates to a kind of digital information processing system and method, particularly a kind of system and method that algorithm entity is verified.
Background technology
Along with the development of Digital Signal Processing, the realization of algorithm is also more and more easier, and then has advanced each application all to adopt various algorithms to realize application target.The expansion of range of application has also caused the complicacy and the necessity of algorithm, what use was more at present is to monitor in real time by the professional test instrument, but because the professional test instrument all compares costliness, so the cost of checking is also very high, for the algorithm entity verification in some applications is not very practical, such as the application of some special digital wave filters.
Because arithmetic physical adopts integrated circuit to realize mostly, so its running frequency can reach hundreds of million even higher, and as the PC main frame of verifying display terminal cheaply, its processing speed does not obviously catch up with so high running frequency, when particularly having adopted non-real time operating system.
Therefore, need provide a kind of algorithm entity verification system cheaply and method, come the algorithm implementation procedure is coordinated control and data processing.
Summary of the invention
Technical matters to be solved by this invention provides a kind of algorithm entity verification system and method, to coordinate the travelling speed of PC main frame and arithmetic physical, and with the PC main frame as master controller and the checking display terminal, do not need to purchase in addition professional instrument, algorithm entity is verified the realization simple and flexible.
In order to solve the problems of the technologies described above, the present invention is achieved in that a kind of algorithm entity verification system, comprises master controller, is used to realize test data analysis, processing and demonstration; With the arithmetic physical that is used for implementation algorithm, wherein, described verification system also comprises a secondary controller, is used to connect master controller and arithmetic physical.
Described master controller adopts the application software in PC main frame and the PC main frame to realize;
Described secondary controller comprises input clock, counter, first memory and second memory; Described first memory is used to the test data that prestores, and reads for arithmetic physical; Described second memory is used to preserve the output data of arithmetic physical.
Described master controller adopts the connected mode of USB to be connected with secondary controller.
Described arithmetic physical can adopt FPGA.
Described secondary controller is connected by following arbitrary mode with arithmetic physical: I
2The mode of C, SPI or MPU external memory access.
Another solution of the present invention provides a kind of implementation method of algorithm entity verification system, and described implementation method comprises the steps:
Step 1, secondary controller produce a Global reset pulse and pass to arithmetic physical, make arithmetic physical be in init state;
Step 2, secondary controller be to arithmetic physical read test data, and pass through I
2The connected mode of C, SPI or MPU external memory access is kept at test data in the first memory, by arithmetic physical direct read test data in the first memory;
Step 4, arithmetic physical output data, and be saved in the second memory;
Step 6; If do not obtain " beginning checking " instruction, then be in waiting status always;
Step 6, master controller send an instruction of reading the designated length data by USB to secondary controller;
Step 8, secondary controller enable the input clock of arithmetic physical, and arithmetic physical writes data in second memory, and circulation execution in step 8 is received the data of designated length up to master controller;
After step 9, master controller are received the designated length data, data are further processed and analyze, and the checking result is shown;
Step 10, judge whether master controller receives outside " stop checking " instruction, if, then enter step 11, if not, then return step 6;
Step 11, master controller send " stopping a checking " instruction to secondary controller;
Step 12, secondary controller produce a global reset signal to arithmetic physical after receiving " stopping checking " instruction, make arithmetic physical be in init state.
In described step 1～4, secondary controller is not done response to the instruction that master controller sends;
The described designated length of step 6 equals the clock periodicity of secondary controller output;
In the step 8, when rolling counters forward arrived designated value, secondary controller kept original state.
The present invention makes it compared with prior art owing to adopted above-mentioned technical scheme, has following advantage and good effect:
1, in the middle of master controller and arithmetic physical, a secondary controller is set, coordinate the travelling speed of main frame and arithmetic physical, and with the PC main frame as master controller and checking display terminal, do not need to purchase professional instrument in addition, cost is lower, realizes flexible;
2, can the effective coordination master controller and the travelling speed of arithmetic physical, because behind the periodicity of arithmetic physical each run appointment, just be in the state of time-out, during this period of time, the PC main frame can be handled the data that before received with regard to time enough is arranged; The PC main frame can rerun clock period of appointment by arithmetic physical by secondary controller after handling data, and so repeatedly, arithmetic physical is equivalent to the state that always is in operation, up to finishing once complete verification operation.
Description of drawings
The concrete structure of the verification system of a kind of algorithm entity of the present invention and the flow process of implementation method are provided by following embodiment and accompanying drawing.
Fig. 1 is the verification system structural representation of the embodiment of the invention;
Fig. 2 is the verification method schematic flow sheet of the embodiment of the invention.
Embodiment
Below will be described in further detail algorithm entity verification system of the present invention and implementation method.
The structure of algorithm entity verification system of the present invention as shown in Figure 1, this verification system comprises master controller 1, secondary controller 2 and arithmetic physical 3.Master controller 1 is the PC main frame, and all test datas are handled and analyzed and realized by the application software on the PC main frame that all this measure has reduced the cost of data analysis.Secondary controller 2 and arithmetic physical 3 can realize by a shared chip, also can adopt two separate chips to realize.In present embodiment, for simplied system structure, secondary controller 2 adopts the LPC2148 chip of Philips company to realize ARM controller 21, and the interior counter 22 of XC2V6000 chip that adopts Xilinx company, second memory in the first memory in the XC2V6000 chip, XC2V6000 chip is formed jointly; The P0.8 of LPC2148 chip is as the Global reset control signal wire of XC2V6000 chip, and P0.9 is as counter 22 reset signals of XC2V6000 chip internal.When the count value of the counter in the XC2V6000 chip 22 is 66, it is in hold mode, when the P0.9 of LPC2148 chip produces a reset pulse, after counter 22 is reset to 0, again since 0 counting, up to 66 o'clock, be in hold mode again, when the count value of counter 22 is 1 to 64, produce a high impulse, enable the input clock (not shown) of XC2V6000 chip; First memory in the XC2V6000 chip has test data.Arithmetic physical 3 is the physical device of implementation algorithm, adopts the XC2V6000 chip of Xilinx company, with secondary controller 2 shared chips; PC main frame 1 and LPC2148 chip adopt the connected mode of USB, and LPC2148 chip and XC2V6000 chip adopt I
2The connected mode of C.
PC main frame 1 has been controlled the operation of LPC2148 chip as the master controller of whole verification system, and the LPC2148 chip has then been controlled the operation of XC2V6000 chip.
In conjunction with seeing figures.1.and.2, the verification step of algorithm entity of the present invention is as follows:
S1, secondary controller 2 produce a Global reset pulse and pass to arithmetic physical 3, make arithmetic physical 3 be in init state;
S2, secondary controller 2 be to arithmetic physical 3 read test data, and pass through I
2C interface writes data in advance in the first memory in the XC2V6000 chip, by arithmetic physical 3 direct read test data in the first memory;
S3, secondary controller 2 are that the P0.9 of LPC2148 chip produces a high impulse, and behind the reset counter 22, counter 22 began counting, kept original state up to 66 o'clock; When the count value of counter 22 is 1～64, produce a high impulse, enable the input clock that arithmetic physical 3 is the XC2V6000 chip, thereby imported 64 clock period; Arithmetic physical 3 brings into operation;
S4, arithmetic physical 3 output datas, and be saved in the second memory;
S5, finish S1～S4 after, master controller 1 enters waiting status, if outside input " begins checking " instruction then enters S6; If do not obtain " beginning checking " instruction, then be in waiting status always;
The instruction that S6, master controller 1 send a reading of data by USB to secondary controller 2, data length are 64;
S7, secondary controller 2 are given master controller 1 by the USB line with the data transfer that obtains among the step S4;
S8, repeated execution of steps S8a: enable arithmetic physical 3 input clocks by secondary controller 2, and step S8b: write data by arithmetic physical 3 to second memory, up to rolling counters forward to 64, promptly master controller 1 has received 64 data;
S9, master controller 1 are further processed and analyze data after receiving 64 data, and the checking result is shown;
S10, in step S6～S9, if master controller 1 is received outside " stop checking " instruction, then enter step S11, otherwise, return step S6 behind the execution of step S9;
S11, master controller 1 send " stopping a checking " instruction to secondary controller 2;
After S12, secondary controller 2 received " stopping checking " instruction, the P0.8 of LPC2148 produced a global reset signal to arithmetic physical 3, makes arithmetic physical 3 be in init state.
Need to prove that in above-mentioned steps S1～S4, response is not done in the instruction that 2 pairs of master controllers 1 of secondary controller send.
Claims (12)
1. an algorithm entity verification system comprises master controller, is used to realize test data analysis, processing and demonstration; Arithmetic physical with being used for implementation algorithm is characterized in that: described verification system also comprises a secondary controller, is used to connect master controller and arithmetic physical.
2. algorithm entity verification system as claimed in claim 1 is characterized in that: described master controller adopts the application software in PC main frame and the PC main frame to realize.
3. algorithm entity verification system as claimed in claim 1 is characterized in that: described secondary controller comprises input clock, counter, first memory and second memory.
4. algorithm entity verification system as claimed in claim 3 is characterized in that: described first memory is used to the test data that prestores, and reads for arithmetic physical.
5. algorithm entity verification system as claimed in claim 3 is characterized in that: described second memory is used to preserve the output data of arithmetic physical.
6. algorithm entity verification system as claimed in claim 1 is characterized in that: described master controller adopts the connected mode of USB to be connected with secondary controller.
7. algorithm entity verification system as claimed in claim 1 is characterized in that: described arithmetic physical can adopt FPGA.
8. algorithm entity verification system as claimed in claim 1 is characterized in that: described secondary controller is connected by following arbitrary mode with arithmetic physical: I
2The mode of C, SPI or MPU external memory access.
9. the implementation method of algorithm entity verification system as claimed in claim 3, it is characterized in that: described implementation method comprises the steps:
Step 1, secondary controller produce a Global reset pulse and pass to arithmetic physical, make arithmetic physical be in init state;
Step 2, secondary controller be to arithmetic physical read test data, and pass through I
2The connected mode of C, SPI or MPU external memory access is kept at test data in the first memory, by arithmetic physical direct read test data in the first memory;
Step 3, secondary controller enable the input clock of arithmetic physical, and arithmetic physical brings into operation;
Step 4, arithmetic physical output data, and be saved in the second memory;
Step 5, master controller enter waiting status, instruct if outside input " begins checking ", then enter
Step 6; If do not obtain " beginning checking " instruction, then be in waiting status always;
Step 6, master controller send an instruction of reading the designated length data by USB to secondary controller;
Step 7, secondary controller are given master controller by USB with the data transfer that obtains in the step 4;
Step 8, secondary controller enable the input clock of arithmetic physical, and arithmetic physical writes data in second memory, and circulation execution in step 8 is received the data of designated length up to master controller;
After step 9, master controller are received the designated length data, data are further processed and analyze, and the checking result is shown;
Step 10, judge whether master controller receives outside " stop checking " instruction, if, then enter step 11, if not, then return step 6;
Step 11, master controller send " stopping a checking " instruction to secondary controller;
Step 12, secondary controller produce a global reset signal to arithmetic physical after receiving " stopping checking " instruction, make arithmetic physical be in init state.
10. the implementation method of the described algorithm entity verification system of claim 9, it is characterized in that: in described step 1～4, secondary controller is not done response to the instruction that master controller sends.
11. the implementation method of algorithm entity verification system as claimed in claim 9 is characterized in that: the described designated length of step 6 equals the clock periodicity of secondary controller output.
12. the implementation method of algorithm entity verification system as claimed in claim 9 is characterized in that: when the count value of counter reached designated value, secondary controller kept original state.
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| CNA2007100457159A CN101118533A (en) | 2007-09-07 | 2007-09-07 | Algorithm entity verification system and method |
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| CNA2007100457159A CN101118533A (en) | 2007-09-07 | 2007-09-07 | Algorithm entity verification system and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106292330A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm test method |
| CN106295808A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm test method |
| CN106295809A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm pilot system |
-
2007
- 2007-09-07 CN CNA2007100457159A patent/CN101118533A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106292330A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm test method |
| CN106295808A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm test method |
| CN106295809A (en) * | 2016-07-13 | 2017-01-04 | 北京航空航天大学 | Aircraft embedded real-time diagnosis reasoning algorithm pilot system |
| CN106295808B (en) * | 2016-07-13 | 2018-12-11 | 北京航空航天大学 | The embedded real-time diagnosis reasoning algorithm test method of aircraft |
| CN106295809B (en) * | 2016-07-13 | 2018-12-14 | 北京航空航天大学 | The embedded real-time diagnosis reasoning algorithm pilot system of aircraft |
| CN106292330B (en) * | 2016-07-13 | 2019-08-23 | 北京航空航天大学 | The embedded real-time diagnosis reasoning algorithm test method of aircraft |
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