CN101114626B - Wafer structure - Google Patents
Wafer structure Download PDFInfo
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- CN101114626B CN101114626B CN200610099115A CN200610099115A CN101114626B CN 101114626 B CN101114626 B CN 101114626B CN 200610099115 A CN200610099115 A CN 200610099115A CN 200610099115 A CN200610099115 A CN 200610099115A CN 101114626 B CN101114626 B CN 101114626B
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- detection welding
- welding pad
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- protective layer
- pad
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- 238000003466 welding Methods 0.000 claims abstract description 154
- 238000001514 detection method Methods 0.000 claims description 143
- 239000011241 protective layer Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 18
- 238000012360 testing method Methods 0.000 abstract description 50
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 210000001364 upper extremity Anatomy 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention relates to a wafer structure, which comprises a substrate, a plurality of wafer welding pads and a plurality of testing welding pad groups, and is characterized in that the substrate is provided with an active surface on which the wafer welding pads are arranged, at least part of the wafer welding pads are permutated along a first line, the testing welding pad groups are arranged on the active surface and are permutated along a second line, a first line and a second line are paralleled and the intervals between the adjacent testing welding pad groups are the same, each testing welding pad group is provided with a plurality of testing welding pads which are electrically connected with wafer welding pads that are permutated along a first line, the distances between the testing welding pads in each testing welding pad group and the first line are different. Therefore, the cost of the wafer structure is not increased according to an electricity test.
Description
Technical field
The present invention relates to a kind of chip architecture, particularly relate to a kind of wafer (also being called chip) structure with a plurality of detection welding pads.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the encapsulation (IC package) of the making (ICprocess) of the design of integrated circuit (IC design), integrated circuit and integrated circuit.
In the making of integrated circuit, wafer (chip) is to finish via wafer (wafer) making, formation integrated circuit, testing electrical property (electrical testing) and cutting crystal wafer steps such as (wafersawing).Wafer has an active surface (active surface), the surface with active member (active device) of its general reference wafer.After the integrated circuit of wafer inside is finished, the active surface of wafer will dispose a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed wafer by wafer.
In wafer form test individual wafer, its process is called probe of wafer (wafer sorting).Probe of wafer is to set up temporary transient electrical the contact between wafer and automatic test equipment.Probe of wafer is the important test of integrated circuit (IC) design and function, with before carrying out subsequent wafer separation and encapsulation procedure, filters out good wafer.
See also shown in Figure 1A and Figure 1B, wherein Figure 1A is the schematic top plan view of existing a kind of chip architecture, and Figure 1B is the schematic side view of the chip architecture of Figure 1A.Existing chip architecture 100 comprises a base material (substrate) 110, a plurality of chip bonding pads (chip bonding pad) 120, one protective layer (passivation layer) 130 and a plurality of projections (bump) 140.Base material 110 has an active surface 112, and these chip bonding pads 120 are disposed on the active surface 112 and present annular array.Protective layer 130 covers active surface 112, and exposes these chip bonding pads 120.In addition, these projections 140 are disposed at respectively on these chip bonding pads 120.
Yet, because under the trend that the integrated level (integration) of the miniaturization of chip architecture 100 or its inner member promotes, these chip bonding pads 120 interval (pitch) to each other is more and more littler.So, when chip architecture 100 when carrying out testing electrical property (that is above-mentioned probe of wafer stage and chip architecture 100 singulation separation not yet), a plurality of test contacts of testing equipment (not illustrating) (testing contacts) (not illustrating) interval each other can't dwindle along with the interval between these chip bonding pads 120 and shorten accordingly.Therefore, these test contacts (not illustrating) just can't electrically contact these projections 140 on these chip bonding pads 120 accordingly and successfully carry out the work of testing electrical property chip architecture 100.From the above, the interval downsizing between these chip bonding pads 120 will cause the degree of difficulty of testing electrical property chip architecture 100 to improve, and then increase the cost of testing electrical property.
Summary of the invention
The purpose of this invention is to provide a kind of chip architecture, the interval between its these chip bonding pads is less and still can existing testing equipment carry out testing electrical property.
For reaching above-mentioned or other purposes; the present invention proposes a kind of chip architecture; it comprises a base material; a plurality of chip bonding pads; first protective layer; at least one second protective layer; a plurality of projections; a plurality of detection welding pad groups (test-bonding-pad set) and many weld pad connecting lines. base material has an active surface; these chip bonding pads are disposed on the active surface; wherein to these chip bonding pads of small part along one first linear array. first protective layer covers active surface and also exposes these chip bonding pads. second protective layer partly covers first protective layer. a plurality of projections are disposed on these chip bonding pads and first protective layer. these detection welding pad assembly place on the active surface and along one second linear array; wherein first straight line and second straight line parallel; and the interval between adjacent these detection welding pad groups is mutually the same. each detection welding pad group has a plurality of detection welding pads (test bonding pad); these detection welding pads electrically connect with these chip bonding pads along first linear array respectively; and these detection welding pads of each detection welding pad group and the distance between first straight line differ from one another, and wherein each detection welding pad is disposed on second protective layer.Wherein these chip bonding pads along first linear array electrically connect with these detection welding pads by these weld pad connecting lines respectively; the part of each weld pad connecting line is disposed on one of these chip bonding pads; each weld pad connecting line another part is disposed on first protective layer; and the sidewall that covers part first protective layer also directly covers the upper surface of first protective layer, and other parts of each weld pad connecting line are disposed on second protective layer.
In one embodiment of this invention, these detection welding pads of above-mentioned each detection welding pad group comprise one first detection welding pad and one second detection welding pad.Distance between first detection welding pad and first straight line can be less than the distance between second detection welding pad and first straight line.
In one embodiment of this invention, these detection welding pads of above-mentioned each detection welding pad group comprise one first detection welding pad and one second detection welding pad.Distance between first detection welding pad and first straight line can be less than the distance between second detection welding pad and first straight line.In addition, above-mentioned chip architecture more comprises one the 3rd detection welding pad, is disposed on second protective layer and is positioned at the least significant end of these detection welding pad groups.The 3rd detection welding pad with electrically connect along one of these chip bonding pads of first linear array, distance between the 3rd detection welding pad and first straight line is equal to the distance between first detection welding pad and first straight line, and the 3rd detection welding pad is adjacent with second detection welding pad.
In one embodiment of this invention, these detection welding pads of above-mentioned each detection welding pad group comprise one first detection welding pad and one second detection welding pad.Distance between first detection welding pad and first straight line can be less than the distance between second detection welding pad and first straight line.In addition, above-mentioned chip architecture more comprises one the 3rd detection welding pad, is disposed on second protective layer and is positioned at the least significant end of these detection welding pad groups.The 3rd detection welding pad with electrically connect along one of these chip bonding pads of first linear array, distance between the 3rd detection welding pad and first straight line is equal to the distance between second detection welding pad and first straight line, and the 3rd detection welding pad is adjacent with first detection welding pad.
In one embodiment of this invention, above-mentioned these chip bonding pads can be arranged in ring-type, and configurable on a plurality of side areas of active surface.
In one embodiment of this invention, above-mentioned these chip bonding pads can be arranged in ring-type, and configurable on a plurality of side areas of active surface.In addition, above-mentioned these detection welding pad groups can be positioned on the interior zone of these chip bonding pads of arranging in the form of a ring.
In one embodiment of this invention, the thickness of above-mentioned each detection welding pad can be more than or equal to 2 microns and can be smaller or equal to 6 microns.
In one embodiment of this invention, the material of above-mentioned each detection welding pad can be gold.
In one embodiment of this invention, the shape of second protective layer can be bulk, ring-type or strip.
In one embodiment of this invention, the material of second protective layer can be pi (polyimide).
In one embodiment of this invention, the material of above-mentioned each weld pad connecting line can be gold.The material of above-mentioned each projection can be gold.
Based on above-mentioned, because each detection welding pad group of chip architecture of the present invention has these detection welding pads, so under the more and more littler trend in the interval between these chip bonding pads, the process of testing electrical property chip architecture still can see through testing equipment and electrically contact and tested and finish with these detection welding pads. therefore, chip architecture of the present invention still can utilize existing testing equipment to finish the work of testing electrical property, and can not increase the cost of testing electrical property.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, specific embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A is the schematic top plan view of existing a kind of chip architecture.
Figure 1B is the schematic side view of the chip architecture of Figure 1A.
Fig. 2 A is the schematic top plan view of a kind of chip architecture of first embodiment of the invention.
Fig. 2 B is the schematic side view of the chip architecture of Fig. 2 A.
Fig. 3 is the schematic top plan view of a kind of chip architecture of second embodiment of the invention.
Fig. 4 is the schematic top plan view of a kind of chip architecture of third embodiment of the invention.
100,200,300,400: chip architecture 110,210: base material
112,212: active surface 120,220: chip bonding pads
130: protective layer 140,280: projection
230: detection welding pad group 232: detection welding pad
232a: the first detection welding pad 232b: second detection welding pad
240,240 ': 250: the first protective layers of the 3rd detection welding pad
260,360,460: the second protective layers 270: weld pad connecting line
A1: side area A2: interior zone
D1, d2, d3: 1: the first straight line of distance L
L2: the second straight line P1, P2, P 3, P4: at interval
T1, t2: thickness
Embodiment
Fig. 2 A is the schematic top plan view of a kind of chip architecture of first embodiment of the invention, and Fig. 2 B is the schematic side view of the chip architecture of Fig. 2 A.Please consult simultaneously shown in Fig. 2 A and Fig. 2 B, the chip architecture 200 of first embodiment comprises a base material 210, a plurality of chip bonding pads 220 and a plurality of detection welding pad groups 230.Base material 210 has an active surface 212, and these chip bonding pads 220 are disposed on the active surface 212, wherein arranges along one first straight line L1 to these chip bonding pads 220 of small part.
These detection welding pad groups 230 are disposed on the active surface 212 and along one second straight line L2 and arrange, and wherein the first straight line L1 is parallel with the second straight line L2, and the interval P1 between adjacent these detection welding pad groups 230 is mutually the same.Each detection welding pad group 230 has a plurality of detection welding pads 232 (Fig. 2 A schematically illustrates two), these detection welding pads 232 electrically connect with these chip bonding pads 220 of arranging along the first straight line L1 respectively, and differing from one another apart from d1, d2 between these detection welding pads 232 of each detection welding pad group 230 and the first straight line L1.
In first embodiment, these detection welding pads 232 of each detection welding pad group 230 comprise between one first detection welding pad 232a and one second detection welding pad 232b., the first detection welding pad 232a and the first straight line L1 apart from d1 can less than between the second detection welding pad 232b and the first straight line L1 apart from d2. in addition, these chip bonding pads 220 can be arranged in ring-type, and configurable on a plurality of (Fig. 2 A schematically illustrates four) side area A1 of active surface 212, and these detection welding pad groups 230 can be positioned on the interior zone A2 of these chip bonding pads 220 of arranging in the form of a ring.
See also shown in Fig. 2 A, with regard to chip architecture 200 with regard to the relative position among Fig. 2 A, on the side area A1 of the upper limb of active surface 212, the chip architecture 200 of first embodiment more comprises one the 3rd detection welding pad 240, and it is disposed on the active surface 212 and is adjacent with one of them of two these detection welding pad groups 230 of least significant end.In first embodiment, the 3rd detection welding pad 240 is adjacent with the detection welding pad group 230 of the rightmost side.One of them electric connection of the 3rd detection welding pad 240 and these chip bonding pads 220 of arranging along the first straight line L1, and between the 3rd detection welding pad 240 and the first straight line L1 apart from d 3 be equal between the first detection welding pad 232a and the first straight line L1 apart from d1, and the 3rd detection welding pad 240 is adjacent with the second detection welding pad 232b.
In other words, on the side area A1 of the upper limb of active surface 212, these first detection welding pads 232a, these second detection welding pad 232b and the 3rd detection welding pad 240 are staggered and arrange the shape of its arrangement such as zigzag.By Fig. 2 A as can be known, these first detection welding pad 232a and the 3rd detection welding pad 240 are parallel to the second straight line L2 and form a line, and these second detection welding pads 232b is parallel to the second straight line L2 and forms a line.
When a plurality of test contacts (not illustrating) of testing equipment (not illustrating) desire to carry out testing electrical property for these chip bonding pads 220 on the side area A1 that is positioned at active surface 212 upper limbs of chip architecture 200, even these chip bonding pads 220 interval P2 each other that is positioned on the side area A1 of active surface 212 upper limbs is shorter, testing equipment (not illustrating) still can be tested these first detection welding pad 232a and the 3rd detection welding pad 240 earlier by these test contacts (not illustrating), and its interval P 3 each other comes longly than interval P2.Afterwards, test these second detection welding pads 232b again, its interval P4 each other also comes longly than interval P2.Wherein, the length of P3 and interval P4 is the length that is same as the interval P1 between adjacent these detection welding pad groups 230 in logic at interval.Offer a piece of advice it, these detection welding pad groups 230 that are positioned on the side area A1 of active surface 212 upper limbs still can utilize existing testing equipment (not illustrating) to finish the work of testing electrical property, and can not increase the cost of testing electrical property.
In this mandatory declaration is that these chip bonding pads 220 on the A1 of other side areas of active surface 212 are same as above-mentioned with the arrangement mode and the test mode of these detection welding pad groups 230 substantially.Main difference is, 212 leftmost side area A1 are example with active surface, as long as under the prerequisite of the function that does not influence above-mentioned testing electrical property chip architecture 200, the designer can make so according to the order that these detection welding pad groups 230 are arranged, and position and relativeness that the position and the relativeness of the 3rd detection welding pad 240 ' is designed to be same as these second detection welding pads 232b.In other words, on active surface 212 leftmost side area A1, these first detection welding pads 232a forms a line, and these second detection welding pad 232b and the 3rd detection welding pad 240 ' form a line, and these first detection welding pads 232a, these second detection welding pad 232b and the 3rd detection welding pad 240 ' are staggered arrangement, the shape of its arrangement such as zigzag.
In addition, it must be emphasized that as long as under the prerequisite of the function that does not influence above-mentioned testing electrical property chip architecture 200, the designer can increase the number of these detection welding pads 232 of each detection welding pad group 230 according to design requirement.In other words, the number of these detection welding pads 232 of each detection welding pad group 230 of first embodiment (two) is non-limiting the present invention in order to give an example.
See also shown in Fig. 2 B, in first embodiment, the thickness t 1 of each detection welding pad 232 can be more than or equal to 2 microns and can be smaller or equal to 6 microns, and the material of each detection welding pad 232 can be gold.In addition, chip architecture 200 more comprises one first protective layer 250 and at least one second protective layer 260.The material that first protective layer 250 covers active surfaces 212 and exposes these chip bonding pads 220, the first protective layers can be benzocyclobutene (BenzoCycloButene, BCB).The material of second protective layer 260 can be pi, and its part covers first protective layer 250, and wherein each detection welding pad 232 is disposed on second protective layer 260.In first embodiment, the shape of second protective layer 260 can be bulk (seeing Fig. 2 A).
What be worth emphasizing is, when when carrying out testing electrical property chip architecture 200, in order to make these test contacts (not illustrating) of testing equipment (not illustrating) keep electrically contacting with these detection welding pads 232, testing equipment (not illustrating) must bring pressure to bear on these detection welding pads 232.Yet second protective layer 260 can bear the function of this pressure with active surface 212 that Additional Protection base material 210 is provided.
Please consult shown in Fig. 2 A and Fig. 2 B, chip architecture 200 more comprises many weld pad connecting lines 270 again.For with regard to the example, wherein these chip bonding pads 220 of arranging along the first straight line L1 electrically connect with these detection welding pads 232 by these weld pad connecting lines 270 respectively with regard to the side area A1 of the upper limb of active surface 212.The part of each weld pad connecting line 270 is disposed on one of them of these chip bonding pads 220; another part of each weld pad connecting line 270 is disposed on first protective layer 250, and other parts of each weld pad connecting line 270 are disposed on second protective layer 260.In addition, the thickness t 2 of each weld pad connecting line 270 can be more than or equal to 2 microns and can be smaller or equal to 6 microns, and the material of each weld pad connecting line 270 can be gold.
In first embodiment, chip architecture 200 more comprises a plurality of projections 280, be disposed at respectively on these chip bonding pads 220, and the material of each projection 280 can be gold.These projections 280 are electrically connected to the media of carrier (not illustrating) as chip architecture 200.
See also shown in Figure 3ly, it is the schematic top plan view of a kind of chip architecture of second embodiment of the invention.The main difference part of the chip architecture 300 of second embodiment and the chip architecture 200 of first embodiment is that second protective layer 360 of chip architecture 300 can be ring-type.See also shown in Figure 4ly, it is the schematic top plan view of a kind of chip architecture of third embodiment of the invention.The chip architecture 400 of the 3rd embodiment is that with the main difference part of above-mentioned chip architecture 200,300 second protective layer 460 of chip architecture 400 can be strip, and the number of second protective layer 460 for example is four.
In sum, because each detection welding pad group of chip architecture of the present invention has these detection welding pads, so under the more and more littler trend in the interval between these chip bonding pads, the process of testing electrical property chip architecture still can see through testing equipment and electrically contact and tested and finish with these detection welding pads.Therefore, chip architecture of the present invention still can utilize existing testing equipment to finish the work of testing electrical property, and can not increase the cost of testing electrical property.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. chip architecture is characterized in that it comprises:
One base material has an active surface;
A plurality of chip bonding pads are disposed on this active surface, wherein to those chip bonding pads of small part along one first linear array;
First protective layer covers this active surface and exposes those chip bonding pads;
At least one second protective layer, part covers this first protective layer;
A plurality of projections are disposed on those chip bonding pads and this first protective layer;
A plurality of detection welding pad groups, be disposed on this second protective layer, and cover on this active surface along one second linear array, wherein this first straight line and this second straight line parallel, and the interval between adjacent those detection welding pad groups is mutually the same, respectively this detection welding pad group has a plurality of detection welding pads, those detection welding pads electrically connect with those chip bonding pads along this first linear array respectively, and respectively the distance between those detection welding pads of this detection welding pad group and this first straight line differs from one another, and wherein respectively this detection welding pad is disposed on this second protective layer; And
Many weld pad connecting lines; wherein those chip bonding pads along this first linear array electrically connect with those detection welding pads by those weld pad connecting lines respectively; respectively the part of this weld pad connecting line is disposed on one of those chip bonding pads; respectively this weld pad connecting line another part is disposed on this first protective layer, and respectively other parts of this weld pad connecting line are disposed on this second protective layer.
2. chip architecture according to claim 1 is characterized in that those detection welding pads of wherein said each detection welding pad group comprise:
One first detection welding pad; And
One second detection welding pad, wherein the distance between this first detection welding pad and this first straight line is less than the distance between this second detection welding pad and this first straight line.
3. chip architecture according to claim 2; it is characterized in that it more comprises one the 3rd detection welding pad; be disposed on this second protective layer and be positioned at the least significant end of those detection welding pad groups; wherein the 3rd detection welding pad with electrically connect along one of those chip bonding pads of this first linear array; distance between the 3rd detection welding pad and this first straight line is equal to the distance between this first detection welding pad and this first straight line, and the 3rd detection welding pad is adjacent with this second detection welding pad.
4. chip architecture according to claim 2; it is characterized in that it more comprises one the 3rd detection welding pad; be disposed on this second protective layer and be positioned at the least significant end of those detection welding pad groups; wherein the 3rd detection welding pad with electrically connect along one of those chip bonding pads of this first linear array; distance between the 3rd detection welding pad and this first straight line is equal to the distance between this second detection welding pad and this first straight line, and the 3rd detection welding pad is adjacent with this first detection welding pad.
5. chip architecture according to claim 1, it is characterized in that wherein said chip bonding pads is arranged in ring-type, and be disposed on a plurality of side areas of this active surface, those detection welding pad groups are to be positioned on the interior zone of those chip bonding pads of arranging in the form of a ring.
6. chip architecture according to claim 1, the thickness that it is characterized in that wherein said each detection welding pad is more than or equal to 2 microns and smaller or equal to 6 microns.
7. chip architecture according to claim 1, what it is characterized in that wherein said second protective layer is shaped as bulk, ring-type or strip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610099115A CN101114626B (en) | 2006-07-27 | 2006-07-27 | Wafer structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610099115A CN101114626B (en) | 2006-07-27 | 2006-07-27 | Wafer structure |
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| Publication Number | Publication Date |
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| CN101114626A CN101114626A (en) | 2008-01-30 |
| CN101114626B true CN101114626B (en) | 2010-05-12 |
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| TW201340283A (en) * | 2012-03-23 | 2013-10-01 | Chipmos Technologies Inc | Wafer structure, chip structure and stacked chip structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534853B2 (en) * | 2001-06-05 | 2003-03-18 | Chipmos Technologies Inc. | Semiconductor wafer designed to avoid probed marks while testing |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534853B2 (en) * | 2001-06-05 | 2003-03-18 | Chipmos Technologies Inc. | Semiconductor wafer designed to avoid probed marks while testing |
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