CN101114381A - Frame buffer merging - Google Patents
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- CN101114381A CN101114381A CNA200710103747XA CN200710103747A CN101114381A CN 101114381 A CN101114381 A CN 101114381A CN A200710103747X A CNA200710103747X A CN A200710103747XA CN 200710103747 A CN200710103747 A CN 200710103747A CN 101114381 A CN101114381 A CN 101114381A
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Abstract
A method for delayed frame buffer merging. The method includes accessing a polygon that relates to a group of pixels stored at a memory location, wherein each of the pixels has an existing color. A determination is made as to which of the pixels are covered by the polygon, wherein each pixel includes a plurality of samples. A coverage mask is generated corresponding the samples that are covered by the polygon. The group of pixels is updated by storing the coverage mask and a color of the polygon in the memory location. At a subsequent time, the group of pixels is merged into a frame buffer.
Description
Technical field
The present invention relates generally to graphics computer system.The present invention discloses the delayed frame buffer zone that has compression at least and merges.
Background technology
Generally speaking, be fit to handle 3D rendering data computing machine system and except traditional C PU (CPU (central processing unit)), also comprise specialized graphics processor unit (or GPU).GPU comprises the specialised hardware of the object that the computing machine that is configured to handle 3D produces.GPU is configured to one group of data model and formation " pel " (the normally triangular polygon of describing with arithmetic form) thereof are operated, and described " pel " defines shape, position and the attribute of object.The described object of the hardware handles of GPU is implemented in and produces the required calculating of 3D rendering true to nature on the display of computer system.
The performance that typical graphics is played up processing depends on the performance of the bottom hardware of system to a great extent.The high-performance real-time graph is played up the storer that requires storage 3D object data and constitute pel and is had the wide and low latency of high data carousel.Therefore, people have dropped into the data access stand-by period that a large amount of developments increase transmission bandwidth and reduce storer.
Therefore, more expensive prior art GPU subsystem (for example, being equipped with the graphics card of GPU etc.) generally includes special, expensive, this machine of high bandwidth graphic memory of big (for example, 128MB or bigger), is used for required feeds of data to GPU.This kind GPU generally includes on the bigger chip cache memory and has the registers group of low-down data access stand-by period.This type of this machine graphic memory that more cheap prior art GPU subsystem comprises is less (64MB or still less), and some the most cheap GPU subsystem do not have this machine graphic memory, comes graphics to play up data but depend on system storage.
The problem of each among the prior art GPU of the above-mentioned type is, the wide cache memory and the data carousel of register well below GPU inside of the data carousel of system storage (or this machine graphic memory) is wide.For instance, GPU needs reading order stream and scene explanation, and each pixel of definite frame buffer zone is subjected to the effect that each comprises the graph primitive of scene.This process may cause repeatedly reading and writing the frame buffer memory of storage pixel data.Though cache memory and register provide low-down access waiting time on the chip, a large amount of pixels in the given scenario (for example, 1280 * 1024,1600 * 1200 etc.) make inevitable to a large amount of accesses of frame buffer zone.
Therefore, overall figure render process is caused the mis-behave that brings out than the big stand-by period.For the GPU of its frame buffer zone of storage in system storage, mis-behave is serious far.The render process that need read and write a plurality of samples for each pixel (for example, anti-aliasing etc.) is subjected to the influence of this type of mis-behave that is brought out by the stand-by period especially easily.
Therefore, need a kind of communication path that can reduce to this machine graphic memory and/or to the data transmission circumscribed solution that the stand-by period caused of the communication path of system storage.The present invention provides novel solution for above demand.
Summary of the invention
In one embodiment, the invention process is to be used for the method by GPU enforcement that delayed frame buffer zone merges.Described method comprises access and the relevant polygon of group's pixel (for example, one or more splice sheet) that is stored in the memory location place, and wherein each pixel has existing color.Determine which pixel polygon has covered, and wherein each pixel comprises a plurality of samples.Generation is corresponding to the covering shade of the sample that is covered by polygon.By being stored in, polygonal covering shade and color upgrade described group pixel in the memory location.Sometime afterwards, described group pixel is merged in the frame buffer zone.
In one embodiment, a plurality of polygons are updated in the pixel group, whereby a plurality of follow-up polygons that the GPU access is relevant with pixel group (for example, partly covering the follow-up polygon of pixel).For in the follow-up polygon each,, each follow-up polygonal indivedual covering shade and individual colors upgrade described group pixel in the memory location by being stored in.
In one embodiment, use label value to follow the tracks of the state of the memory location of storage group pixel, wherein upgrade label value according to follow-up polygon.In addition, can use label value to determine when the memory location of the described group of storage pixel is full of, and when indication should merge to described group pixel in the frame buffer zone whereby.
In this way, delayed frame buffer zone merging process of the present invention can will (for example be accumulated to low latency time memorizer from the polygonal renewal that arrives, register, cache memory) in pixel group in, therefore rather than must read and write and cause high latency performance to worsen to frame buffer zone.Therefore, delayed frame buffer zone merging process can improve the bottleneck that the higher data access waiting time of this machine graphic memory and system storage is caused.
Description of drawings
In each figure of accompanying drawing, the present invention is described, and in each figure of accompanying drawing, same reference numbers refers to treat similar components in mode for example and not limitation.
Fig. 1 shows computer system according to an embodiment of the invention.
Fig. 2 shows the process flow diagram of the step of process according to an embodiment of the invention.
Fig. 3 shows the explanation that definite according to an embodiment of the invention polygon covers which pixel in the group.
Fig. 4 shows the figure describe according to an embodiment of the invention gained sample that the coverage of polygon on group's pixel estimated.
Fig. 5 displaying is put at the covering screening that group's pixel is stored in the memory location according to an embodiment of the invention.
Fig. 6 shows the follow-up polygon that covers described group pixel according to an embodiment of the invention.
Fig. 7 shows according to an embodiment of the invention the sample of the pixel that is covered by polygon, wherein has a pixel not to be capped fully.
Fig. 8 shows that the polygonal gained in the quadrant that is stored in memory location according to an embodiment of the invention covers shade and color.
Fig. 9 shows the follow-up polygon that covers described group pixel according to an embodiment of the invention.
Figure 10 shows according to an embodiment of the invention the sample of the pixel that is covered by polygon, wherein has a pixel not to be capped fully.
Figure 11 shows that the polygonal gained in the right lower quadrant that is stored in memory location according to an embodiment of the invention covers shade and color.
Figure 12 shows the follow-up polygon that covers pixel group according to an embodiment of the invention.
Figure 13 shows memory location according to an embodiment of the invention, and wherein first color is in the left upper quadrant of memory location.
Figure 14 shows the pixel group by delayed frame buffer zone merging process operation of the alternate embodiment according to the present invention.
Figure 15 is illustrated in the memory location according to storage colouring information under the scheme of the present invention.
Label value under the alternative plan of Figure 16 displaying alternate embodiment according to the present invention.
Figure 17 is illustrated in second explanation of the memory location of storage colouring information under the alternate embodiment of the present invention.
Figure 18 shows according to an embodiment of the invention two samples and by its corresponding color separately that covers shade indication.
Figure 19 shows according to two additional samples of the embodiment of the invention and the color separately of being indicated by its corresponding covering shade thereof.
Figure 20 shows the continuous state as the pixel group of colouring information synthetic according to one embodiment of the invention.
Figure 21 shows the figure of the relative mistake of data access between the stand-by period of illustrative system storer, this machine graphic memory and cache memory and register according to an embodiment of the invention.
Embodiment
Now will be in detail with reference to the preferred embodiments of the present invention, the example of described embodiment illustrates in the accompanying drawings.Although will describe the present invention in conjunction with the preferred embodiments, should be appreciated that and do not wish that it makes the present invention be limited to these embodiment.On the contrary, wish that the present invention contains replacement scheme, modification and the equivalent that is included in the spirit and scope of the present invention that defined by the claims of enclosing.In addition, in the detailed description of the following embodiment of the invention, state that many specific detail are so that provide thorough understanding of the present invention.Yet one of ordinary skill in the art will recognize not have putting into practice the present invention under the situation of these specific detail.In other cases, do not describe well-known method, program, assembly and circuit in detail, so that can obscure the each side of the embodiment of the invention necessarily.
Symbol and term
About to program, step, logical block, processing and other symbolic notation of the operation of data bit in the computer memory and propose some part of detailed description subsequently.These are described and representation is that the technician of technical field of data processing is used for the flesh and blood of its work is conveyed to most effectively others skilled in the art's mode.The step of (and usually) imagination program, computing machine execution, logical block, process etc. are for causing the self-consistent step or the instruction sequence of expected result herein.Described step is to carry out the step that entity is controlled to physical quantity.Usually (but unnecessary), this tittle adopts the form of electrical or magnetic signal, and described signal can be stored in computer system, transmits, makes up, relatively and in other mode control.Main for general reason, the fact proves that sometimes it is easily that these signals are called position, value, element, symbol, character, term, numeral etc.
Yet it will be appreciated that all these terms and similar terms will be associated with suitable physical quantity, and only for being applied to the mark that makes things convenient for of this tittle.Unless according to following discussion obviously with other mode concrete regulation, otherwise should be appreciated that in the present invention in full, use the discussion of for example " processing " or " access " or " compression " or " storage " or terms such as " playing up " to refer to that all computer system (for example, the computer system 100 of Fig. 1) or the action and the process of similar computing electronics, it will be expressed as the data manipulation of physics (electronics) amount in the RS of computer system and change into and be expressed as computer system memory or register or the storage of other this type of information similarly, other data of physical quantity in transmission or the display device.
Computer system platform:
Fig. 1 shows computer system 100 according to an embodiment of the invention.Computer system 100 is described the assembly of basic computer system, and described computer system is provided for certain based on hardware with based on functional execution platform of software.In general, computer system 100 comprises at least one CPU 101, system storage 115 and at least one Graphics Processing Unit (GPU) 110.CPU 101 can be coupled to system storage 115 via bridge assembly 105, perhaps can be directly coupled to system storage 115 via the Memory Controller (not shown) of CPU 101 inside.Bridge assembly 105 (for example, north bridge) can support to connect the expansion bus (for example, expansion bus 106) of various I/O devices (for example, one or more hard disk drives, Ethernet Adaptation Unit, CD ROM, DVD etc.).GPU 110 is coupled to display 112.Can be coupled to system 100 by optionally that one or more are extra GPU, with its computing power of further increase.GPU 110 is coupled to CPU 101 and system storage 115 via bridge assembly 105.System 100 can be configured as (for example) desktop computer systems or server computer system, and it has the strong universal cpu 101 that the dedicated graphics of being coupled to is played up GPU 110.In this embodiment, can comprise the assembly that adds peripheral bus, special this machine graphic memory, IO device and analog.Similarly, system 100 (for example can be configured as hand-held device, mobile phone etc.) or top set video game console device, the Xbox that for example can buy from Washington Microsoft Corporation of Redmond and the PlayStation3 that can buy from Tokyo Sony Computer Entertainment Corporation.
Should be appreciated that, GPU 110 can be configured as discrete component, via connector (for example be designed to, AGP slot, PCI-Express slot etc.) (for example be coupled to the discrete graphics card of computer system 100, discrete integrated circuit die, be directly installed on the motherboard), or be configured as the integrated GPU of (for example, be integrated in bridging chip 105 in) in the integrated circuit die that is included in the computer system chipset assembly.In addition,, can optionally comprise this machine graphic memory 116, so that the storage of high bandwidth graph data to be provided for GPU 110.
Embodiments of the invention:
Embodiments of the invention are implemented a kind of method that delayed frame buffer zone merges that is used for.In one embodiment, GPU utilizes the subdivision of label value and frame buffer zone splicing sheet (frame buffer tile) to store and covers shade (coveragemask).Cover the level of coverage (number of the sample that for example, be capped) of shade corresponding to the splicing sheet.The pixel that comprises frame buffer zone splicing sheet can be by storing with compressive state in the memory location that polygonal color and described polygonal covering shade is stored into the described splicing sheet of storage.In addition, be stored in described memory location, extra polygon can be rendered in the splicing sheet by being used for new polygonal follow-up covering shade and being used for described new polygonal color.
This makes and can under the situation that needn't carry out access to frame buffer zone and write new polygon be rendered in the splicing sheet.For instance, can before the splicing sheet is full of, use delayed frame buffer zone merging process polygon to be rendered in the splicing sheet, when the splicing sheet is full of, the splicing sheet can be merged in the frame buffer zone.In this way, delayed frame buffer zone merging process of the present invention can make be accumulated to GPU 110 from the polygonal renewal that arrives low latency time memorizer (for example, register, cache memory) limited size in the splicing sheet in, therefore and nonessential frame buffer zone (for example, being stored in this machine graphic memory 116 or the system storage 115) is read and writes and causes that high latency performance worsens.Delayed frame buffer zone merging process is hereinafter described in Fig. 2 in more detail.
Fig. 2 shows the process flow diagram of the step of process 200 according to an embodiment of the invention.Describe as Fig. 2, process 200 is described according to an embodiment of the invention the operation steps that comprises in the delayed frame buffer zone merging process that the GPU (for example, GPU 110) by computer system (for example, computer system 100) implements.
Under the situation of the illustrative computer system 100 of Fig. 1 and Fig. 3-13 and describe the step of process 200 embodiment of Fig. 2 with reference to it.
In step 202, process 200 determines which pixel is covered by polygon in the group.Among Fig. 3 explanation this about which pixel by determining that polygon covers, Fig. 3 shows the figure that is just standing the polygon 301 of rasterisation at the group that comprises eight pixels.Fig. 3 shows two the splicing sheets side by side that respectively have four pixels.Each pixel further is divided into four sub-pixels, and wherein each sub-pixel has a sampled point, and it is depicted as " x " in Fig. 3, thereby obtains anti-aliasing middle 16 sampled points that use of (for example) 4x.Fig. 4 shows the sample of gained, whereby, and by the sampled point deepening of polygon covering, and the not deepening of sampled point that does not cover by polygon.As shown in Figure 4, pixel is labeled as A, B, C, D, E, F, G and H.Note that pixel H is not capped fully.
In step 203, produce covering shade corresponding to the sample that covers by polygon 301.In one embodiment, cover shade and can be embodied as a shade, wherein each sample of group respectively has one.Whether therefore, 16 samples of group can be represented in 16 positions, wherein be capped according to described sample and set each.Therefore, polygon 301 parts cover the pixel of group and therefore part cover under the situation of described 16 samples, in the memory location that can store storage splicing sheet into this information (that is level of coverage) is updated in the group by covering shade and color with the gained of polygon 301.
Importantly, should notice that this renewal can take place in the storer of GPU 110 inside.This storer is storage pixel group at polygon raster display and rendered pixel group the time.Therefore, can and be rendered in the pixel group polygon raster display, and needn't and then the pixel group through upgrading be write back to frame buffer zone (for example, reading-revise-write) from frame buffer zone read pixel group, renewal pixel group.
In step 204, by upgrading pixel group in the memory location that polygonal covering shade and respective color is stored into group.This shows in Fig. 5.It should be noted that covering shade is stored in owing to pixel H is not capped in the storer that causes for sky fully.As Fig. 5 explanation, the memory location of storage pixel group is depicted as the rectangle 500 with four quadrants.The compressed background color of eight pixels of 1/4th (for example, left upper quadrant) storage in space, wherein (for example) single last polygon covers all eight pixels fully, and therefore can and be stored as a kind of color of each pixel with sample 4 to 1 compressions.The right upper quadrant storage covers shade 501 and is used for a kind of color of pixel A to G.As mentioned above, which sample covers shade indicates covered by polygon.
In this way, delayed frame buffer zone merging process of the present invention can will (for example be accumulated to low latency time memorizer from the polygonal renewal that arrives, register, cache memory) in pixel group in, and nonessential frame buffer zone read and writes.
Still, in step 205, determine whether memory location 500 is full of referring to the process 200 of Fig. 2.If the memory location underfill, process 200 can proceed to step 206 and continue and handle the follow-up polygon relevant with pixel group so, and for each follow-up polygon, execution in step 202 to 204.For instance, Fig. 6 shows the follow-up polygon 601 that covers pixel group, Fig. 7 shows the sample of the pixel that is covered by polygon 601, and wherein pixel A is not capped fully, and Fig. 8 shows that the gained of the polygon 601 in the left lower quadrant that is stored in memory location 500 covers shade 801 and color.Fig. 9 then shows the follow-up polygon 901 that covers pixel group, Figure 10 shows the sample of the pixel that is covered by polygon 901, wherein pixel C, D, G and H are not capped fully, and Figure 11 shows that the gained of the polygon 901 in the right lower quadrant that is stored in memory location 500 covers shade 1101 and color.
In this way, delayed frame buffer zone merging process of the present invention can be accumulated in the pixel group from the polygonal renewal that arrives, and nonessential frame buffer zone is read, revises and writes.Therefore delayed frame buffer zone merging process has improved the bottleneck that the higher data access waiting time by this machine graphic memory and system storage causes.As mentioned above, available follow-up polygon upgrades pixel group and need not force to merge to enter and be used for each polygonal frame buffer zone.
In step 207, when as shown in figure 11, when memory location 500 was full of, when follow-up polygon arrived, the informational needs decompress(ion) that is stored in the memory location 500 contractd synthetic with new polygon.Then this information can be merged in the frame buffer zone.In case merge in the frame buffer zone, information just can be left the form of uncompressed.
In one embodiment, after merging to information in the frame buffer zone, GPU 110 is the colouring information of packed pixel group again, and with compressed format pixel group is stored in the low latency time memorizer.Can use above-mentioned covering shade and color to compress this colouring information.This process illustrates that in Figure 12 wherein follow-up polygon 1201 covers pixel group.Information decompress(ion) in being stored in memory location 500 contract with polygon 1201 synthetic after, information compressed again and be stored in the memory location 500, as shown in figure 13.Figure 13 shows memory location 500, wherein first color in left upper quadrant (for example, background color), cover shade 1301 and corresponding to second color that covers shade 1301 in right upper quadrant, and cover shade 1302 and corresponding to the 3rd color that covers shade 1302 in left lower quadrant.Therefore, after compressing again, the right lower quadrant of memory location 500 is opened to receive another polygon.
It should be noted that all samples in each pixel will have identical color so if receive the follow-up polygon of all pixels that cover group fully, and therefore can be stored in (for example) left upper quadrant through 4 to 1 compressions and as single color.Although it should be noted that in the situations of the many samplings of 4x and describe embodiments of the invention, the present invention is more useful in the application of situation neutralization except that anti-aliasing of the more high-grade many samplings of practice (for example, the many samplings of 8x etc.).
In addition, should notice in one embodiment that GPU 110 uses label value to follow the tracks of the state of the memory location 500 that is used for pixel group.This label value can be followed the tracks of GPU 110 to be updated to the polygonal number in the memory location 500.For instance, in one embodiment, label value can be embodied as 3 place values, wherein 4 to 1 compressions of a kind of color of (for example) label value 0 each pixel of indication, 4 to 1 compressions that two quadrants of label value 1 instruction memory position 500 are occupied, as shown in Figure 5,4 to 1 compressions that three quadrants of label value 3 instruction memory positions 500 are occupied, as shown in Figure 8, and whole four quadrants of label value 4 instruction memory positions 500 occupied 4 to 1 the compression, as shown in figure 11.
The delayed frame buffer zone merging process of Figure 14 to 16 explanation alternate embodiment according to the present invention.In alternate embodiment, label is embodied as the free pointer that points in the memory location 500.In this embodiment, memory location 500 can be supported nearly six renewals, and needn't carry out the merging with frame buffer zone.In this embodiment, can implement label value makes it have following meaning:
The 0=uncompressed;
1=compresses fully, the free pointer at sample 8 places;
Many segments of 2=, sample 12 place's free pointers;
The free pointer at 3=sample 16 places;
The free pointer at 4=sample 20 places;
The free pointer at 5=sample 24 places;
The free pointer at 6=sample 28 places;
9=memory location 500 is full of, but still unsettled.
Figure 14 shows to have color pixel group according to indicated sample position.Figure 15 shows memory location 500, wherein stores colouring information under the scheme of describing in the discussion of Fig. 2 above.Figure 16 shows the label value according to alternate embodiment, wherein label value 1 is shown as " 1 " at sample position 8 places that are stored in memory location 500, label value 2 is shown as " 2 " that are stored in sample position 16 places, and similarly, is shown as " 6 " at sample position 28 places up to label value 6.Figure 17 shows memory location 500, wherein stores colouring information under the scheme of alternate embodiment of the present invention.Therefore, as shown in figure 17, pixel group can have background color and reach the color of six kinds of new renewals, and wherein the covering shade 1701-1702 of gained is stored in sample position 12 and 8 respectively, and the color that is associated with covering shade 1701-1702 is adjacent and stores.
Figure 18 to 20 visually illustrates shade is caught renewal from the polygon of follow-up arrival the mode that covers.For instance, Figure 18 shows two samples and the color separately of being indicated by covering shade 1701 thereof, and Figure 19 shows two samples and the color separately of being indicated by covering shade 1702 thereof.Figure 20 shows four continuous states of pixel group, its explanation is in the mode of the end-state of the plain group of memory location 500 built-in standing statues, wherein state 2002 is showed initial two samples, state 2003 is showed with latter two sample, state 2004 is showed the color synthetic with background color, and end-state 2005 describes to be stored in the gained information in the memory location 500.
Therefore, according to alternate embodiment, need 16 bytes to write, it not necessarily writes more effective than 32 bytes, but still saves once reading from frame buffer zone.By darker pixel or bigger pixel footprint area, still available 3 labels of alternate embodiment method play a role.In above-mentioned example, pixel group comprises eight pixel footprint area.Comprise in the pixel footprint area under the situation of 16 pixel groups, process will then be come memory allocated with eight sample increments or 32 byte particles.Perhaps, under the situation that just writes 8 byte pixel, 2 * 4 pixel groups fully work and write to produce 32 bytes as used herein.
Figure 21 shows Figure 21 00 according to an embodiment of the invention, the relative mistake of data access between the stand-by period of its illustrative system storer 115, this machine graphic memory 116 and cache memory 2101 and register 2102.As mentioned above, delayed frame buffer zone merging process of the present invention can will (for example be accumulated to low latency time memorizer from the polygonal renewal that arrives, register 2102, cache memory 2101) in pixel group in, reduce the number of times that reads and write whereby, and reduce the mis-behave that causes by the high storage access stand-by period whereby frame buffer zone.This attribute can improve performance at frame buffer zone (for example, graph data 2120) when being stored in this machine graphic memory 116, and can improve performance on much higher degree when frame buffer zone (for example, graph data 2110) is stored in the system storage 115.In this way, therefore delayed frame buffer zone merging process has improved the bottleneck that the higher data access waiting time by this machine graphic memory 116 and system storage 115 causes.
Simplified summary, the present invention discloses following content:
Notion is used for the method that frame buffer zone merges for 1. 1 kinds, and it comprises:
Access and the relevant polygon of pixel group that is stored in memory location, each in the wherein said pixel has existing color;
Determine which pixel is covered by described polygon in the described pixel, wherein each pixel comprises a plurality of samples;
Generation is corresponding to the covering shade of the sample that is covered by described polygon;
By being stored in, described polygonal described covering shade and color upgrade described pixel group in the described memory location; With
Subsequently described pixel group group is merged in the frame buffer zone.
Notion 2. is according to notion 1 described method, and it further comprises:
Access and the relevant a plurality of follow-up polygon of described pixel group; With
For in the described follow-up polygon each,, each follow-up polygonal indivedual covering shade and individual colors upgrade described pixel group in the described memory location by being stored in.
Notion 3. is according to notion 2 described methods, and it further comprises:
Use label value to follow the tracks of the state of the memory location of the described pixel of storage group; With
Upgrade described label value according to described follow-up polygon.
Notion 4. is according to notion 2 described methods, and it further comprises:
When the memory location of determining the described pixel of storage group is full of; With
When memory location is full of, the pixel group group is merged in the frame buffer zone.
Notion 5. is according to notion 4 described methods, and it further comprises:
After merging, store in the memory location pixel group is compressed in the memory location by at least one being covered shade and at least a color according to color of pixel.
Notion 6. is according to notion 4 described methods, the wherein said number of times that is configured in the frame buffer zone reduce to the access of described frame buffer zone that the pixel group group is merged to.
Notion 7. is according to notion 1 described method, and wherein said pixel group is updated to causes 4 to 1 compressions in the memory location.
The computer-readable media of 8. 1 kinds of storage computation machines of notion readable code, described computer-readable code causes described computer system to implement to be used for the computer-readable media that delayed frame buffer zone merges when being carried out by the computer system with the processor that is coupled to storer, and it comprises:
Access and the relevant polygon of pixel group that is stored in memory location, each in the wherein said pixel has existing color;
Determine which pixel is covered by described polygon in the described pixel, wherein each pixel comprises a plurality of samples;
Generation is corresponding to the covering shade of the sample that is covered by described polygon;
By being stored in, described polygonal described covering shade and color upgrade described pixel group in the described memory location;
Access and the relevant a plurality of follow-up polygon of described pixel group;
For in the described follow-up polygon each,, each follow-up polygonal indivedual covering shade and individual colors upgrade described pixel group in the described memory location by being stored in; With
Subsequently described pixel group group is merged in the frame buffer zone.
Notion 9. is according to notion 8 described computer-readable medias, and it further comprises:
Use label value to follow the tracks of the state of the memory location of the described pixel of storage group; With
Upgrade described label value according to described follow-up polygon.
Notion 10. is according to notion 8 described computer-readable medias, and it further comprises:
When the memory location of determining the described pixel of storage group is full of; With
When memory location is full of, the pixel group group is merged in the frame buffer zone.
Notion 11. is according to notion 10 described computer-readable medias, and it further comprises:
After merging, store in the memory location pixel group is compressed in the memory location by at least one being covered shade and at least a color according to color of pixel.
Notion 12. is according to notion 10 described computer-readable medias, the wherein said number of times that is configured in the frame buffer zone reduce to the access of described frame buffer zone that the pixel group group is merged to.
Notion 13. is according to notion 8 described computer-readable medias, and wherein said pixel group is updated to causes 4 to 1 compressions in the memory location.
14. 1 kinds of computer systems of notion, it comprises:
Processor;
System storage, it is coupled to described processor; With
Graphics Processing Unit, it is coupled to described processor, wherein said graphic process unit is configured to computer readable code executed, and described computer-readable code causes described graphic process unit to implement a kind of method that delayed frame buffer zone merges that is used for, and described method comprises:
Access and the relevant polygon of pixel group that is stored in memory location, each in the wherein said pixel has existing color;
Determine which pixel is covered by described polygon in the described pixel, wherein each pixel comprises a plurality of samples;
Generation is corresponding to the covering shade of the sample that is covered by described polygon;
By being stored in, described polygonal described covering shade and color upgrade described pixel group in the described memory location;
Access and the relevant a plurality of follow-up polygon of described pixel group;
For in the described follow-up polygon each,, each follow-up polygonal indivedual covering shade and individual colors upgrade described pixel group in the described memory location by being stored in; With
Subsequently described pixel group group is merged in the frame buffer zone.
Notion 15. is according to notion 14 described computer systems, and it further comprises:
Use label value to follow the tracks of the state of the memory location of the described pixel of storage group; With
Upgrade described label value according to described follow-up polygon.
Notion 16. is according to notion 14 described computer systems, and it further comprises:
When the memory location of determining the described pixel of storage group is full of; With
When memory location is full of, the pixel group group is merged in the frame buffer zone.
Notion 17. is according to notion 16 described computer systems, and it further comprises:
After merging, store in the memory location pixel group is compressed in the memory location by at least one being covered shade and at least a color according to color of pixel.
Notion 18. is according to notion 14 described computer systems, and it further comprises:
Use label value as free pointer, with the state of the memory location of following the tracks of storage pixel group; With
Upgrade described label value according to described follow-up polygon.
Notion 19. is according to notion 14 described computer systems, and wherein said frame buffer zone is stored in the system storage.
Broadly, the present invention discloses a kind of method that delayed frame buffer zone merges that is used at least.Described method can comprise access and the relevant polygon of pixel group that is stored in memory location, and each in the wherein said pixel has existing color.Can determine which pixel is covered by described polygon in the described pixel, wherein each pixel comprises a plurality of samples.
Can produce covering shade corresponding to the sample that is covered by described polygon.Can upgrade described pixel group in the described memory location by described polygonal described covering shade and color are stored in.In later time, described pixel group group can be merged in the frame buffer zone.
Presented above description for the purpose of illustration and description to specific embodiment of the present invention.Do not wish that it is completely or limit the invention to the precise forms that disclosed, and according to above teaching, many modifications and variations are possible.Select and describe embodiment,, make others skilled in the art utilize the present invention best whereby and be suitable for expecting the various embodiment with various modifications of special-purpose so that explain principle of the present invention and practical application thereof best.Wish that scope of the present invention defines by being additional to claims of the present invention and equivalent thereof.
Claims (7)
1. computer system, it comprises:
Processor;
System storage, it is coupled to described processor; With
Graphics Processing Unit, it is coupled to described processor, and wherein said graphic process unit is configured to computer readable code executed, and described code causes described graphic process unit to implement to be used for the method that delayed frame buffer zone merges, and described method comprises:
Access and the relevant polygon of group's pixel that is stored in the memory location place, each in the wherein said pixel has existing color;
Determine described polygon covers which pixel in the described pixel, and wherein each pixel comprises a plurality of samples;
Generation is corresponding to the covering shade of the sample that is covered by described polygon;
By being stored in, described polygonal described covering shade and color upgrade described group pixel in the described memory location;
Access and the relevant a plurality of follow-up polygon of described group pixel;
For in the described follow-up polygon each,, each follow-up polygonal indivedual covering shade and individual colors upgrade described group pixel in the described memory location by being stored in; With
Subsequently described group pixel is merged in the frame buffer zone.
2. computer system according to claim 1, it further comprises:
Use label value to follow the tracks of the state of the memory location of the described group of storage pixel; With
Upgrade described label value according to described follow-up polygon.
3. computer system according to claim 1, it further comprises:
When the memory location of determining the described group of storage pixel is full of; With
When memory location is full of, described group pixel is merged in the described frame buffer zone.
4. computer system according to claim 3, it further comprises:
After described merging, described group pixel is compressed in the described memory location by at least one covering shade being stored in the described memory location with at least one color according to described color of pixel.
5. computer system according to claim 1, it further comprises:
Use label value to follow the tracks of the state of the memory location of the described group of storage pixel as free pointer; With upgrade described label value according to described follow-up polygon.
6. computer system according to claim 1, wherein said frame buffer zone is stored in the described system storage.
7. computer system according to claim 1, wherein said frame buffer zone are stored in this machine graphic memory that is coupled to described Graphics Processing Unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80274606P | 2006-05-22 | 2006-05-22 | |
| US60/802,746 | 2006-05-22 |
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| CN2007101037484A Active CN101114382B (en) | 2006-05-22 | 2007-05-22 | Frame buffer merging |
| CN200710103747XA Active CN101114381B (en) | 2006-05-22 | 2007-05-22 | Frame buffer merging |
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| CN2007101037484A Active CN101114382B (en) | 2006-05-22 | 2007-05-22 | Frame buffer merging |
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| CN102103739A (en) * | 2009-12-17 | 2011-06-22 | Arm有限公司 | Graphics processing systems |
| CN113473226A (en) * | 2021-08-09 | 2021-10-01 | 深圳软牛科技有限公司 | Method and device for improving video rendering efficiency, computer equipment and storage medium |
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| CN113473226A (en) * | 2021-08-09 | 2021-10-01 | 深圳软牛科技有限公司 | Method and device for improving video rendering efficiency, computer equipment and storage medium |
| CN113473226B (en) * | 2021-08-09 | 2023-02-14 | 深圳软牛科技有限公司 | Method and device for improving video rendering efficiency, computer equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101114382B (en) | 2010-09-01 |
| TW200820131A (en) | 2008-05-01 |
| CN101114381B (en) | 2012-02-22 |
| CN101114382A (en) | 2008-01-30 |
| TW200820132A (en) | 2008-05-01 |
| TWI498850B (en) | 2015-09-01 |
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