CN101110661A - Dithering cache regulation means for circuit simulation system - Google Patents
Dithering cache regulation means for circuit simulation system Download PDFInfo
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Abstract
The present invention discloses a dithering buffer adjustment method in a circuit simulating system including procedures below: Dithering buffering in a preset period is monitored to observe existence of quite higher or lower time-delay dithering of a group-based exchange network. As the time-delay dithering exceeds an upper dithering threshold, it is necessary to reset a new dithering buffer depth and an upper and a lower dithering threshold to increase the dithering buffer. While the time-delay dithering is lower than the lower dithering threshold, it needs to reset a new dithering buffer depth and a new upper and a lower dithering threshold to decrease the dithering buffer. As the time-delay dithering ranges between the upper threshold and the lower threshold, a next preset period is monitored. The method arranges dithering buffer variation to realize automatic adjustment according to variations of network time-delay dithering, makes the time-delay dithering led in by the group-based exchange network absorbed at most and optimizes the time delay led in the dithering buffer.
Description
Technical field
The present invention relates to circuit simulation (CES, Circuit Emulation Service) field, particularly relate to a kind of dithering cache regulation means of circuit simulation system.
Background technology
Along with popularizing of IP technology, the carrying multiple business more and more becomes the trend of network technical development on packet switching network, wherein a kind of typical business is exactly the time division multiplexing (TDM that utilizes packet switched network transmission traditional, Time Division Multiplexing) the various Circuit Services in the network, the technology that it used is exactly the CES technology.
The basic principle of CES technology as shown in Figure 1, this technology is built a passage on the packet switching network (PSN, Packet SwitchNetwork), by increasing packet header at the source end, seal each tdm data frame of dress with grouping, again by the channel transfer built in the packet switching network to destination.Destination regenerates synchronizing clock signals after receiving packet, remove the packet header in the packet simultaneously, remaining reduction of data is become original tdm data frame, thereby make the TDM equipment at network two ends not need to be concerned about whether the network of its connection is the TDM network.Interworking unit among Fig. 1 (IWF, InterWork Function) equipment plays the effect of CES gateway, is the node of tdm data frame turnover packet switching network.
Because the packet switching network is a kind of network of doing one's best, unavoidably can be when transmitting the TDM business because some uncertain factors are introduced in the time-delay of packet switching network.For example: the delay jitter of introducing (PDV, Packet Delay Variation) is transmitted in grouping bag storage, need be absorbed at destination, otherwise can influence the quality of output end signal clock.This just needs the destination equipment of CES system to provide a kind of dithering cache to absorb PDV, and the effect that this dithering cache plays is: the bag that will divide into groups is adjusted in the correct sequence, and as required suitable time-delay is carried out in grouping, to compensate the deviation in its network delay.In addition, the TDM service needed clock information that the business of recovering is carried from grouping bag is finished by the timing recovery algorithms as this step 1.
Figure 2 shows that the structure of dithering cache in the CES system, this buffer memory generally is a first in first out (FIFO, First In First Out) buffer, wherein, write pointer writes successively according to the order of the actual packet of receiving, because the deviation of grouping packet network time-delay, destination receives that the order of grouping bag may be upset, if receive the grouping bag that early arrives, then need to vacate corresponding position and leave the late grouping bag that arrives for, like this can be to out of order adjustment of grouping bag.Simultaneously, the clock that recovers according to clock recovery algorithm of the read pointer bag that will divide into groups is successively read.
Because write pointer writes the position of grouping bag in buffer memory unfixing, so can there be a shake at random in write pointer with respect to the position of read pointer, this shake shows as in Fig. 2: write pointer is shake back and forth between buffer memory depth capacity that is used and the buffer memory minimum-depth that used, this jitter range is exactly the PDV of packet switching network, if dithering cache is enough big, the business clock of TDM stably that the timing recovery algorithms just can recover, this moment, dithering cache can absorb the delay jitter of packet switching network well.
The size of described dithering cache and the PDV of packet switching network are closely related, and when the network of grouping bag process changed, for example network node changed, and perhaps offered load changes, and can cause the variation of PDV.Like this, should be able to dynamic change with regard to the setting that requires the dithering cache size: when packet switching network PDV becomes big, must increase dithering cache, to absorb bigger PDV with PDV, otherwise can cause overflowing of dithering cache, can't recover correct clock information and tdm data frame; When PDV reduces, must reduce dithering cache, otherwise very big always by the formed time-delay of dithering cache meeting, thus can cause the TDM service transmission quality to descend.
In the prior art, setting for CES thrashing buffer memory, generally be to depend on experience to finish by hand, or based on finishing on the basis to a large amount of static statistics data analyses, or by the professional practical operation situation of monitoring, for example whether the TDM business is delayed time excessive or is not had the situation of packet loss to determine.These methods are not the technology of adjusting dithering cache automatically, cause the transmission quality of TDM business to descend easily even interrupt, perhaps since dithering cache be provided with and excessively cause time-delay too big, transmission quality decline.
Summary of the invention
In view of this, main purpose of the present invention is to provide the dithering cache regulation means of a kind of CES system, and the PDV that packet switching network is introduced can be absorbed as much as possible, and the time-delay that CES is introduced can be optimised.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of dithering cache regulation means of circuit simulation system, predetermined amount of time and shake Upper threshold J1 and shake Lower Threshold J2 are set, this method may further comprise the steps: monitor the dithering cache in the predetermined amount of time, if Jk is greater than described shake Upper threshold J1 in the network delay that monitors shake, execution in step B then, if described delay jitter Jk is less than described shake Lower Threshold J2, execution in step C then, if described delay jitter Jk then returns steps A and continues next predetermined amount of time of monitoring between described shake Upper threshold J1 and shake Lower Threshold J2; Increase dithering cache degree of depth J0, and adjust described shake Upper threshold J1 and shake Lower Threshold J2, make described delay jitter Jk between described shake Upper threshold J1 and shake Lower Threshold J2; Reduce dithering cache degree of depth J0, and adjust described shake Upper threshold J1 and shake Lower Threshold J2, make described delay jitter Jk between described shake Upper threshold J1 and shake Lower Threshold J2; Wherein, J2＜J1＜J0.
Increase the dithering cache depth step or reduce in the dithering cache depth step, increase or reduce after new dithering cache degree of depth J0 satisfy following the relation with described delay jitter Jk: described delay jitter Jk equals 70% of new dithering cache degree of depth J0; And the value of Lower Threshold satisfies in the adjusted shake: shake Upper threshold J1 and shake Lower Threshold J2 are respectively 80% and 20% of new dithering cache degree of depth J0.
Wherein, described monitoring is: monitor an above predetermined amount of time; If in each predetermined amount of time, delay jitter Jk then carries out increase dithering cache depth step greater than shake Upper threshold J1; If in each predetermined amount of time, all less than shake Lower Threshold J2, then execution reduces the dithering cache depth step to delay jitter Jk; Otherwise continuing execution in step A monitors.
Wherein, also further comprise initialization step before the described detection step: after professional the connection, the network delay shake of a time period of monitoring is provided with initial dithering cache degree of depth J0 according to this delay jitter that monitors then.
In the dithering cache regulation means of circuit simulation system of the present invention, increasing the dithering cache depth step also comprises: the speed of slowing down sense data, the write pointer of dithering cache is moved to the center of the new dithering cache degree of depth J0 after the increase, and wherein sense data rate variations rate requires decision by the TDM service timing index that is transmitted.
Wherein, the value of described new dithering cache degree of depth J0 and described delay jitter Jk satisfy following relation: described delay jitter Jk equals 70% of new dithering cache degree of depth J0, and adjusted shake Upper threshold J1 is respectively 80% and 20% of new dithering cache degree of depth J0 with shake Lower Threshold J2.
In the dithering cache regulation means of circuit simulation system of the present invention, reducing the dithering cache depth step is specially: the new dithering cache degree of depth J0 that reduces is set, and the speed of quickening sense data, the write pointer of dithering cache is moved to the center of described new dithering cache degree of depth J0, and wherein sense data rate variations rate requires decision by the TDM service timing index that is transmitted; New shake Upper threshold J1 and shake Lower Threshold J2 are set, make new being provided with satisfy J2＜Jk＜J1＜J0.
Wherein, the value of described new dithering cache degree of depth J0 and described delay jitter Jk satisfy following relation: described delay jitter Jk equals 70% of new dithering cache degree of depth J0, and adjusted shake Upper threshold J1 is respectively 80% and 20% of new dithering cache degree of depth J0 with shake Lower Threshold J2.
In the dithering cache regulation means of circuit simulation system of the present invention, be the cycle with described predetermined amount of time, repeated execution of steps detects step, increases the dithering cache depth step and reduces the dithering cache depth step.
The dithering cache regulation means of CES provided by the present invention system, actual conditions according to the network delay shake that monitors are adjusted the dithering cache size automatically, do not need manually to be provided with the size of change dithering cache according to experience or statistical analysis, simplified operating process thus, can provide suitable dithering cache to absorb delay jitter, optimize the TDM transmission quality, specifically, the process of adjusting dithering cache is automatic fully, does not need the user to participate in.
The present invention has optimized because the time-delay that dithering cache produced makes the CES system because the time-delay that dithering cache produced reduces as far as possible under the situation that PDV reduces; And in the process of adjusting dithering cache, the speed that the present invention adjusts according to the index request decision of institute's transport service can accomplish that the clock Transfer Quality of TDM business is unaffected.
Description of drawings
Fig. 1 is the structural representation of CES system in the prior art;
Fig. 2 is the structural representation of CES thrashing buffer memory in the prior art;
Fig. 3 is the flow chart of CES thrashing cache regulation means of the present invention;
Fig. 4 is for increasing the realization flow figure of dithering cache in the CES thrashing cache regulation means of the present invention;
Fig. 5 is for reducing the realization flow figure of dithering cache in the CES thrashing cache regulation means of the present invention.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.For convenience of description, abbreviate packet switching network as network below.
As shown in Figure 3, the dithering cache regulation means of CES of the present invention system may further comprise the steps:
Step 101: the also dithering cache of initialization CES system is set.
After professional the connection, destination obtains the PDV of network, and initial dithering cache length is set then.Here, the professional gateway and the intermediate node that are meant network of being communicated with disposes correctly, makes the tdm data frame be encapsulated as the grouping bag via the source end, passes through packet network then, recovers the tdm data frame by destination.After professional the connection, source end and destination can both continue transmitting-receiving grouping bag, and dithering cache is started working, and regularly recovery algorithms also can be started working, and beginning recovers the clock information of TDM gradually.
In order to guarantee the transmission quality of TDM business, begin dithering cache most and be set to maximum automatically by destination, this maximum is generally chosen by empirical value.Thereupon through the analysis of a predetermined amount of time, this time period length can be provided with by the user, it generally is an empirical value, such as about 1 minute, can obtain the PDV of network by the jitter range of monitoring write pointer in dithering cache, jitter range such as write pointer is Jk, and promptly the PDV of network equals Jk.Jk is the foundation that is provided with of dithering cache, and dithering cache comprises three parameters: dithering cache degree of depth J0, shake Upper threshold J1 and shake Lower Threshold J2.These two thresholdings that thresholding in fact also is the write pointer jitter range should not exceed J1 in the write pointer jitter range, if exceed J1, just need increase adjustment to dithering cache; If the write pointer jitter range should less than J2, just need not reduce to adjust less than J2 to dithering cache.The selection of this several values will meet the following conditions:
J2＜Jk＜J1＜J0 (1)
In addition, to the setting of J2 and J1 and J0, can be according to become a kind of mode of fixed proportion to select with Jk, as long as relational expression (1) is satisfied in the selection of this ratio.
As a preferred embodiment of the present invention, select to satisfy between this Several Parameters following proportionate relationship:
J2＝J0×20％
J1＝J0×80％
Jk＝J0×70％
With the initial value of J0, and shake Upper threshold and shake Lower Threshold: J1 and J2 are set as the dithering cache degree of depth.
Step 102: the dithering cache of a predetermined amount of time of monitoring, whether the PDV of observation grid exists excessive or too small situation.
Dithering cache is monitored in real time, can do monitoring to the jitter range of write pointer every a predetermined amount of time T, the selection of this time period length is determined by actual conditions.If the select time section is oversize, then the dithering cache setting can not change with PDV better, and the select time section is too short, then can increase the expense of destination.In addition, when adjusting dithering cache, need to adjust the speed of sense data bag, if this adjustment process is too fast, then can influence the quality of the TDM clock information that recovers, so it is too short that the monitoring time section also should not be set.As the preferred embodiments of the present invention, can select T=10 minute.Suppose in the time period T that the jitter range of write pointer is Jk, if Jk still can satisfy: J2＜Jk＜J1, think also that then the delay jitter of network does not change to the degree that needs to adjust dithering cache.If but Jk＞J1 illustrates that then the delay jitter of packet network has exceeded the shake Upper threshold, must increase dithering cache; If Jk＜J2 illustrates that then the delay jitter of packet network has exceeded the shake Lower Threshold, can reduce dithering cache.
In this step, too frequent in order to prevent adjustment, adjust again after can confirming through the monitoring of a plurality of time period T.The number of monitoring time section is decided by actual conditions, and in this preferred embodiment, the company's of the selection observation process first time is in the monitoring that repeats of interior totally three time period T.
If all satisfy Jk＞J1 in continuous three time period T, just need do to increase and adjust dithering cache; If but it is too big to monitor Jk in first time period T, for example Jk＞J0 * 95% just illustrates that being provided with of dithering cache is seriously less than normal, must increase adjustment to dithering cache, and not need to confirm twice again at once; If desired dithering cache is done to increase and adjust, with regard to execution in step 103.
Similarly, if all satisfy Jk＜J2 in continuous three time period T, just need do to reduce to adjust execution in step 104 to dithering cache.
Step 103: increase dithering cache.
As shown in Figure 4, increase dithering cache and comprise two sub-steps:
If the Jk that monitors, illustrates that there is excessive situation in PDV greater than former J1.So just need to increase dithering cache.It is that Lower Threshold J1 and J2 are gone up in J0 and shake that the new dithering cache degree of depth is set.These parameters still require to satisfy:
J2＜Jk＜J1＜J0
J2＝J0×20％
J1＝J0×80％
Jk＝J0×70％
Wherein, except first relational expression, other proportionate relationship all can freely be adjusted, and clashes only otherwise with first relational expression get final product, and 20% in the formula, 80% and 70% is a kind of selective value in the present embodiment.Jk is exactly the mean value of the write pointer jitter range that monitoring obtains in first three time period T; If Jk is more than 95% of original J0 in the last time period T, and just directly do not adjust through the monitoring of three time periods, then Jk just directly gets the Jk of write pointer in the last time period T.
If direct mobile write pointer causes erroneous judgement to the center of new dithering cache degree of depth J0 immediately with regard to making Jk easily less than new J2.So select by slowing down the method for sense data speed, the write pointer of dithering cache is moved to the center of new dithering cache degree of depth J0, the reason of selecting to move to the center is to overflow from the buffer memory two ends for the shake that prevents write pointer.Along with slowing down of the speed of sense data, cached data packet increases between the read-write pointer, that is to say that dithering cache degree of depth J0 increases thereupon.The operation that slows down sense data speed is realized by destination control.
In this substep, owing to slow down the speed of sense data, can cause the professional regularly variation of quality of the TDM of institute, for example in speech business, it is slack-off that the speed of slowing down sense data can cause exporting speech frequency, and in the TDM business, requires strict more to the rate of change of the clock information of output, so the process of the write pointer of mobile dithering cache should guarantee that sense data rate variations rate satisfies the index request of institute's transport service.
For transmission tdm data frame, should guarantee that sense data rate variations rate must satisfy the requirement of the professional timing index of TDM, this index request is different with practical application, for example: need to satisfy the index request of functional area G.823, still satisfy synchronous mouthful index request G.823.Owing to above reason, slow down the speed of sense data, the write pointer of dithering cache is moved in the process of center of new J0, sense data rate variations rate should monitored and real-time adjustment, and the foundation of adjustment then is the timing index requirement of institute's TDM operation transmission.
Step 104: reduce dithering cache.
As shown in Figure 5, reduce dithering cache and comprise two sub-steps:
With consistent among the step 103b, impact for fear of quality institute's transport service, at first new dithering cache degree of depth J0 is set in this substep according to the Jk that monitors, and, the method of the speed of employing quickening sense data slowly moves to the write pointer of dithering cache the center of new dithering cache degree of depth J0, with identical among the step 103b, the operation of accelerating sense data speed is realized by destination control, sense data rate variations rate is answered monitored and real-time adjustment, and the foundation of adjustment then is the timing index requirement of institute's TDM operation transmission.
Wherein, new J0 obtains by relational expression: Jk=J0 * 70%, and certainly, this proportionate relationship also can be selected other numerical value, as long as satisfy Jk＜J0.Wherein Jk is exactly the mean value that first three time period T monitors the write pointer moving range that obtains.
According to new dithering cache degree of depth J0, shake is set goes up Lower Threshold J1 and J2.These parameters still require to satisfy:
J2＜Jk＜J1＜J0
J2＝J0×20％
J1＝J0×80％
Wherein, except first relational expression, other proportionate relationship all can freely be adjusted, clash only otherwise with first relational expression and to get final product, in the formula 20% and 80% is a kind of selective value in the present embodiment, can change it according to actual conditions, for example select 30%, 90% also can.
In order to make the dithering cache regulation means of the circuit simulation system among the present invention, can change and the self adaptation adjustment along with the PDV of network, can further include step after the step 104:
Continue repeatedly execution in step 102 and execution in step 103 or 104 as required.
The above is preferred embodiment of the present invention only, is not to be used for limiting protection scope of the present invention.Those skilled in that art should be able to associate; proportionate relationship for other is set between the jitter range of Lower Threshold and write pointer in the dithering cache degree of depth, the shake; different write pointer translational speed and mode are set; adjust the monitoring time section of different length, all should belong to protection scope of the present invention.
Claims (9)
1. the dithering cache regulation means of a circuit simulation system is characterized in that, predetermined amount of time and shake Upper threshold J1 and shake Lower Threshold J2 are set, and this method may further comprise the steps:
Dithering cache in A, monitoring one predetermined amount of time, if Jk is greater than described shake Upper threshold J1 in the network delay that monitors shake, execution in step B then, if described delay jitter Jk is less than described shake Lower Threshold J2, execution in step C then, if described delay jitter Jk then returns steps A and continues next predetermined amount of time of monitoring between described shake Upper threshold J1 and shake Lower Threshold J2;
B, increase dithering cache degree of depth J0, and adjust described shake Upper threshold J1 and shake Lower Threshold J2, make described delay jitter Jk between described shake Upper threshold J1 and shake Lower Threshold J2;
C, reduce dithering cache degree of depth J0, and adjust described shake Upper threshold J1 and shake Lower Threshold J2, make described delay jitter Jk between described shake Upper threshold J1 and shake Lower Threshold J2;
Wherein, J2＜J1＜J0.
2. the dithering cache regulation means of circuit simulation system according to claim 1 is characterized in that,
Increase among step B or the C or reduce after new dithering cache degree of depth J0 satisfy following the relation with described delay jitter Jk: described delay jitter Jk equals 70% of new dithering cache degree of depth J0;
And the value of Lower Threshold satisfies in the adjusted shake: shake Upper threshold J1 and shake Lower Threshold J2 are respectively 80% and 20% of new dithering cache degree of depth J0.
3. the dithering cache regulation means of circuit simulation system according to claim 1 is characterized in that, monitoring described in the steps A is: monitor an above predetermined amount of time;
If in each predetermined amount of time, delay jitter Jk is greater than shake Upper threshold J1, then execution in step B; If in each predetermined amount of time, delay jitter Jk is less than shake Lower Threshold J2, then execution in step C; Otherwise continuing execution in step A monitors.
4. the dithering cache regulation means of circuit simulation system according to claim 1, it is characterized in that, also further comprise initialization step before the described steps A: after professional the connection, the network delay shake of a time period of monitoring is provided with initial dithering cache degree of depth J0 according to this delay jitter that monitors then.
5. the dithering cache regulation means of circuit simulation system according to claim 1 is characterized in that, described step B also comprises:
Slow down the speed of sense data, the write pointer of dithering cache is moved to the center of the new dithering cache degree of depth J0 after the increase, wherein sense data rate variations rate requires decision by the TDM service timing index that is transmitted.
6. the dithering cache regulation means of circuit simulation system according to claim 5, it is characterized in that, the value of described new dithering cache degree of depth J0 and described delay jitter Jk satisfy following relation: described delay jitter Jk equals 70% of new dithering cache degree of depth J0, and adjusted shake Upper threshold J1 is respectively 80% and 20% of new dithering cache degree of depth J0 with shake Lower Threshold J2.
7. the dithering cache regulation means of circuit simulation system according to claim 1 is characterized in that, described step C is specially:
The new dithering cache degree of depth J0 that setting reduces, and the speed of quickening sense data, the write pointer of dithering cache is moved to the center of described new dithering cache degree of depth J0, and wherein sense data rate variations rate requires decision by the TDM service timing index that is transmitted;
New shake Upper threshold J1 and shake Lower Threshold J2 are set, make new being provided with satisfy J2＜Jk＜J1＜J0.
8. the dithering cache regulation means of circuit simulation system according to claim 7, it is characterized in that, the value of described new dithering cache degree of depth J0 and described delay jitter Jk satisfy following relation: described delay jitter Jk equals 70% of new dithering cache degree of depth J0, and adjusted shake Upper threshold J1 is respectively 80% and 20% of new dithering cache degree of depth J0 with shake Lower Threshold J2.
9. the dithering cache regulation means of circuit simulation system according to claim 1 is characterized in that, is the cycle with described predetermined amount of time, repeated execution of steps A to C.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102158402A (en) * | 2011-03-16 | 2011-08-17 | 华为技术有限公司 | Method and device for cache cells of xbar |
| CN102571561A (en) * | 2011-12-16 | 2012-07-11 | 瑞斯康达科技发展股份有限公司 | PWE3 device and method for reading and writing data in jitter buffer of device |
| CN103870248A (en) * | 2014-03-06 | 2014-06-18 | 北京神舟航天软件科技有限公司 | Dynamic self-adapting technique for simulating buffer zone of instruction set |
| US10389645B2 (en) | 2015-04-30 | 2019-08-20 | Huawei Technologies Co., Ltd. | Communications network delay variation smoothing method, apparatus, and system |
| CN110875860A (en) * | 2020-01-20 | 2020-03-10 | 翱捷科技(上海)有限公司 | Method and device for processing network jitter |
| WO2024021777A1 (en) * | 2022-07-28 | 2024-02-01 | 腾讯科技（深圳）有限公司 | Data transmission method, related apparatus, device and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7423983B1 (en) * | 1999-09-20 | 2008-09-09 | Broadcom Corporation | Voice and data exchange over a packet based network |
| US7006511B2 (en) * | 2001-07-17 | 2006-02-28 | Avaya Technology Corp. | Dynamic jitter buffering for voice-over-IP and other packet-based communication systems |
| CN100394810C (en) * | 2003-11-14 | 2008-06-11 | 中兴通讯股份有限公司 | Grouped dispatching method of wireless communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158402A (en) * | 2011-03-16 | 2011-08-17 | 华为技术有限公司 | Method and device for cache cells of xbar |
| CN102158402B (en) * | 2011-03-16 | 2013-10-02 | 华为技术有限公司 | Method and device for cache cells of xbar |
| US8594111B2 (en) | 2011-03-16 | 2013-11-26 | Huawei Technologies Co., Ltd. | Method and device for buffering cell by crossbar switching matrix |
| CN102571561A (en) * | 2011-12-16 | 2012-07-11 | 瑞斯康达科技发展股份有限公司 | PWE3 device and method for reading and writing data in jitter buffer of device |
| CN102571561B (en) * | 2011-12-16 | 2014-08-06 | 瑞斯康达科技发展股份有限公司 | PWE3 device and method for reading and writing data in jitter buffer of device |
| CN103870248A (en) * | 2014-03-06 | 2014-06-18 | 北京神舟航天软件科技有限公司 | Dynamic self-adapting technique for simulating buffer zone of instruction set |
| US10389645B2 (en) | 2015-04-30 | 2019-08-20 | Huawei Technologies Co., Ltd. | Communications network delay variation smoothing method, apparatus, and system |
| CN110875860A (en) * | 2020-01-20 | 2020-03-10 | 翱捷科技(上海)有限公司 | Method and device for processing network jitter |
| WO2024021777A1 (en) * | 2022-07-28 | 2024-02-01 | 腾讯科技（深圳）有限公司 | Data transmission method, related apparatus, device and storage medium |
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