CN101110419B - Integrated circuit structure with metallic programmable sheet metal used for generating identification data and manufacturing method thereof - Google Patents
Integrated circuit structure with metallic programmable sheet metal used for generating identification data and manufacturing method thereof Download PDFInfo
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- CN101110419B CN101110419B CN2006101055952A CN200610105595A CN101110419B CN 101110419 B CN101110419 B CN 101110419B CN 2006101055952 A CN2006101055952 A CN 2006101055952A CN 200610105595 A CN200610105595 A CN 200610105595A CN 101110419 B CN101110419 B CN 101110419B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 107
- 239000002184 metal Substances 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims description 11
- 150000002739 metals Chemical class 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 240000000233 Melia azedarach Species 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
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Abstract
The present invention relates to an integrated circuit (IC) structure, which comprises a structure layer (W) with a source structure (S), a first and a second programmable metal layer (M1 and M2). Wherein, the metal layer is utilized for wiring of the structure (S) and provides an indicator composed of an identifying bit (ID1). The first metal layer is arranged as a first bit (a) to confirm the identifying bit (ID1) and the second metal layer is arranged as a second bit (b) to confirm the identifying bit (ID1) relying on metal programming. The circuit structure has the advantages that an exclusive-OR circuit is provided with an input terminal to apply the first and the second bit (a and b) and an output terminal to confirm or provide a circuit bit (o) of the identifying bit (ID1).
Description
Technical field
The present invention relates to a kind of integrated circuit structure, the invention still further relates to the method for making this integrated circuit structure with a plurality of metal-programmable metal levels that are used to produce recognition data.
Background technology
The manufacturing of integrated circuit roughly is reduced to two steps basically.The first step is to produce the active member of electronics on wafer surface region, as transistor, diode or resistance.Carry out the wiring of member then, for example form logic gates or register as standard component, and the tandem circuit that forms simulation.The geometry of member and the line that is used to connect up are formed on wafer surface by means of the mask through photochemical treatment.
In so-called metal level, connect up by means of aluminum steel.These aluminum steels couple together standard component and analog circuit component, become the complication system that is used for data and signal processing.Form SOC (system on a chip) (SoC:System on a Chip) with method by this way.
Make in the technology of integrated circuit in the modern times, four or more metal level are spaced from each other ground by additional insulating barrier and successively are applied on the wafer.Connection between each layer forms by so-called intermediary contact.Used mask correspondingly is called " metal mask " or " intermediary's mask " when forming wiring.
The control of a SoC is undertaken by a control interface (Control interface).Interface for example can be an I2C interface, can realize control by reading state information with it.Special state information is a chip id or information indication, and it is used for unique identification of corresponding IC type with the form of the word that is made of a plurality of bits.Chip id is the value of a fixed program, and it can not change afterwards again.Fixed program so realizes: the logic input terminal of a standard component is directly connected to the supply power voltage V corresponding to logical value 1 and 0
DDOr U
SSOn.Thereby this logic input signal with the logical communication link of other signal or irrelevant with the state of register, and directly depend on metal level in and supply power voltage V
DDOr U
SSThe line of the corresponding utmost point.This line is directly determined by " metal mask " and " intermediary's mask ".Therefore the change of the previous value of order can only realize by changing a plurality of masks or metal level.This processing mode is known as " metal-programmable ".
The shortcoming of this processing mode is that the cost of a mask set increases along with reducing of electronic component physical dimension.So owing to the reason of cost can not be made all masks again for little circuit change.The major part of mask is essential when making transistor, diode and resistance.If just metal mask and intermediary's mask are changed, can only relate to one " metal redesign ".At this moment can change line mutual between member, become possibility thereby make little circuit change.
People also wish correspondingly adaptive chip id when " metal redesign " just, so that can discern it reliably when comparing with the former integrated circuit structure that minor variations only takes place.But may be to need to change an additional metal mask owing to changing chip id.
Summary of the invention
The objective of the invention is to, improve the general integrated circuit structure with at least one first and one second metal-programmable metal level, these metal levels are used for the wiring of member and produce a recognition data that is made of at least one identification bit.Especially manufacturing cost can reduce by the simplification of manufacture method.
Above-mentioned task by integrated circuit structure with following characteristics and the method that is used to make this integrated circuit finish.
According to the present invention, a kind of integrated circuit structure is provided, has a structure sheaf with active member, with a plurality of metallic programmable sheet metals, be used for the wiring of member and be used to provide an identification indication that constitutes by at least one identification bit, wherein each metal level is constructed to provide a bit value that is used for by the definite identification of metal programming bit, wherein, the mutual cascade of a plurality of XOR circuit connects, each XOR circuit has a plurality of inputs and an output, wherein introduce identification bit value on each input of first XOR circuit respectively from a metal level, and the output of last XOR circuit is directed to an input of back one XOR circuit, introduce the identification bit value from other metal level on other input of back one XOR circuit respectively, the input of last XOR circuit is as a circuit bit value that is used for determining or providing the identification bit.
In addition, the present invention also provides a kind of method that is used to make integrated circuit structure, have following steps: provide a structure sheaf with active member, and form a plurality of metallic programmable sheet metals, be used for the wiring of member and be used to provide an identification indication that constitutes by at least one identification bit, wherein each metal level is constructed to provide a bit value that is used for by the definite identification of metal programming bit, wherein, the mutual cascade of a plurality of XOR circuit connects, each XOR circuit has a plurality of inputs and an output, wherein introduce identification bit value on each input of first XOR circuit respectively from a metal level, and the output of last XOR circuit is directed to an input of back one XOR circuit, introduce the identification bit value from other metal level on other input of back one XOR circuit respectively, the input of last XOR circuit is as a circuit bit value that is used for determining or providing the identification bit.
What have advantage especially is that the number of metal level is Duoed one than the number of XOR circuit.
What have advantage especially is a kind of like this circuit structure, and wherein recognition data comprises a plurality of identification bits, and each metal level is constructed to and can discerns than the peculiar programming of metal completely possibility each.
What have advantage especially is to use for the interface code of the SOC (system on a chip) circuit structure as the identification bit.
What have advantage especially is a kind of like this circuit structure, wherein metal level be constructed to by with two voltage poles in a voltage pole link to each other to fetch bit value be provided.
What have advantage especially is a kind of like this circuit structure, and wherein XOR circuit forms in structure sheaf.
What have advantage especially is a kind of like this circuit structure, and wherein XOR circuit forms in an interface of integrated circuit structure.
The application of the combination of above-mentioned metal programming and XOR circuit can expand to all spectra that uses the metal-programmable value.
Particularly the sort circuit structure can be used to provide a chip identification, the initial value of a random generator algorithm, and key value in the encryption system or Configuration Values are to activate or to forbid the functional unit of integrated circuit.For example can and be similar to and realize conversion between the low-cost version that bundlees option at Advanced Edition.
Description of drawings
Describe embodiments of the invention in detail by accompanying drawing below.In the accompanying drawing:
Fig. 1 is the schematic cross sectional view according to an integrated circuit structure of first kind of execution mode,
Fig. 2 is the schematic cross sectional view according to an integrated circuit structure of another kind of alternate embodiments,
Fig. 3 is the element of an XOR circuit,
Fig. 4 is first kind of configuration of a plurality of XOR circuit of an integrated circuit structure with 5 metal levels, and
Fig. 5 is second kind of XOR circuit according to another kind of alternate embodiments.
Embodiment
Fig. 1 schematically shows the profile of an integrated circuit structure (IC), wherein only shows to understanding the required element of described metal programming.Also can correspondingly be transformed to the layer and the alternate embodiments of other arrangement mode with other quantity.
In the surf zone of basal layer or wafer W, form construction unit S with method in known manner.Construction unit mainly is active member, as transistor, gate circuit system and like.Above the wafer W surface or above arranging other the layer.These other layer is insulating barrier IS and so-called metal level M
1, M
2Metal level M
1, M
2Separate by an insulating barrier IS respectively each other or with respect to wafer W, to avoid short circuit.The metal level M of sort circuit structure I C
1, M
2Be used for active member each other or with being connected of interface I, this interface has been realized the outside contact of the member S of integrated circuit structure IC.Correspondingly, metal level M
1, M
2Be constructed to the what is called " metal mask " of " intermediary's mask " under having, and make so-called metal programming become possibility.
Formed the contact of active member by interface I, be used for control signal being transferred to member S, perhaps be used for the signal of active member S is transferred to external device (ED) by external device (ED).In order to simplify diagrammatic sketch, required for this reason contact does not illustrate with being connected in the drawings.This external tapping I also is used to present at least one voltage U
SS, U
DDAs supply power voltage, wherein connect VI accordingly and pass each layer W, M from the contact of interface I
1, M
2, IS.
The contact to interface I that illustrates in the drawings in addition also is used for one or best a plurality of identification bit ID 1, and the form of ID2 provides an identification indication.Thereby the identification indication constitutes an interface code ID, can externally install a side by means of it and identify this integrated circuit structure IC.Preferably can discern uniquely about the identification of function and technical parameter.
Each discerns bit ID 1, and ID2 determines and can pass through only at single metal layer M by unique mode and method
1, M
2In carry out corresponding metal and programme and realize.Each discerns bit ID 1 in addition, and ID2 determines and can be preferably in each metal level M by unique mode and method
1, M
2The middle realization.For the metal programming that active member S is conducted interviews, this should carry out so-called " metal redesign ".
In order to realize this point, from each metal level M
1, M
2Draw being connected of a VI and logic XOR circuit XO, wherein under the situation of a plurality of metal levels, in an XOR circuit territory XOF, a plurality of such XOR circuit are set in case of necessity.In the scope of metal programming, corresponding connection VI is at affiliated metal level M
1, M
2In be applied in desirable magnitude of voltage, wherein this preferably by one be connected to one with supply power voltage U
SSOr U
DDThe Metal Contact of connection VI connect V and finish.In a simple embodiment, these two supply power voltage U
SS, U
DDRepresent logical value 1 or 0.In the embodiment shown, from first metal M
1To the corresponding connection VI of XOR gate XO and to the first supply power voltage U
SSContact connect V and be connected second metal M
2Correspondingly with another supply power voltage U
DDBe connected.These two corresponding connects two inputs that VI guide to XOR circuit XO, and correspondingly first bit value a or second bit value b from the first or second metal level M
1, M
2Be sent to this two inputs, as shown in Figure 1.XOR circuit XO provides a circuit bit value o, and it is sent to first contact by corresponding connection VI, is used to provide first identification bit ID 1.In the corresponding way and method, can carry out corresponding metal programming and another identification bit ID 2 is provided.
Fig. 2 illustrates another alternate embodiments, and wherein XOR circuit territory XOF is formed among the wafer layer W by means of active member S, but forms this XOR circuit territory XOF in interface I.Alternatively, this XOR circuit territory also can for example form and be connected by corresponding contact on the interface I as external device (ED).
Execution mode shown in Figure 2 in addition has 3 metallic programmable sheet metal M
1, M
2, M
3In this case, for each is discerned bit ID 1, ID2 carries out unique programming, has formed more complicated connection and XOR circuit XO, XO
*, as illustrating by means of the circuit diagram among Fig. 4 and Fig. 5.
Have one illustrated dotted ellipse frame symbolically among the metal level M1-M5 and gone out metal programming in the metal level M1-M5 that is marked.XOR circuit or corresponding XOR gate are fixedly attached to the first supply power voltage U corresponding to logical one on this position
DDOn, perhaps be connected to the second supply power voltage U corresponding to logical zero
SSOn.
According to exemplary circuit configuration shown in Figure 4, a plurality of XOR circuit XO cascade of connecting mutually connects, and wherein first XOR circuit XO inserts the first or second metal level M1, the bit value a of M2, and b is as input value.The XOR gate XO of back inserts the output valve of last XOR circuit XO respectively, i.e. a metal level M of its circuit bit value o and back
3, M
4Or M
5Another bit value a as input value.The output valve of last XOR circuit XO is as circuit bit value o, simultaneously also as the identification bit ID 1 or the ID2 that provide by interface I.
Fig. 5 illustrates one and has XOR circuit XO
*Circuit structure, XOR circuit XO
*Have the input more than 2, it has 3 inputs respectively in the embodiment shown.At first XOR circuit XO
*First three metal level M1 of last access, M2, the bit value a of M3, b, c.XOR circuit XO in the back
*The previous XOR circuit XO of last access
*Output valve as its circuit bit value o, and other metal level M4, the bit value b of M5, c.Last XOR circuit XO of Lian Jieing like this
*Output also be to be used to provide circuit bit value o, it provides as identification bit ID 1 or ID2 by interface I.
By being connected in parallel of this XOR circuit chain, corresponding identification bit ID 1 is provided, ID2 is used to provide an identification bit sequence, as interface code ID.Particularly also can be dissimilar XOR circuit XO here according to Figure 4 and 5 or other execution mode, XO
*Combination.
Like this, the generation of interface code ID by means of as the programmability of the interface code ID of chip id at any one metal level M1, M2, ... go up so and realize: at each existing metal level M1 that should consider, M2, ... in each bit of carrying out chip id carry out so-called metal programming, all these metals programmings of each bit are carried out the logic XOR by a logical circuit in addition.
Preferred circuit is at each existing metal level M1 of integrated circuit (IC), M2 ... in the metal programming is provided.
The value of all metal programmings is carried out the logical difference exclusive disjunction.This computing has following characteristic: by changing any one programming, operation result can become 1 or become 0 by 1 by 0.When the new metal mask pattern of design, the chip id of interface code form thereby can realize as shown in Figure 1 by changing any " metal mask " respectively.
The logical value of following the first metal layer M1 " metal programming " is also referred to as the link initial value.
This characteristic can be implemented in the change that each layer gone up ID, and this is based on the XOR function, and this also can be by being used for two metal level M1, and the example truth table of M2 is found out:
The XOR gate truth table
The input input and output
a b o
0 0 0
0 1 1
1 0 1
1 1 0
If two input values, i.e. the first and second metal level M1, the bit value a of M2, b is changed, and then the output valve as circuit bit value o remains unchanged.Otherwise circuit bit value o changes.Preceding two row of truth table illustrate: when first bit value a was zero, second bit value b of input was constant, and o appears at output as the circuit bit value, thereby has realized caching function.On the contrary, if first bit value a be the inverse value of 1, the second bit value as circuit bit value o, this can find out by the 3rd and the 4th row from truth table, thereby realize inverter function.
Carry out the metal programming with logical value 1 after, the function of any one XOR gate can change an inverter into.Therefore can on each position of XOR chain, make initial value " upset ".Same change by a metal programming from 1 to 0, the XOR gate with inverter function can change caching function into.
Each bit of chip id or interface code word can for example pass through to change arbitrary metal level M1 by means of the circuit among Fig. 2, M2......, and each metal among the M5 is programmed and is realized.Owing to have self a chain for each bit, be enough to show, all satisfy separately for the conclusion of a chain.Variable each bit that means of bit can be by the variation of single metal programming by 1 to 0 or by 0 to 1 change.
It is because change inverter by the function that a metal programming is changed to 1, one XOR circuit of logical value or an XOR gate into by buffer that the XOR circuit chain has this specific character.So increased an inverter in the chain altogether, output valve o becomes 1 or become 0 by 1 by 0.Under other situation, be set to 0, one XOR gate of logical value by a metal programming and change buffer into by inverter.The number of inverter has reduced 1 in chain, thereby output valve becomes 1 or become 0 by 1 by 0.If initial value changes by the metal programming, output valve correspondingly changes.Output valve is identical with initial value still opposite, depends on other metal programming.
By a metal programming is changed to 1, can change output valve o; Be set to 0 by a metal programming, can change output valve equally; And also can change output valve o by changing initial value.Thereby output valve o changes by changing any metal programming.
This metal programming and one or more XOR circuit XOR, XOR
*Combination a plurality of advantages are provided and have used may.
Can be in the application of sort circuit with a chip identification for being worth arbitrarily.This can realize by the metal programming that changes in any metal mask chips identification.This has been avoided producing only in order to change the expensive expense that mask increased that chip identification just needs.
Claims (8)
1. an integrated circuit structure (IC) has
-one structure sheaf (W) with active member (S) and
-a plurality of metallic programmable sheet metals are used for the wiring of member (S) and are used to provide an identification indication that is made of at least one identification bit, and wherein each metal level is constructed to provide a bit value that is used for by the definite identification of metal programming bit,
It is characterized in that, a plurality of XOR circuit (XOR) cascade mutually connect, each XOR circuit has a plurality of inputs and an output, wherein introduce identification bit value on each input of first XOR circuit respectively from a metal level, and the output of last XOR circuit is directed to an input of back one XOR circuit, introduce the identification bit value from other metal level on other input of back one XOR circuit respectively, the input of last XOR circuit is as a circuit bit value (o) that is used for determining or providing the identification bit.
2. circuit structure as claimed in claim 1, the number of metal level is Duoed one than the number of XOR circuit (XOR).
3. circuit structure as claimed in claim 1, wherein the identification indication comprises that a plurality of identification bits, each metal level are constructed to discern bit to each the possibility of metal programming is completely all arranged.
4. circuit structure as claimed in claim 3 has the identification bit of conduct to the interface code (ID) of SOC (system on a chip) (SoC).
5. circuit structure as claimed in claim 1, wherein metal level (M1, M2......) be constructed to by with two voltage poles in a voltage pole (U
DD, U
SS) be connected and provide bit value (a, b, c).
6. circuit structure as claimed in claim 1, wherein XOR circuit forms in structure sheaf (W).
7. as each described circuit structure in the claim 1 to 6, wherein XOR circuit forms in an interface (I) of integrated circuit structure (IC).
8. be used to make the method for integrated circuit structure (IC), have following steps:
-structure sheaf (W) with active member (S) is provided, and
-form a plurality of metallic programmable sheet metals, be used for the wiring of member (S) and be used to provide an identification indication that constitutes by at least one identification bit, wherein each metal level is constructed to provide a bit value that is used for by the definite identification of metal programming bit
It is characterized in that, a plurality of XOR circuit (XOR) cascade mutually connect, each XOR circuit has a plurality of inputs and an output, wherein introduce identification bit value on each input of first XOR circuit respectively from a metal level, and the output of last XOR circuit is directed to an input of back one XOR circuit, introduce the identification bit value from other metal level on other input of back one XOR circuit respectively, the input of last XOR circuit is as a circuit bit value (o) that is used for determining or providing the identification bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101055952A CN101110419B (en) | 2006-07-19 | 2006-07-19 | Integrated circuit structure with metallic programmable sheet metal used for generating identification data and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101055952A CN101110419B (en) | 2006-07-19 | 2006-07-19 | Integrated circuit structure with metallic programmable sheet metal used for generating identification data and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101110419A CN101110419A (en) | 2008-01-23 |
| CN101110419B true CN101110419B (en) | 2010-12-01 |
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|---|---|---|---|
| CN2006101055952A Expired - Fee Related CN101110419B (en) | 2006-07-19 | 2006-07-19 | Integrated circuit structure with metallic programmable sheet metal used for generating identification data and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI584144B (en) * | 2014-04-14 | 2017-05-21 | 艾銳勢企業有限責任公司 | Real time key collection in device provisioning |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140197463A1 (en) * | 2013-01-15 | 2014-07-17 | Altera Corporation | Metal-programmable integrated circuits |
| CN105590866B (en) * | 2014-10-20 | 2019-01-15 | 华邦电子股份有限公司 | Determine the method and multi-wafer modular device of individual crystalline grains identifier |
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|---|---|---|---|---|
| US5537557A (en) * | 1993-10-01 | 1996-07-16 | Nokia Mobile Phones Ltd. | Interface between unsynchronised devices |
| EP0929040A2 (en) * | 1997-12-25 | 1999-07-14 | Nippon Telegraph and Telephone Corporation | Microprocessor with data randomizing |
| US6617621B1 (en) * | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
| CN1776906A (en) * | 2005-12-08 | 2006-05-24 | 北京中星微电子有限公司 | Configuration system of chip identifying code and con figuration method |
-
2006
- 2006-07-19 CN CN2006101055952A patent/CN101110419B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537557A (en) * | 1993-10-01 | 1996-07-16 | Nokia Mobile Phones Ltd. | Interface between unsynchronised devices |
| EP0929040A2 (en) * | 1997-12-25 | 1999-07-14 | Nippon Telegraph and Telephone Corporation | Microprocessor with data randomizing |
| US6617621B1 (en) * | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
| CN1776906A (en) * | 2005-12-08 | 2006-05-24 | 北京中星微电子有限公司 | Configuration system of chip identifying code and con figuration method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI584144B (en) * | 2014-04-14 | 2017-05-21 | 艾銳勢企業有限責任公司 | Real time key collection in device provisioning |
| US9912771B2 (en) | 2014-04-14 | 2018-03-06 | Arris Enterprises Llc | Real time key collection in device provisioning |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101110419A (en) | 2008-01-23 |
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