CN101110354A - Suspending variable capacitor manufacturing method compatible with CMOS technique - Google Patents
Suspending variable capacitor manufacturing method compatible with CMOS technique Download PDFInfo
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- CN101110354A CN101110354A CNA2007100442933A CN200710044293A CN101110354A CN 101110354 A CN101110354 A CN 101110354A CN A2007100442933 A CNA2007100442933 A CN A2007100442933A CN 200710044293 A CN200710044293 A CN 200710044293A CN 101110354 A CN101110354 A CN 101110354A
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Abstract
The invention relates to a suspension type variable capacitor manufacturing method that is compatible with CMOS technique, which is characterized in that: a device structure is formed with galvanization technique, the device is eroded in isotropy via XeF2 gas, remove partial silicon material on the underlay to release variable capacitor structure and reduce the underlay loss. The suspended capacitor structure is supported by a silicon oxide layer at two sides. Therefore, the invention, which realizes a variable capacitor with large variation scope, high Q value and low voltage on ordinary silicon dice with a low temperature technique of not exceeding 120 DEG C., has the advantages of simple technical procedure, high yield rate and compatible technique with CMOS technique for the whole device.
Description
Technical field
What the present invention relates to is a kind of manufacture method that provides with the suspending variable capacitor of CMOS process compatible, described device adopts and is no more than 120 ℃ low temperature process, can with the compatible mutually single silicon-chip of realizing radio circuit of CMOS (complementary metal oxide semiconductors (CMOS)) technology on integrated.Belong to radio-frequency micro-machinery device and circuit engineering application.
Background technology
Along with the application of radio-frequency technique more and more widely, for the requirement of high-performance variable capacitance, make that the research of this respect is more and more.Silicon micromachining technique has the unexistent characteristics of some surface C MOS technologies, and it has expanded the ability of designs.Expand to three-dimension device from two traditional dimensional devices.Along with field of wireless communication, to high sensitivity with the requirement of the low-power consumption of device, need some high performance radio-frequency devices especially, as mobile phone, satellite communication, radio-frequency (RF) identification and various wireless network.
Variable capacitance is widely used a kind of passive device in the communicating circuit, or is called varactor.It is widely used in low noise amplifier, harmonic oscillator and the FREQUENCY CONTROL.Traditional variable capacitance utilizes pn knot or schottky-barrier (Xiao Te potential barrier) structure to be manufactured on silicon or the arsenic potassium substrate, along with the advantage of MEMS is obvious gradually, more and more researchers is engaged in the research of micro-mechanical variable capacitor, these micro-mechanical variable capacitors change their capacitance by the trim physical size, the medium of electric capacity is generally air, can strike out main dielectric loss.In the evolution of MEMS variable capacitance, flat capacitor is more common, and this capacitance structure generally has the metal top crown of a suspension to drive by electrostatic force, changes the capacitance between metal polar plate up and down.Because the variable capacitance of MEMS type realizes that by the metal material of low-resistance its Q value is than the variable capacitance height of traditional structure pn knot.Young in 1996 and Boser have delivered first variable capacitance [D.J.Yong that pass through change electric capacity spacing that utilizes surface micromechanical process to make, V.Malba, J.J.Ou, A.F.Bemhardt andB.E.Boser, " A micromachined variable capacitor for monolithic low-noiseVCOs; " Tech.Digest Solid State Sensor and Actuator Workshop, 1988:128-131.].But capacity plate antenna exists the variable capacitance scope to be no more than 50% one theory, and driving voltage is bigger, and along with capacitance variation, the also corresponding change of the polar plate spacing of electric capacity is affected the bearing capacity of radio frequency (RF) power.
In order to solve the deficiency that exists in the flat variable capacitor structure, people such as Larson reported the variable area variable capacitance [L.E.Larson that utilizes the surface micromachined technology to realize for the first time in 1991, R.H.Hackett, M.A.Melendes and R.F.Lohr, " Micromachined microwave actuator (MIMAC) technology-a new tuning approach for microwave integrated circuits " IEEE Microwave and Millimeter-Wave Monolithic circuits Symp, 1991:27-30.], this device is that broach drives, because the edge capacitance between broach is very little, so the voltage that applies rises to 80-200V.Electric capacity changes to 100fF from 35fF, and broach overlapping spacing changes to 375 microns from 150 microns.Broach drives the restriction that the variable area variable capacitance that detects can not be subjected to any variable ratio in theory, and the linearity is better, and the radio-frequency power ability to bear is not subjected to the influence of capacitance variations.People such as J.J.Yao have reported that in 1998 a kind of floated broach drives the variable area variable capacitance [J.J.Yao that detects, S.Park andJ.DeNatale, " High tuning-ratio MEMS-based tunable capacitors for RFcommunications applications " Solid State Sensor and Actuator Workshop, 1998:124-127.], it utilizes deep erosion monocrystalline silicon to complete on soi wafer, in order to reduce the Q value that series resistance improves variable capacitance, reduce series resistance at broach surface coverage skim metal again at last.Compare with above-mentioned gap variable capacitance, the electric capacity adjustable extent of this structure, promptly variable ratio does not have theoretic restriction, the variable ratio of the device of having reported is 3.18: 1, just capacitance variation 218%, the highest even can reach 8.4: 1.
But present broach variable capacitance all is to adopt silicon materials as device architecture, finishes by deep etching technique, and series resistance is bigger, and manufacturing cost is also higher.Can enough adopt simple technology and low cost, can realize that high performance variable capacitance has become the technological difficulties that those skilled in the art thirst for solving with cmos compatible processing step again, thereby also be guided out purpose of the present invention.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of suspending variable capacitor of and CMOS process compatible.From reducing cost and reducing the complex process degree and consider that the present invention only adopts two reticle just to realize described device architecture.Processing step is simple and clear, adopts to be no more than 120 ℃ low temperature process, is convenient to post-CMOS and makes on the realization silicon chip integrated.In order to make the structure of suspending variable capacitor, at first on the surface of silicon chip, cover a layer dielectric by deposition or thermal oxidation process, then corrosion defines the dielectric film that needs release, electroplate and form floated capacitance structure, utilize isotropism silicon etchant gas to remove the silicon substrate of device bottom periphery at last, discharge device architecture.
By the suspending variable capacitor structural representation of manufacture method manufacturing provided by the invention shown in Fig. 1 (1).Total is kept to the side, and the edge housing is regional to be supported, and after the silicon of bottom was removed, device was suspended in the feature of silicon chip surface.
In sum, the suspending variable capacitor of a kind of CMOS process compatible provided by the invention, total is by the silica or the silicon nitride medium film support on both sides.
The concrete processing step that rotary suspension variable capacitance provided by the invention is realized is
1, selected material: N type or P type silicon chip; Adopt thermal oxidation, low-pressure chemical vapor deposition (LPCVD) or with the method for plasma enhanced chemical vapor deposition (PECVD) at silicon chip surface formation silica or silicon nitride medium film, as the supporting layer after the release of entire device structure, as its name suggests, suspending variable capacitor provided by the invention is to be suspended on silicon dioxide or the silicon nitride medium film, and thickness is 0.5～3 micron;
2, make the zone of the anisotropic etch that needs and remove this zone silica or silicon nitride layer by lithography, the splash-proofing sputtering metal Seed Layer is that titanium tungsten/copper (is that first sputtered titanium tungsten is followed sputter copper then on silicon chip, titanium/gold, chromium/copper, chromium/gold or titanium tungsten/gold down together),, spin coated photoresist thickness is 1～10 micron, and lithographic definition goes out the variable capacitor structure shape;
3, electroplate the metallic nickel of one deck 0.5-9 micron thickness, then electroplate the gold layer of 0.2～0.5 micron of one deck again.This thin au is used for avoiding nickel oxidized under environment.0.2 the above gold layer of micron thickness is necessary, can realize the coating to nickel; And will increase manufacturing cost than 0.5 micron thick again gold layer, can't further improve capacitive property.Therefore general golden layer thickness is 0.2～0.5 micron, removes Seed Layer at last;
4, utilize XeF
2Gas carries out the isotropic etch (XeF of silicon
2Gas has fabulous corrosion selectivity, promptly only corrode silicon and do not corrode other any materials), the silicon in device bottom periphery zone all is removed, the height that the structure of variable capacitance is suspended in silicon chip substrate is 5～70 microns, and the entire device structure is supported on the both sides of groove by silica medium film that forms in the step 1 or silicon nitride medium film.
This device is that the method for CMOS process compatible is made, and is easy to the integrated and batch process of monolithic system of radio circuit, and firm HI high impact and the vibration that can bear external environment of device architecture.
In sum, the structure and the manufacture method of the suspending variable capacitor of provided by the invention and CMOS process compatible have following four characteristics.
1, entire device adopts the 120 ℃ of low temperature process that are no more than with the CMOS process compatible, can not impact established cmos device.
2, utilization is no more than 120 ℃ of cryogenic electroplating process and forms the variable capacitor structure layers, and at the oxidation resistant gold of surface coverage skim.
3, adopt the dry method isotropic etch that device architecture is suspended in silicon chip surface, only pass through the silica or the silicon nitride medium film support at housing place, edge.Form intermediate capacitance comb structure in the floated capacitance structure, by two ends folded beam support and connection to housing.
4, the manufacture method that is provided among the present invention, technology is simple, and cost is low and rate of finished products is high.
Description of drawings
Fig. 1: suspending variable capacitor structure and schematic cross-section
(1) flying capacitor structural representation
(2) flying capacitor schematic cross-section
Fig. 2: the principle of insulation variable capacitance, make flow process and device
(1) the insulation variable capacitance is made flow process
(2) device that completes
Fig. 3: insulation variable capacitance test result
(1) relation of capacitance variations value and driving voltage
(2) radiofrequency characteristics of Q value and capacitance
Among the figure:
1, drive part; 2, sensitization capacitance part; 3, thin au; 4, nickel metal; 5, metal seed layer; 6, silicon oxide layer or silicon nitride medium thin layer; 7, XeF
2Gas attack removes part; 8, insulative bridge; 9, silicon substrate
Embodiment
The making of the plating suspending variable capacitor of embodiment and CMOS process compatible
Utilize the method for CMOS process compatible to make the plating suspending variable capacitor, whole technological temperature is no more than 120 ℃.A kind of possible making execution mode with the device of actual fabrication shown in Fig. 2 (1) and (2), wherein (1) expression is along AA ' visual angle manufacturing process in (2).The enforcement of this device is not limited only to this technological process.Accompanying drawings is as follows:
1, selected material: 4 inches N types or P type (100) silicon chip, resistivity 3～8 Ω cm, thick 450 ± 10 μ m of silicon chip, angular error＜1% that silicon chip is cut edge; The method that adopts gas ions to strengthen chemical vapour deposition (CVD) (PECVD) forms silicon oxide film at silicon chip surface, the supporting layer after discharging as the entire device structure, and thickness is 1～3 micron; Make the zone of anisotropic etch by lithography, remove the oxide layer in this zone, shown in a among Fig. 2 (1);
2, splash-proofing sputtering metal Seed Layer (titanium tungsten and copper) on silicon chip, the rotation gluing, photoresist thickness is 9～10 microns, makes the variable capacitor structure shape by lithography, shown in b among Fig. 2 (1);
3, plated metal nickel and one deck prevent the structure of the oxidized thin au of nickel as variable capacitance, and the thickness of metallic nickel is 7～9 microns, and thin au thickness is 0.5 micron, removes Seed Layer then, shown in c among Fig. 2 (1);
4, utilize XeF
2Gas carries out the isotropic etch (XeF of silicon
2Gas has fabulous corrosion selectivity, promptly only corrode silicon and do not corrode other any materials), the silicon of electric capacity peripheral region all is removed, the height that is suspended in silicon chip substrate is 30～50 microns, the whole capacitor structure is supported on both sides by the silicon oxide film that forms in the step 1, shown in d among Fig. 2 (1).
Claims (9)
1. manufacture method with the suspending variable capacitor of CMOS process compatible, it is characterized in that the surface coverage one deck dielectric film of elder generation at silicon chip, then corrosion defines the dielectric film in the zone that needs release, electroplates and forms floated capacitance structure, adopts XeF at last
2Gas isotropism dry etching removes the silicon substrate of device bottom periphery, discharges device architecture.
2. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 1, it is characterized in that processing step is:
(a) select two (100) silicon chips of throwing for use, and form the dielectric film of one deck silica or silicon nitride in the surface coverage of silicon chip;
(b) make the zone of isotropic etch and silicon oxide layer or the silicon nitride layer in the removal zone by lithography;
(c) splash-proofing sputtering metal Seed Layer on silicon chip, the spin coated photoresist, photoetching, developing defines the variable capacitance shape, electroplates layer of metal nickel, and then electroplate one deck be used for preventing nickel in air oxidized thin au as the structured metal layer of variable capacitance;
(d) behind the removal metal seed layer, utilize XeF
2Gas carries out isotropic etch, and the silicon that exposes is Removed All, and variable capacitance is suspended on the silicon chip substrate, and entire device is supported on the groove both sides by silica or the silicon nitride medium film that step (a) forms.
3. by the manufacture method of the suspending variable capacitor of claim 1 or 2 described and CMOS process compatibles, it is characterized in that described silicon chip is N type or P type.
4. by the manufacture method of the suspending variable capacitor of claim 1 or 2 described and CMOS process compatibles, it is characterized in that one deck silica that covers on the silicon chip or the thickness of silicon nitride film are 0.5-3 μ m, it is to adopt the method for thermal oxidation, low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition to form at silicon chip surface.
5. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 2, the metal seed layer that it is characterized in that sputter is titanium tungsten/copper, titanium/gold, chromium/copper, chromium/gold or titanium tungsten/gold.
6. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 2, the thickness that it is characterized in that the plated metal nickel dam is 0.5～9 micron, is 0.2～0.5 micron at the golden layer thickness of the electroplating surface of nickel.
7. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 2, the height that the structure that it is characterized in that variable capacitance is suspended in silicon chip substrate is 5～70 microns.
8. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 2, the thickness that it is characterized in that the spin coated photoresist is the 1-10 micron.
9. by the manufacture method of the described suspending variable capacitor with the CMOS process compatible of claim 1, the electric capacity comb structure that it is characterized in that the centre in the structure of floated electric capacity by two ends folded beam support and connection to housing.
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| CNA2007100442933A CN101110354A (en) | 2007-07-27 | 2007-07-27 | Suspending variable capacitor manufacturing method compatible with CMOS technique |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021812A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Method for preparing III-VOI structure |
| WO2022047977A1 (en) * | 2020-09-01 | 2022-03-10 | 瑞声声学科技(深圳)有限公司 | Method for preparing silicon wafer having rough surface, and silicon wafer |
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2007
- 2007-07-27 CN CNA2007100442933A patent/CN101110354A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021812A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Method for preparing III-VOI structure |
| CN103021812B (en) * | 2012-12-20 | 2016-02-17 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of III-V OI structure |
| WO2022047977A1 (en) * | 2020-09-01 | 2022-03-10 | 瑞声声学科技(深圳)有限公司 | Method for preparing silicon wafer having rough surface, and silicon wafer |
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