CN101109775A - Programmable voltage monitoring circuit - Google Patents
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- CN101109775A CN101109775A CNA2007100758086A CN200710075808A CN101109775A CN 101109775 A CN101109775 A CN 101109775A CN A2007100758086 A CNA2007100758086 A CN A2007100758086A CN 200710075808 A CN200710075808 A CN 200710075808A CN 101109775 A CN101109775 A CN 101109775A
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Abstract
The invention discloses a programmable voltage monitoring circuit, which comprises a program control circuit, a monitoring voltage generating circuit and a real-time voltage monitoring circuit. The program control circuit comprises a program state selecting end and a state judging circuit. The program state selecting end is for a user to select one from four program states i.e. input grounding, connecting power supply, suspending and suspended connection, etc. The state judging circuit generates corresponding control signal based on the program state selected by the user, and outputs that to the monitoring voltage generating circuit; the monitoring voltage generating circuit, based on the input control signal, generates a corresponding monitoring voltage and sends the monitoring voltage to the real-time voltage monitoring circuit; the real-time voltage monitoring circuit compares the monitored voltage and the voltage to be monitored and generates the corresponding monitoring results. The invention adds program states without increasing program pins and changing programming way, and enlarges the range of voltage coverable by the monitored circuit.
Description
Technical field
The present invention relates to voltage monitoring, relate in particular to a kind of programmable voltage monitoring circuit.
Background technology
The general at present programmable voltage monitoring circuit of using, its each programming pin connects power supply, ground connection and unsettled three kinds of states; Each pin produces two switch controlling signals, is used for controlling the input resistance of an in-phase amplifier, and this in-phase amplifier has different enlargement factors under the different situation of input resistance, produce different monitoring voltages with this.This programmable voltage monitoring circuit has 3
NPlant different voltage state is set, wherein N has represented the programming number of pins.
In the application of programmable voltage monitoring circuit, to note following main points:
1) require the value of two adjacent monitoring voltages can not be mutually too far away, otherwise can reduce the voltage-programming precision, it be good differing 0.1v with two adjacent monitoring voltages;
2) scope of voltage detecting wants wide, otherwise the range of application of electric voltage observation circuit will be restricted, and voltage commonly used at present has 5v, 3.3v, this several values of 2.5v, 1.8v, one preferably programmable voltage monitoring circuit should be able to cover above-mentioned voltage range;
3) pin of programmed settings will lack, and the programming set-up mode wants simple, so that reduce the loss of PCB area;
4) power consumption of Chan Shenging is little.
According to above some requirement, we can see that above-mentioned programmable voltage monitoring circuit has following shortcoming:
At first, be 0.1v (referring to that two adjacent monitoring voltages differ 0.1v) in the programming precision, adopt under the situation of three programming pins, because three pins can only have 3
N=27 kinds of states, then Bian Cheng variable range has only 2.7v, can not cover the gamut of 1.8v to 5v, in order to enlarge the voltage coverage, certainly will will increase the programming pin, will cause the loss of PCB area like this.
Secondly, this circuit adopts the in-phase amplifier of resistance form, and the resistance of amplifier has formed earthy DC channel when amplifying, and can produce bigger dc power.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of programmable voltage monitoring circuit, this circuit can increase programming state under the prerequisite that does not increase the programming pin, and expansion can cover the scope of voltage.
To achieve these goals, the present invention has adopted following technical scheme:
Programmable voltage monitoring circuit, comprise that programming Control circuit, monitoring voltage produce circuit and the real-time observation circuit of voltage, described programming Control circuit comprises programming state selecting side and status determination circuit, described programming state selecting side be used for for the user select ground connection, connect power supply, unsettled and unsettled one of the four kinds of programming states that link to each other, the programming state that described status determination circuit is selected according to the user produces corresponding control signal and exports monitoring voltage generation circuit to; Described monitoring voltage produces circuit and exports the real-time observation circuit of voltage to according to the monitoring voltage that the described control signal of importing produces correspondence; The real-time observation circuit of described voltage is monitoring voltage and voltage to be monitored relatively, produces corresponding monitoring result.
Described status determination circuit comprises single pin status decision circuitry, unsettled decision circuitry and the unsettled decision circuitry that links to each other; Described single pin status decision circuitry, its input end links to each other with the programming state selecting side, be respectively ground connection in order to produce with the programming state selecting side, corresponding control signal when connecing power supply or unsettled these three kinds of programming states, and export monitoring voltage generation circuit and unsettled decision circuitry to; Described unsettled decision circuitry is monitored the control signal that single pin status decision circuitry produces, and produces corresponding control signal and exports unsettled continuous decision circuitry to when a plurality of vacant state appears in the programming state selecting side determining; The input end of described unsettled continuous decision circuitry links to each other with the programming state selecting side, described unsettled continuous decision circuitry responds the control signal of unsettled decision circuitry input, produces circuit determining to produce control signal and export monitoring voltage to when unsettled continuous state appears in the programming state selecting side.
Described unsettled decision circuitry comprises digital operational circuit, described digital operational circuit is used for the control signal that any two single pin status decision circuitry produce is carried out digital operation, when judging that described two pins are in vacant state simultaneously, the output corresponding control signal is to unsettled continuous decision circuitry.
Described digital operational circuit comprise first rejection gate and first and the door, described unsettled continuous decision circuitry comprises second rejection gate, latch and second and door, described first rejection gate, two input ends are imported the control signal of described single pin status decision circuitry output respectively, and output terminal links to each other with door one input end with second with door with first respectively; Described first with the door another input end be clock signal input terminal, output terminal links to each other with described latch clock signal input terminal; Described second rejection gate, two input ends are imported the signal of programming state selecting side output respectively, output terminal links to each other with described latch input end, described latch output terminal links to each other with another input end of door with described second, and described second produces circuit with door output corresponding to the monitoring voltage that controls signal to of the unsettled state that links to each other.
Described latch is a D flip-flop.
Described unsettled continuous decision circuitry also comprises level forming circuit, described level forming circuit comprises first node that links to each other with described second rejection gate, one input end and the Section Point that links to each other with described another input end of second rejection gate, described first node links to each other with two programming state selecting sides respectively with Section Point, be used for producing the logic opposite levels during state, when unsettled continuous state, produce the logic same level in unsettled not linking to each other.
Described monitoring voltage produces circuit and comprises switched-capacitor integrator, described switched-capacitor integrator comprises sampling capacitance, integrating capacitor, reference source, two-phase do not overlap clock and operational amplifier, described sampling capacitance is used for the control signal of described programming Control circuit output is coupled to operational amplifier one input end, described integrating capacitor is connected across between described operational amplifier input end and the operational amplifier output terminal, another input end of described operational amplifier links to each other with reference source, thereby the control signal control break sampling capacitance value of described programming Control circuit output makes monitoring voltage to change.
Comprise the open loop comparer in the real-time observation circuit of described voltage, described open loop comparer two input ends link to each other with voltage to be monitored with the monitoring voltage of monitoring voltage generation circuit output respectively.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention provides than the more programming state of existing observation circuit by adding unsettled continuous judgement, thereby do not increasing the programming pin and changing under the prerequisite of programming mode, has enlarged the scope that observation circuit can cover voltage.
Further, monitoring voltage generation monitoring voltage produces the way of realization that circuit adopts switching capacity, has avoided amplifying the formation of work feedback fraction in period to the earth potential DC channel, thereby has reduced dc power.
Description of drawings
Fig. 1 is the circuit module synoptic diagram of the embodiment of the invention;
Fig. 2 is four asynchronous clock signal synoptic diagram using in the embodiment of the invention;
Fig. 3 is the gate level circuit synoptic diagram of programming Control circuit in the embodiment of the invention;
Fig. 4 is the gate level circuit synoptic diagram that monitoring voltage produces circuit and real-time observation circuit in the embodiment of the invention;
Fig. 5-A is the switched-capacitor integrator schematic diagram that adopts in the embodiment of the invention;
Fig. 5-B is the equivalent circuit schematic diagram under a kind of state of switched-capacitor integrator in the embodiment of the invention;
Fig. 6 is switched-capacitor integrator is used in the embodiment of the invention the two-phase clock circuit synoptic diagram that do not overlap;
Fig. 7 is switched-capacitor integrator is used in the embodiment of the invention the two-phase clock signal synoptic diagram that do not overlap.
Embodiment
Specific embodiments of the present invention is described in detail below in conjunction with accompanying drawing.
Referring to Fig. 1, the programmable voltage monitoring circuit of the embodiment of the invention is by the programming pin is taked different connected modes: connect power supply, ground connection, unsettled, two pins are unsettled and link to each other and set different monitoring voltage values, this circuit comprises that programming Control circuit, monitoring voltage produce circuit and the real-time observation circuit of voltage.Wherein, the programming Control circuit comprises: single pin status decision circuitry, unsettled decision circuitry, unsettled continuous decision circuitry and three asynchronous clock signal inputs.Monitoring voltage produces circuit and comprises five control signal inputs and an asynchronous clock signal input.At first the course of work of programming Control circuit is specifically described below.
The programmable voltage monitoring circuit of the embodiment of the invention has four asynchronous clock signal Ck0, Ck1, Ck2 and Ck3, and as shown in Figure 2, these four clocks have identical period T 3, and the time of keeping high level simultaneously is also identical, all is T1.The high level arrival time delay T2 of the high level arrival relative Ck0 of time of Ck1, the high level of relative respectively Ck1 of the high level arrival time of Ck2 and Ck3 and the Ck2 time that arrives also postpones T2.Provide clock signal, Ck2 to be used for judging two pins provide clock, Ck3 to be used for providing clock when producing monitoring voltage when whether linking to each other when wherein this two phase clock of CK0 and Ck1 is used for the state of single pin judged.
The gate level circuit of programming Control circuit is referring to Fig. 3, in Fig. 3 and each accompanying drawing subsequently
The switch that expression is made of MOSFET (metal oxide type field effect transistor),
On the control signal of symbolic representation gauge tap closed and disconnected, for example work as
On symbol when being Ph1, represent that then this switch controls its closed and disconnected by Ph1.All switches all are closures when control signal is high level, disconnect for low level the time.The pin status decision circuitry of PIN0 pin and PIN1 pin has been shown among Fig. 3.Because both circuit structures are identical, existing is that example describes its principle of work with PIN0 pin decision circuitry.PIN0 pin pin status decision circuitry comprises switching tube Q11, Q12, Q13, Q14, Q15, Q16, the first trigger T11, the second trigger T12, all adopt D flip-flop in the present embodiment, comprise first and second resistor voltage divider circuits in addition, two resistor voltage divider circuits respectively comprise divider resistance 1R and 9R, the resistance ratio of two divider resistances of expression is 1: 9, wherein two resistance, one end of first resistor voltage divider circuit is intersected in the input end of the first trigger T11, the resistance other end of resistance 1R links to each other with switching tube Q11, and the resistance other end of resistance 9R links to each other with switching tube Q15; Two resistance, one end of second resistor voltage divider circuit is intersected in the input end of the second trigger T12, and the resistance other end of resistance 9R links to each other with switching tube Q12; The resistance other end of resistance 1R links to each other with switching tube Q16.The clock signal of the first trigger T11 and the second trigger T12 is respectively CK0 and CK1, switching tube Q11, Q13 and Q15 subject clock signal CK0 control, Q12, Q14 and Q16 subject clock signal CK1 control.When Ck0 is high level, the switch of being controlled by Ck0 in the single pin status decision circuitry among Fig. 3 is all closed, rest switch all disconnects, be switching tube Q11, Q13 and Q15 closure, switching tube Q12, Q14 and Q16 disconnect, and the while, the output Q by the first trigger T11 of Ck0 control equaled to import D.If this moment, PIN0 connect power supply (VDD), the voltage of D1 and S1 all is VDD (' 1 ') so; If PIN0 ground connection (VSS), the voltage of D1 and S1 all is VSS (' 0 ') so; If PIN0 is unsettled, so for resistance ratio 1R and the 9R shown in first resistor voltage divider circuit in the single pin status decision circuitry among Fig. 3, the voltage that can obtain D1 according to the principle of electric resistance partial pressure is 9*VDD/10, is desirable digital high (' 1 ') after the gate circuit shaping of the voltage of S1 through trigger inside.Ck0 is become by high level after the low level, is all disconnected the voltage that obtains when being locked in Ck0 for high level by the output S1 of the D flip-flop of Ck0 control simultaneously by the switch of Ck0 control.
After Ck1 became high level by low level, the switch of being controlled by Ck1 in the single pin status decision circuitry among Fig. 3 was all closed, and rest switch all disconnects, and promptly switching tube Q11, Q13 and Q15 disconnect, switching tube Q12, Q14 and Q16 closure.Output Q by the second trigger T12 of Ck1 control equals to import D.If this moment, PIN0 connect power supply (VDD), the voltage of D2 and S2 all is VDD (' 1 ') so; If PIN0 ground connection (VSS), the voltage of D2 and S2 all is VSS (' 0 ') so; If PIN0 is unsettled, so for resistance ratio 9R and the 1R shown in second resistor voltage divider circuit in the single pin status decision circuitry among Fig. 3, the voltage that can obtain D1 according to the principle of electric resistance partial pressure is VDD/10, is desirable digital low level (' 0 ') after the gate circuit shaping of the voltage of S2 through trigger inside.Ck1 is become by high level after the low level, is all disconnected the voltage that obtains when being locked in Ck1 for high level by the output S2 of the D flip-flop of Ck1 control simultaneously by the switch of Ck1 control.
Therefore after Ck0 and Ck1 clock became low level, with respect to the different connected mode of PIN0, the non-signal S2B of S1, S2 and S2 can obtain different voltages: if PIN0 connects power supply, S1, S2 and S2B were respectively: ' 1 ', ' 1 ', ' 0 '; If PIN0 ground connection, S1, S2 and S2B are respectively: ' 0 ', ' 0 ', ' 1 '; If PIN0 is unsettled, S1, S2 and S2B are respectively: ' 1 ', ' 0 ', ' 1 '.Can obtain by top result, if S1 and these two signals of S2B are carried out NOT-AND operation, so only when PIN0 is unsettled, with non-F0 as a result just be ' 0 ', connect at PIN0 that F0 is ' 1 ' under the situation of power supply and ground connection, so just can distinguish whether unsettled PIN0 is.
More than explanation is that the pin status of PIN0 is judged, same as described above for the pin status deterministic process of PIN1.Pin status decision circuitry through PIN1 is judged the state of PIN1, produces the non-signal S4B of S3, S4, S4; If PIN1 connects power supply, S3, S4 and S4B are respectively: ' 1 ', ' 1 ', ' 0 '; If PIN1 ground connection, S3, S4 and S4B are respectively: ' 0 ', ' 0 ', ' 1 '; If PIN1 is unsettled, S3, S4 and S4B are respectively: ' 1 ', ' 0 ', ' 1 '.In like manner, S3 and S4B being carried out NOT-AND operation, just is ' 0 ' with non-F1 as a result under the unsettled situation of PIN1 only, connects at PIN1 that F1 is ' 1 ' under the situation of power supply and ground connection.
Unsettled decision circuitry adopts digital operational circuit, comprises the first Sheffer stroke gate G21, the second Sheffer stroke gate G22, the first rejection gate G23, the 3rd Sheffer stroke gate G24 and the first not gate G25, wherein the 3rd Sheffer stroke gate G24 and first not gate G25 formation first and door.By the first Sheffer stroke gate G21 S1 and these two signals of S2B being carried out NOT-AND operation obtains and non-F0 as a result; By the second Sheffer stroke gate G22 signal S3 and S4B being carried out NOT-AND operation obtains and non-F1 as a result; F0 and these two signals of F1 are carried out NOR operation by the first rejection gate G23, and the result that operation obtains is FF01.Only FF01 just is ' 1 ' when the value of F0 and F1 all is ' 0 ', and this expression PIN0 and these two pins of PIN1 are all unsettled, needs further to judge whether they link to each other; If F0 and F1 have one or more non-' 0 ', then FF01 is ' 0 ', this expression PIN0 and PIN1 have at least one not unsettled, judgement in this case need not link to each other, FF01 and clock signal C k2 by first with the door, promptly the 3rd Sheffer stroke gate G25 finishes and operation with the first not gate G25, will be ' 0 ' with the clock signal C k2c01 that produces, can disconnect switches all in the unsettled continuous decision circuitry does not work it, the signal FPC01 that unsettled continuous judgement is produced directly is changed to ' 0 ' simultaneously, the unsettled pin that expression does not link to each other.
Unsettled continuous decision circuitry comprises switching tube Q31, Q32, Q33 and Q34, the second not gate G31, the 3rd not gate G32, the second rejection gate G33, latch T31, the 4th Sheffer stroke gate G34 and the 4th not gate G35, and level forming circuit, wherein the 4th Sheffer stroke gate G34 and the 4th not gate G35 constitute second with door, it is 1: 9: 5 resistance 1R0,9R0 and the 5R0 and first and second nodes that level forming circuit comprises the resistance ratio, first node links to each other with the second not gate G31 input end, and Section Point links to each other with the 3rd not gate G32 input end.The clock signal of latch T31 is Ck2c01, is 1 o'clock at FF01, and Ck2c01 is a clock signal identical with Ck2.When Ck2c01 was high level, the switch of its control was all closed, and promptly switching tube Q31, Q32, Q33 and Q34 are all closed.When PIN0 does not link to each other with PIN1, resistance 1R0 among Fig. 3 in the level forming circuit shown in the unsettled continuous decision circuitry, 9R0, the out1 as a result that the resistance ratio dividing potential drop of 5R0 obtains the second not gate G31 is ' 0 ', and the out2 as a result of the second not gate G32 is ' 1 ', by the second rejection gate G33 out1 and out2 being carried out the out3 as a result that NOR operation obtains is ' 0 ', with out3 is the input signal of latch T31, at this moment the output Qc of latch T3 1 is ' 0 ', by second with the door, promptly the 4th Sheffer stroke gate G34 carries out Qc and operation with FF01 with the 3rd not gate G35, and the operating result FPC01 that obtains also is ' 0 '; When PIN0 links to each other with PIN1, among Fig. 3 in the level forming circuit resistance be the resistance of 9R0 by short circuit, at this moment out1 and out2 are ' 0 ', they are carried out the out3 as a result that NOR operation obtains is ' 1 ', at this moment Qc and FPC01 are ' 1 '.After Ck2c01 became low level by high level, the Qc as a result that obtains when the Ck2c01 high level will be latched device T31 and latch, and judged the result who obtains when then FPC01 also can keep the Ck2c01 high level always.Therefore when two unsettled pins linked to each other, value of unsettled continuous decision circuitry generation meeting generation was ' 1 ' signal FPC01; When having not unsettled or two the unsettled pins of one or more pins not link to each other in two pins, FPC01 be ' 0 ', and expression does not have pin unsettled continuous.
Can be obtained by above analysis, after three intervals equal asynchronous clock Ck0, Ck1, Ck2, the programming Control circuit can produce and latch S1, S2, S3, S4, this several Control signal of FPC01.In the present embodiment, d type flip flop and devices such as Sheffer stroke gate, rejection gate have been adopted, can understand, do not limit and use these devices, as trigger type can be RS, JK flip-flop, Sheffer stroke gate, rejection gate also available with door or door, with or devices such as door, XOR gate replace, only need do corresponding adjustment and get final product the signal of drawing.
Shown in Fig. 4 and 6, monitoring voltage produces the sampling capacitance size of circuit by the by-pass cock capacitance integrator and produces different monitoring voltages, comprising: from the switching capacity noninverting integrator of zero clearing, asynchronous clock signal input, a two-phase do not overlap clock generation circuit, sampling hold circuit and a reference source; Wherein the switching capacity noninverting integrator from zero clearing comprises operational amplifier, sampling capacitance C1, integrating capacitor C2, switching tube Q41, Q42, Q43, Q44, Q46; Sampling capacitance C1 is connected between the inverting input of output of programming Control circuit and operational amplifier, reference source is from operational amplifier in-phase input end input, integrating capacitor C2 be connected across between operational amplifier inverting input and the output terminal after switching tube Q46 is in parallel.Sampling hold circuit comprises capacitor C s1 and Cs2, switching tube Q45, capacitor C s1 is connected between operational amplifier output terminal and the ground, capacitor C s2 one end ground connection, the other end links to each other with the real-time observation circuit input of voltage, links to each other with operational amplifier output terminal through switching tube Q45 simultaneously.
Before the course of work that monitoring voltage is produced circuit is introduced, earlier the principle of work from the switching capacity noninverting integrator of zero clearing is introduced.Shown in Fig. 5-A, Ph1 and Ph2 are the clock signals that two-phase does not overlap among the figure, as shown in Figure 7 from the switching capacity noninverting integrator of zero clearing.They can be simultaneously for high level preventing that electric charge takes place to be lost in transfer process, produce by the clock generation circuit that do not overlap of the two-phase shown in Fig. 6.Is under the low level situation at Ph2 for high level Ph1, the switch closure of Ph2 control and the switch of Ph1 control all disconnects, i.e. and switching tube Q42, Q44, Q46 closure, Q41, Q43 disconnects.Sampling capacitance C1 and integrating capacitor C2 are discharged by short circuit, this moment, the voltage at sampling capacitance C1 two ends all was ground level, because the imaginary short effect of operational amplifier, the left pole plate of integrating capacitor C2 and right polar plate voltage all equal the DC voltage Vref of operational amplifier in-phase input end, and this moment, the output voltage of operational amplifier equaled Vref; Is under the low level situation at Ph1 for high level Ph2, the switch closure of Ph1 control and the switch of Ph2 control all disconnects, and this moment, its equivalent circuit was shown in Fig. 5-B.The left pole plate ground connection of sampling capacitance C1 in this case, and right polar plate voltage equals Vref, so sampling capacitance C1 will be recharged, the positive charge of the right pole plate band in charging back is Qc0=Vref*C1.Because the inverting input Inn of operational amplifier is the virtual earth point, so total amount of electric charge conservation on the right pole plate of the C1 that links to each other with Inn and the left pole plate of C2, so the right pole plate of C1 with positive charge Qc0 provide by the left pole plate of C2, be equivalent to the left pole plate of C2 has been filled the negative charge of Qc6=-Qc0, this moment C2 with the quantity of electric charge be Vref*C1, the right pole plate of C1 is reduced to Vref*C1/C2 to the voltage of left pole plate so, so the output voltage of operational amplifier is Opout=Vref+Vref*C1/C2=Vref* (1+C1/C2) at this moment.As seen, Opout and sampling capacitance C1 are linear, under the constant situation of Vref and C2, can obtain different operational amplifier output voltages by the size that changes C1.
The course of work that monitoring voltage produces circuit is as follows: clock signal C k3 produces clock Ph1 and the Ph2 that two-phase does not overlap by the two-phase clock generation circuit that do not overlap, by the front as can be known to the principle of work introduction of switched-capacitor integrator, when Ph2 is high level, the voltage of Opout will be reset and be Vref; Ph1 is that the voltage of Opout can become Vref* (1+C after the high level
Sampling capacitance/ C
Integrating capacitor), this magnitude of voltage is by capacitor C s1 and Cs2 sampling simultaneously; After Ph2 becomes high level again, the voltage of Opout will be reset again and be Vref, sampling maintained switch between this moment Cs1 and the Cs2, promptly switching tube Q45 disconnects, the monitoring voltage value Vref* (1+C that the top crown voltage Vout of capacitor C s2 is provided with when keeping Ph1 for high level
Sampling capacitance/ C
Integrating capacitor) constant.
The size of sampling capacitance C1 can be regulated by the control signal that the programming Control circuit produces; As shown in Figure 4, S1, S2, S3, S4, FPC01 several Control signal each with a capacitances in series and common formation sampling capacitance C1 in parallel with reference capacitance C0, when certain signal is high level, the switch closure of this signal controlling, the electric capacity that links to each other with this switch is in parallel with C0; When certain signal was low level, the switch of this signal controlling disconnected, and the electric capacity that links to each other with this switch is not in parallel with C0.The electric capacity in parallel value of sampling capacitance more at most is big more, and the electric capacity in parallel value of sampling capacitance more at least is more little, and the sampling capacitance C1 size of integrator is set after the Ck2 clock becomes low level.
As can be known from the above analysis: by pin PIN0 and PIN1 are taked different connected modes (connect power supply, ground connection, unsettled, two pins are unsettled and link to each other), the programming Control circuit can produce different control signals and change the size that monitoring voltage produces the sampling capacitance C1 of integrator in the circuit, thereby produces different monitoring voltages.
The real-time observation circuit of voltage comprises: voltage input to be monitored and open loop comparer.After monitoring voltage Vout produces, be sent to the in-phase input end of open loop comparer, with the voltage ratio to be monitored of inverting input, finish real-time monitoring.
In sum, the complete course of work of the programmable voltage monitoring circuit of the specific embodiment of the invention is: at first by single pin status decision circuitry and two asynchronous clock signals (CK0 and CK1) each pin is connect the judgement of power supply, ground connection and unsettled these three kinds of states, and with the D flip-flop that two high level trigger the state control signal (S1, S2 and S2B) that judges is latched.Secondly, carry out unsettled judgement by unsettled decision circuitry and another one asynchronous clock signal: as long as in the middle of PIN0 and the PIN1 pin is arranged is not to be in vacant state, FF01 will be low level (' 0 '), this expression there is no need to be determined further with unsettled continuous decision circuitry, and FF01 will directly be changed to 0 to unsettled continuous judgement signal FPC01; If these two pins of PIN0 and PIN1 all are in unsettled state, FF01 will be high level (' 1 ') so, expression needs to judge whether two unsettled pin PIN0 link to each other with PIN1: if two unsettled pins link to each other, output signal FPC01 will be high level (' 1 ') so; Otherwise FPC01 will be low level (' 0 ').
More than two circuit (single pin status decision circuitry and the unsettled decision circuitry that links to each other) later can produce following control signal and they are latched at three asynchronous clocks, they are respectively: S1, S2, S3, S4, FPC01.This several Control signal will be controlled the size that monitoring voltage produces the sampling capacitance of integrator in the circuit, produces different monitoring voltages with this.Monitoring voltage produces circuit and can latch the monitoring voltage that produces by a sampling hold circuit later at another one asynchronous clock signal CK3, then this voltage Vout being transported to the real-time voltage observation circuit treats monitoring voltage and monitors, if voltage to be monitored is greater than Vout, the output B1 of real-time voltage observation circuit will be low level (' 0 '); If voltage to be monitored is less than Vout, the output B1 of real-time voltage observation circuit will be high level (' 1 '), and the circuit of back will be taked further step to monitoring result so.
Because the present invention is except judging the state of single pin, also whether two unsettled pins are linked to each other and judge, therefore relative prior art, the present invention is (the programming number of pins is greater than 1) under the situation of identical programming pin, has more programming state, can know by inference, a N of the present invention pin has [3
N+ C
N 2* 3
N-2] individual state, wherein, N is programming number of pins, C
N 2For getting 2 combination among the N.Like this, be 0.1v in the programming precision equally, adopt under the situation of three programming pins, the variable range of program voltage of the present invention can reach 3.6v, thereby covers the common voltage scope of 1.8v to 5v fully.
The present invention simultaneously adopts switched-capacitor circuit to produce different monitoring voltages, has avoided the DC channel of feedback circuit to ground, has reduced dc power.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (8)
1. programmable voltage monitoring circuit, comprise that programming Control circuit, monitoring voltage produce circuit and the real-time observation circuit of voltage, it is characterized in that, described programming Control circuit comprises programming state selecting side and status determination circuit, described programming state selecting side be used for for the user select ground connection, connect power supply, unsettled and unsettled one of the four kinds of programming states that link to each other, the programming state that described status determination circuit is selected according to the user produces corresponding control signal and exports monitoring voltage generation circuit to; Described monitoring voltage produces circuit and exports the real-time observation circuit of voltage to according to the monitoring voltage that the described control signal of importing produces correspondence; The real-time observation circuit of described voltage is monitoring voltage and voltage to be monitored relatively, produces corresponding monitoring result.
2. programmable voltage monitoring circuit as claimed in claim 1 is characterized in that, described status determination circuit comprises single pin status decision circuitry, unsettled decision circuitry and the unsettled decision circuitry that links to each other; Described single pin status decision circuitry, its input end links to each other with the programming state selecting side, be respectively ground connection in order to produce with the programming state selecting side, corresponding control signal when connecing power supply or unsettled these three kinds of programming states, and export monitoring voltage generation circuit and unsettled decision circuitry to; Described unsettled decision circuitry is monitored the control signal that single pin status decision circuitry produces, and produces corresponding control signal and exports unsettled continuous decision circuitry to when a plurality of vacant state appears in the programming state selecting side determining; The input end of described unsettled continuous decision circuitry links to each other with the programming state selecting side, described unsettled continuous decision circuitry responds the control signal of unsettled decision circuitry input, produces circuit determining to produce control signal and export monitoring voltage to when unsettled continuous state appears in the programming state selecting side.
3. programmable voltage monitoring circuit as claimed in claim 2, it is characterized in that, described unsettled decision circuitry comprises digital operational circuit, described digital operational circuit is used for the control signal that any two single pin status decision circuitry produce is carried out digital operation, when judging that described two pins are in vacant state simultaneously, the output corresponding control signal is to unsettled continuous decision circuitry.
4. programmable voltage monitoring circuit as claimed in claim 3, it is characterized in that, described digital operational circuit comprise first rejection gate and first and the door, described unsettled continuous decision circuitry comprises second rejection gate, latch and second and door, described first rejection gate, two input ends are imported the control signal of described single pin status decision circuitry output respectively, and output terminal links to each other with door one input end with second with door with first respectively; Described first with the door another input end be clock signal input terminal, output terminal links to each other with described latch clock signal input terminal; Described second rejection gate, two input ends are imported the signal of programming state selecting side output respectively, output terminal links to each other with described latch input end, described latch output terminal links to each other with another input end of door with described second, and described second produces circuit with door output corresponding to the monitoring voltage that controls signal to of the unsettled state that links to each other.
5. programmable voltage monitoring circuit as claimed in claim 4 is characterized in that, described latch is a D flip-flop.
6. programmable voltage monitoring circuit as claimed in claim 4, it is characterized in that, described unsettled continuous decision circuitry also comprises level forming circuit, described level forming circuit comprises first node that links to each other with described second rejection gate, one input end and the Section Point that links to each other with described another input end of second rejection gate, described first node links to each other with two programming state selecting sides respectively with Section Point, be used for producing the logic opposite levels during state, when unsettled continuous state, produce the logic same level in unsettled not linking to each other.
7. as the arbitrary described programmable voltage monitoring circuit of claim 1 to 6, it is characterized in that, described monitoring voltage produces circuit and comprises switched-capacitor integrator, described switched-capacitor integrator comprises sampling capacitance, integrating capacitor, reference source, two-phase do not overlap clock and operational amplifier, described sampling capacitance is used for the control signal of described programming Control circuit output is coupled to operational amplifier one input end, described integrating capacitor is connected across between described operational amplifier input end and the operational amplifier output terminal, another input end of described operational amplifier links to each other with reference source, thereby the control signal control break sampling capacitance value of described programming Control circuit output makes monitoring voltage to change.
8. as the arbitrary described programmable voltage monitoring circuit of claim 1 to 6, it is characterized in that, comprise the open loop comparer in the real-time observation circuit of described voltage, described open loop comparer two input ends link to each other with voltage to be monitored with the monitoring voltage of monitoring voltage generation circuit output respectively.
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| CNB2007100758086A CN100516893C (en) | 2007-07-04 | 2007-07-04 | Programmable voltage monitoring circuit |
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| CNB2007100758086A CN100516893C (en) | 2007-07-04 | 2007-07-04 | Programmable voltage monitoring circuit |
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| CN101109775A true CN101109775A (en) | 2008-01-23 |
| CN100516893C CN100516893C (en) | 2009-07-22 |
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| CNB2007100758086A Active CN100516893C (en) | 2007-07-04 | 2007-07-04 | Programmable voltage monitoring circuit |
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| US4912423A (en) * | 1989-02-27 | 1990-03-27 | General Electric Company | Chopper-stabilized operational transconductance amplifier |
| US5541531A (en) * | 1995-05-01 | 1996-07-30 | Ford Motor Company | Switch capacitor interface circuit |
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| CN114253333A (en) * | 2021-12-16 | 2022-03-29 | 乐鑫信息科技（上海）股份有限公司 | Voltage stabilizer |
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