CN101106448A - Signal synchronization system - Google Patents
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- CN101106448A CN101106448A CNA200610106393XA CN200610106393A CN101106448A CN 101106448 A CN101106448 A CN 101106448A CN A200610106393X A CNA200610106393X A CN A200610106393XA CN 200610106393 A CN200610106393 A CN 200610106393A CN 101106448 A CN101106448 A CN 101106448A
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Abstract
A signal synchronization system comprises a plurality of synchronization units and a control unit. Each of the synchronization units corresponds to an output device respectively, allowing the control unit to correctively receive the output data from the output device. The control unit generates the system clock and the data selection signal according to the number of the output devices and the clock. The frequency of the system clock has to be high enough to allow the control unit to be able to receive all output data from the output devices. The data selection signal determines the order of data from the output devices received by the control unit. The control unit generates the output selection signal and arranges the output data from the output devices into the same signal to provide for a plurality of the receiving devices to receive. The output selection signal is used to label which receiving device should receive the data output by the control unit.
Description
Technical field
The invention relates to signal synchronizing system, be particularly to a plurality of receiving systems and how correctly receive the data that a plurality of output device is exported.
Background technology
Signal Synchronization all is a problem important in the electronic system all the time.For example, transmission or image information the transmission in system of multimedia messages in network system all needs the technology of signal Synchronization, makes receiving system correctly be received the data of output device.
Simultaneous techniques commonly used at present is: utilize quartz (controlled) oscillator that reference frequency is provided, and cooperate phase-locked loop (PLL) and frequency eliminator to produce different work clocks, use for devices different in the system.Yet the clock that the phase-locked loop produces has noise problem usually, makes that the work clock of each device is incomplete same in the system, causes receiving system can't correctly receive the signal of output device.
Calcspar shown in Figure 1 comprises classical signal synchro system 102.Output device 10a ..., 10n transmit signal S1 ..., Sn to receiving system 11a ..., 11z.Wherein, signal S1 ..., Sn include separately data with and the synchronizing information composition.Classical signal synchro system 102 receive these output devices 10a ..., signal S1 that 10n exported ..., Sn and work clock Clock1 ..., behind the Clockn, classical signal synchro system 102 can be respectively to output device 10a ..., after the output of 10n carries out the synchronization operation, corresponding output signal SA ..., SZ, and clock ClockA ..., ClockZ to receiving system 11a ..., 11z.Wherein, signal SA ..., SZ comprises separately through adjusted data of synchronization and synchronizing information.
Yet, classical signal synchro system 102 need be provided with a core assembly sheet stitch at each receiving system, increase along with output device and receiving system, the stitch of classical signal synchro system 102 (pin) number can become a kind of burden, not only the circuit layout of circuit board (circuit layout) can be quite complicated, and encapsulation (package) cost of chip (chip) and the cost of circuit board (PCB) also can rise.Therefore, need a kind of technology that addresses the above problem.
Summary of the invention
Signal synchronizing system provided by the present invention (synchronization system) not only makes a plurality of receiving systems and a plurality of output device synchronous, can also reduce the needed stitch number of chip, make circuit layout simpler and easy, reduce the cost of manufacture of Chip Packaging and printed circuit board (PCB) simultaneously.
The invention provides a kind of signal synchronizing system, comprising a plurality of lock units and a control unit.The corresponding separately output device of these lock units.This control unit (control unit) produces system clock (system clock) and data select signal.This data select signal determines which lock unit (synchronization device) can begin to carry out synchronized operation.And according to output signal, system clock and the data select signal of pairing output device, lock unit can carry out the synchronization operation to the output signal of output device, and control unit receives the output signal through the adjusted output device of synchronization.According to output signal and this system clock of these lock units, this control unit produces output and selects signal.And select signal by system clock and output, a plurality of receiving systems of control unit may command receive the output signal through the adjusted output device of synchronization, and make receiving system receive the data that output device is exported synchronously.
Signal synchronizing system proposed by the invention also can be applicable to the Bitstream signal transmission of many output devices.
The disclosed technology of the present invention also is applicable to other situation.For example: the data that a plurality of output device is exported all are sent to single receiving system or the data that a plurality of output device is exported are sent to a plurality of receiving systems.
Description of drawings
Fig. 1 is the embodiment of classical signal synchro system;
Fig. 2,3,4,5 is the enforcement figure of signal synchronizing system;
Fig. 6 is the circuit diagram of signal synchronizing system;
Fig. 7 is the sequential chart of the output control of signal synchronizing system;
The view data how Fig. 8,9 shows signal synchro systems are exported a plurality of output device is passed to single receiving system;
Figure 10 is the embodiment of the mentioned lock unit of this specification;
Figure 11 show detect and synchronization discrepancy that measuring appliance 1002 is produced apart from the meaning of signal Vph_A, Vph_B representative;
Figure 12 is another embodiment of the mentioned lock unit of this specification;
Figure 13 show detect and synchronization discrepancy that measuring appliance 1302 is produced apart from the meaning of signal Hph_A, Hph_B representative.
[main element label declaration]
102～classical signal synchro system; 202～control unit;
302～control unit; 402～control unit;
502～control unit;
600～signal synchronizing system; Generator is selected in 602～output;
604～output select circuit; 606～multiplex (MUX) controller;
612～control signal; 702-706～pulse signal;
902,1002～control unit; 904,1004～receiving system;
1102～detect and measuring appliance; 1104～signal generator;
1106～comparator;
1108～horizontal-drive signal quantity produces circuit;
1110～horizontal-drive signal quantity deletion circuit;
1112～horizontal-drive signal length counter;
1114～the second vertical synchronizing signal generators;
1122～the second vertical synchronizing signals; 1124～parameter signal;
1126～positive horizontal-drive signal; 1128～negative horizontal-drive signal;
1130～count results signal;
1302～detect and measuring appliance; 1304～signal generator;
1306～comparator; 1308～data generating circuit;
1310～data deletion circuit; 1312～data buffering and controller;
1314～the second horizontal-drive signal generators;
1322～the second horizontal-drive signals; 1324～parameter signal;
1326～positive data signal; 1328～negative data signal;
10a～10n, 20a～20n, 30a～30n, 40a～40n, 50a～50n, 80a～80n, 90a～90n～output device;
11a～11z, 21a～21z, 31a～31z, 41a～41z, 51a～51z, 81a～81z, 91a～91z～receiving system;
12a～12n, 22a～22n, 32a～32n, 42a～42n, 52a～52n, 62a～62n, 82a～82n, 92a～92n～lock unit;
Embodiment
Fig. 2 is the enforcement figure of a signal synchronizing system provided by the present invention.This signal synchronizing system can be applicable to the situation that a plurality of output device transmission data are given a plurality of receiving systems.This signal synchronizing system include a plurality of lock unit 22a ..., 22n and a control unit 202.Lock unit 22a ..., the corresponding separately output device of 22n (be respectively 20a ..., 20n).Control unit 202 according to the number n of these output devices and clock Clock1 ..., Clockn produces system clock Clock_sys and data select signal Data_sel.Under the situation of using system clock Clock_sys, the order that control unit 202 receives data is to be determined by data select signal Data_sel.The content of data select signal Data_sel can be the code name of these output devices.For example, if the quantity of output device is that 2 (n=2), work clock are all 66MHz (Clock1=Clock2=66MHz), then system clock Clock_sys can be set at 132MHz, and data select signal Data_sel is along with system clock Clock_sys changes between " 1 " and " 2 " back and forth.
When lock unit 22a～22 carry out synchronization operation, by being determined according to the signal S1 of output device 20a output and, system clock Clock_sys and data select signal Data_sel.And after carrying out the synchronization operation, signal S1～Sn is adjusted into signal S1 '～Sn '.
Because system clock Clock_sys is by being provided by control unit 202, therefore when control unit 202 provide system clock Clock_sys to lock unit 22a～22n to carry out synchronization, and control unit 202 is when utilizing system clock Clock_sys control that signal is inputed to receiving system 21a～21z, all operations is all based on system clock Clock_sys, also therefore, the signal transmission that output device 20a～22n and receiving system 21a～21z ask, design by the present invention, still belong to synchronous, and compare with known, the signal number between output device 20a～20n and receiving system 21a and 21z is evident as few.
Fig. 3 is the enforcement figure of signal synchronizing system provided by the present invention.On other was used, lock unit 32a～32n can be corresponding built-in (buildin) in output device 30a～30n, and notion as Fig. 2, control unit 302 can be passed to receiving system 21a～21z synchronously with the output of a plurality of output device 30a～30n.
Fig. 4 is the enforcement figure of signal synchronizing system provided by the present invention.The signal of output device 40a～40n output includes vertical synchronizing signal (horizontal synchronization signal, show in the drawings), horizontal-drive signal (vertical synchronization signal shows in the drawings) and data-signal (showing in the drawings).Lock unit 42a～42n carries out the synchronization adjustment in order to the output to output device 40a～40n respectively, and adjusts back output and export horizontal-drive signal Hs1 ', vertical synchronizing signal Vs1 ', data-signal Data1 ' respectively ... horizontal-drive signal Hsn ', vertical synchronizing signal Vsn ', data-signal Datan '.
Similarly, the notion according to the present invention, control unit 402 is controlled each lock unit 42a～42n by system clock Clock_sys and data select signal Data_sel and is carried out the synchronization operation.And, horizontal-drive signal Hs1 ', vertical synchronizing signal Vs1 ', data-signal Data1 ' ... horizontal-drive signal Hsn ', vertical synchronizing signal Vsn ', data-signal Datan ' during by control unit 402 outputs for being defined as horizontal-drive signal Hs_sys, vertical synchronizing signal Vs1_sys, and data-signal Data_sys.To horizontal-drive signal Hs_sys, vertical synchronizing signal Vs1_sys, and the output of data-signal Data_sys control, then select signal Out_sel to receiving system 41a～41z by control unit 402 output system clock Clock_sys and output.
Fig. 5 is the enforcement figure of signal synchronizing system.Output device 50a～50n is output as Bitstream signal (not showing in the drawings).Lock unit 52a～52n can distinguish output bit flow signal Bitstreaml '～Bitstreamn '.And Bitstream signal Bitstreaml '～Bitstreamn ' is defined as Bitstream signal Bitstream_sys when being exported by control unit 502.
Still the notion according to the present invention is controlled each lock unit 52a～52n by system clock Clock_sys and data select signal Data_sel and is carried out the synchronization operation.And select signal Out_sel to receiving system 41a～41z by control unit 402 output system clock Clock_sys and output, with the output of control bit stream signal Bitstream_sys.
Fig. 6 is the circuit diagram of signal synchronizing system.This signal synchronizing system 600 comprises lock unit 62a～62n, output selection generator (output_sel generator) 602, output select circuit (output_select circuit) 604, and multiplex's controller (multiplexer ﹠amp; Controller) 606.According to lock unit 62a ..., 62n horizontal-drive signal Hs1 ', the vertical synchronizing signal Vs1 ' of output respectively ..., horizontal-drive signal Hsn ', vertical synchronizing signal Vsn ', control unit 402 output horizontal-drive signal Hs_sys and vertical synchronizing signal Vs_sys.According to system clock Clock_sys and horizontal-drive signal Hs_sys and vertical synchronizing signal Vs_sys, output is selected generator 602 to produce output and is selected signal Out_sel.Select signal Out_sel according to system clock Clock_sys, output, and horizontal-drive signal Hs_sys and vertical synchronizing signal Vs_sys, output select circuit 604 produces control signal 612.According to control signal 612.Output is selected signal Out_sel to be used for control data signal Data_sys should to be received by which receiving system.
Fig. 7 is the sequential chart of the output control of signal synchronizing system.Please also refer to Fig. 4, control unit 402 by clock signal of system Clock_sys collocation output select signal Out_sel (or Out_sel[a], Out_sel[b], Out_sel[c] ...), whether 41a～41b receives the data-signal Data_sys that follows after horizontal-drive signal Hs_sys and vertical synchronizing signal Vs_sys with the control receiving system.Wherein, select the form that signal Out_sel can Bitstream signal to exist, the mode of enforcement such as Fig. 7 select to have the message whether receiving system 41a～41b can receive behind its header of signal Out_sel.Or, select signal Out_sel[a], Out_sel[b], Out_sel[c] ... form that can pulse signal exists, and the mode of enforcement is controlled the message whether receiving system 41a～41b can receive respectively with many pulse signals also as shown in Figure 7.
Fig. 8 has shown that the view data how signal synchronizing system is exported a plurality of output device is passed to single receiving system.Control unit 802 is controlled each lock unit 82a～82n by system clock Clock_sys and data select signal Data_sel and whether is carried out the synchronization operation.Lock unit 82a～82n can be respectively be adjusted into horizontal-drive signal Hs1 ', vertical synchronizing signal Vs1 ', data-signal Data1 ' with output horizontal-drive signal Hs1, vertical synchronizing signal Vs1, data-signal Data1..., horizontal-drive signal Hsn ', vertical synchronizing signal Vsn ', the data-signal Datan synchronization of output device 80a～80z ..., horizontal-drive signal Hsn ', vertical synchronizing signal Vsn ', the output of data-signal Datan ' back.And after control unit 802 receives the output of lock unit 82a～82n, then can export in regular turn or according to preestablishing output, and be defined as horizontal-drive signal Hs_sys, vertical synchronizing signal Vs_sys, data-signal Data_sys during output.
Fig. 9 has also shown that the view data how signal synchronizing system is exported a plurality of output device is passed to single receiving system.Wherein, output device 90a～90n, signal synchronizing system (lock unit 92a～92n and control unit 1002), and 1004 signal transfer modes of receiving system, roughly identical with Fig. 8, just synchronizing signal and data-signal merging are defined with Bitstream signal.
Signal synchronizing system provided by the present invention also can be applicable to other situation.For example: the data that a plurality of output device is exported are sent to respectively in corresponding a plurality of receiving system.Wherein receiving system equates with the quantity of output device, the respectively corresponding output device of each receiving system.
Figure 10 is the embodiment of the mentioned lock unit of this specification.The phase place (phase) of second vertical synchronizing signal 1122 that detection and measuring appliance (detectionand measure device) the 1002 detection first vertical synchronizing signal Vs1 and signal generator (signalgenerator) 1004 are provided is poor, to produce synchronization discrepancy apart from signal Vph_A, Vph_B.Comparator 1106 compares apart from signal Vph_A, Vph_B and previous synchronization discrepancy this synchronization discrepancy apart from signal, and produces parameter signal 1124 according to its variable quantity.According to this parameter signal 1124, horizontal-drive signal quantity produces circuit (Hs generatingcircuit) 1108 and produces positive horizontal-drive signal 1126, so that the length that the inactive area of this second horizontal-drive signal increases is the integral multiple of receive clock ClockR, horizontal-drive signal quantity deletion circuit (Hseliminating circuit) 1110 produces negative horizontal-drive signal 1128, so that the length that the inactive area of this second horizontal-drive signal reduces is the integral multiple of receive clock ClockR, and horizontal-drive signal length counter (Hs length counter) 1112 produces the count results signal 1130 of length less than the length of a receive clock.The second vertical synchronizing signal generator 1114 according to this parameter signal 1124, this positive horizontal-drive signal 1126, this negative horizontal-drive signal 1128 and this count results signal 1130, is adjusted the length of the inactive area of this second vertical synchronizing signal Vs1 '.
Figure 11 show detect and synchronization discrepancy that measuring appliance 1002 is produced apart from the meaning of signal Vph_A, Vph_B representative.Wherein, compare the first vertical synchronizing signal Vs1 and the second vertical synchronizing signal Vs1 ', the inactive area starting point b that makes inactive area starting point a to the first vertical synchronizing signal Vs1 of the second vertical synchronizing signal Vs1 ' be synchronization discrepancy apart from signal Vph_A, and to make the inactive area terminating point c of inactive area starting point a to the first vertical synchronizing signal Vs1 of the second vertical synchronizing signal Vs1 ' be that synchronization discrepancy is apart from signal Vph_B.
Figure 12 is another embodiment of the mentioned lock unit of this specification.The phase difference of second vertical synchronizing signal 1322 that detection and the measuring appliance 1302 detection first horizontal-drive signal Hs1 and signal generator 1304 are provided is to produce synchronization discrepancy apart from signal Hph_A, Hph_B.Comparator (comparator) 1306 compares apart from signal Hph_A, Hph_B and previous synchronization discrepancy this synchronization discrepancy apart from signal, and produces parameter signal 1324 according to its variable quantity.According to this parameter signal 1324, data generating circuit (dummydata generating circuit) 1308 produces positive data signal 1326, with the length between the dead space that increases this second horizontal-drive signal, data deletion circuit (data eliminating circuit) 1310 produce negative data signal 1328, with the length between the dead space of reducing this second horizontal-drive signal.Data buffering and controller 1312 be according to this parameter signal 1324, this positive data signal 1326 and this negative data signal 1328, adjusts the length between the dead space of this first data-signal Data1, to produce this second data-signal Data1 '.The second horizontal-drive signal generator 1314 according to this parameter signal 1324, this positive data signal 1326, this negative data signal 1328 and this second data-signal Data1 ', is adjusted the length of the inactive area of this second horizontal-drive signal.
Figure 13 show detect and synchronization discrepancy that measuring appliance 1302 is produced apart from the meaning of signal Hph_A, Hph_B representative.Wherein, compare the first horizontal-drive signal Hs1 and the second horizontal-drive signal Hs1 ', the inactive area starting point b that makes inactive area starting point a to the first horizontal-drive signal Hs1 of the second horizontal-drive signal Hs1 ' be synchronization discrepancy apart from signal Hph_A, and to make the inactive area terminating point c of inactive area starting point a to the first horizontal-drive signal Hs1 of the second horizontal-drive signal Hs1 ' be that synchronization discrepancy is apart from signal Hph_B.
The mentioned lock unit of the present invention also can adopt other technology.Every data by adjusting output device all belong to operable lock unit among the present invention so that the technology of correct data to control unit to be provided, and have belonged to the category of institute of the present invention desire protection.
Above embodiment is not to be used for limiting the scope of the invention only with helping understand the present invention.Any device or technology that is produced based on the claim scope all belongs to the scope that this specification institute desire is protected.
Claims (36)
1. signal synchronizing system, comprising:
A plurality of lock units receive the output of a plurality of output devices respectively, and these lock units are exported respectively synchronization operation back is carried out in the output of these output devices according to system clock and data select signal; And
Control unit provides this system clock, this data select signal, and this control unit receives the output of this lock unit, this control unit this system clock is provided and this lock unit of being received export receiving system to.
2. signal synchronizing system according to claim 1, wherein the output of this output device includes first clock, first synchronizing signal, and first data-signal, and the output of this lock unit comprises second synchronizing signal and second data-signal.
3. signal synchronizing system according to claim 2, wherein this lock unit comprises:
Detecting and measuring appliance, is according to this system clock and this first clock, this first synchronizing signal and this second synchronizing signal, to export synchronization discrepancy apart from signal; And
Signal generator, be according to this synchronization discrepancy apart from signal, to export behind the siding-to-siding block length of adjusting this second synchronizing signal, wherein this signal generator produces this second synchronizing signal according to this system clock.
4. signal synchronizing system according to claim 3, wherein this first synchronizing signal comprises first horizontal-drive signal and first vertical synchronizing signal, this second synchronizing signal comprises second horizontal-drive signal and second vertical synchronizing signal.
5. the signal Synchronization device of system according to claim 4, wherein this detection and measuring appliance detect this first clock, this system clock, this first vertical synchronizing signal, this second vertical synchronizing signal, this signal generation device is in this second vertical synchronizing signal interval, adjust in the length of the quantity of this second horizontal-drive signal and this second horizontal-drive signal, the alternatively is to adjust the siding-to-siding block length of this second vertical synchronizing signal.
6. the signal Synchronization device of system according to claim 4, wherein this detection and measuring appliance detect this first clock, this system clock, this first horizontal-drive signal, this second horizontal-drive signal, this signal generation device is in this second horizontal-drive signal interval, adjust the data length of this first data-signal, or adjust this second horizontal-drive signal length, to adjust the length of this second horizontal-drive signal.
7. signal synchronizing system according to claim 1, wherein the output of this output device includes first clock, first Bitstream signal, and the output of this lock unit comprises second Bitstream signal.
8. signal synchronizing system according to claim 1, wherein signal is selected in this control unit utilization output, the output of this lock unit that control is received is received by a plurality of output device, and this output selects signal to can be alternatively between pulse signal and Bitstream signal.
9. signal synchronizing system according to claim 8, wherein this control unit also comprises:
Generator is selected in output, according to the synchronizing signal of this system clock and the output of this lock unit, selects signal to produce this output;
Output select circuit is selected signal according to this system clock, this output, and the synchronizing signal of this lock unit output, with the decision control signal; And
Multiplex's controller receives the data-signal that this lock unit is exported, and the data-signal of exporting according to this lock unit that this control signal control output has received.
10. signal synchronizing system according to claim 1, wherein this data select signal can be alternatively between pulse signal and Bitstream signal.
11. a signal synchronizing system, comprising:
A plurality of lock units receive the output of a plurality of output devices respectively, and these lock units are exported respectively synchronization operation back is carried out in the output of these output devices according to system clock and data select signal; And
Control unit, this system clock, this data select signal are provided, this control unit receives the output of these lock units, and this control unit utilizes this system clock and output to select signal, is received by a plurality of receiving system with the output of controlling these lock units that received.
12. signal synchronizing system according to claim 11, wherein the output of this output device includes first clock, first synchronizing signal and first data-signal, and the output of this lock unit comprises second synchronizing signal and second data-signal.
13. signal synchronizing system according to claim 12, wherein this lock unit comprises:
Detecting and measuring appliance, is according to this system clock and this first clock, this first synchronizing signal and this second synchronizing signal, to export synchronization discrepancy apart from signal; And
Signal generator, be according to this synchronization discrepancy apart from signal, to export behind the siding-to-siding block length of adjusting this second synchronizing signal, wherein this signal generator produces this second synchronizing signal according to this system clock.
14. signal synchronizing system according to claim 13, wherein this first synchronizing signal comprises first horizontal-drive signal and first vertical synchronizing signal, and this second synchronizing signal comprises second horizontal-drive signal and second vertical synchronizing signal.
15. the signal Synchronization device of system according to claim 14, wherein this detection and measuring appliance detect this first clock, this system clock, this first vertical synchronizing signal, this second vertical synchronizing signal, this signal generation device is in this second vertical synchronizing signal interval, adjust in the length of the quantity of this second horizontal-drive signal and this second horizontal-drive signal, the alternatively is to adjust the siding-to-siding block length of this second vertical synchronizing signal.
16. the signal Synchronization device of system according to claim 14, wherein this detection and measuring appliance detect this first clock, this system clock, this first horizontal-drive signal, this second horizontal-drive signal, this signal generation device is in this second horizontal-drive signal interval, adjust the data length of this first data-signal, or adjust this second horizontal-drive signal length, to adjust the length of this second horizontal-drive signal.
17. signal synchronizing system according to claim 11, wherein the output of this output device includes first clock, first Bitstream signal, and the output of this lock unit comprises second Bitstream signal.
18. signal synchronizing system according to claim 11, wherein this control unit also comprises:
Generator is selected in output, according to the synchronizing signal of this system clock and the output of this lock unit, selects signal to produce this output;
Output select circuit is according to the synchronizing signal of this system clock, this output selection signal and the output of this lock unit, with the decision control signal; And
Multiplex's controller receives the data-signal that this lock unit is exported, and the data-signal of exporting according to this lock unit that this control signal control output has received.
19. signal synchronizing system according to claim 11, wherein this data select signal and this output select signal to can be alternatively between pulse signal and Bitstream signal.
20. a signal synchronizing system, comprising:
A plurality of lock units receive the output of a plurality of output devices respectively, and these lock units are exported respectively synchronization operation back is carried out in the output of these output devices according to system clock and data select signal; And
Control unit, this system clock, this data select signal are provided, this control unit receives the output of these lock units, and this control unit utilizes this system clock and this data select signal, is received device with the output of controlling these lock units that received and is received.
21. signal synchronizing system according to claim 20, wherein the output of this output device includes first clock, first synchronizing signal, and first data-signal, and the output of this lock unit comprises second synchronizing signal and second data-signal.
22. signal synchronizing system according to claim 21, wherein this lock unit comprises:
Detecting and measuring appliance, is according to this system clock and this first clock, this first synchronizing signal and this second synchronizing signal, to export synchronization discrepancy apart from signal; And
Signal generator, be according to this synchronization discrepancy apart from signal, to export behind the siding-to-siding block length of adjusting this second synchronizing signal, wherein this signal generator produces this second synchronizing signal according to this system clock.
23. signal synchronizing system according to claim 22, wherein this first synchronizing signal comprises first horizontal-drive signal and first vertical synchronizing signal, and this second synchronizing signal comprises second horizontal-drive signal and second vertical synchronizing signal.
24. the signal Synchronization device of system according to claim 23, wherein this detection and measuring appliance detect this first clock, this system clock, this first vertical synchronizing signal, this second vertical synchronizing signal, this signal generation device is in this second vertical synchronizing signal interval, adjust in the length of the quantity of this second horizontal-drive signal and this second horizontal-drive signal, the alternatively is to adjust the siding-to-siding block length of this second vertical synchronizing signal.
25. the signal Synchronization device of system according to claim 23, wherein this detection and measuring appliance detect this first clock, this system clock, this first horizontal-drive signal, this second horizontal-drive signal, this signal generation device is in this second horizontal-drive signal interval, adjust the data length of this first data-signal, or adjust this second horizontal-drive signal length, to adjust the length of this second horizontal-drive signal.
26. signal synchronizing system according to claim 20, wherein the output of this output device includes first clock, first Bitstream signal, and the output of this lock unit comprises second Bitstream signal.
27. signal synchronizing system according to claim 20, wherein this control unit also comprises:
Output select circuit is according to the synchronizing signal decision control signal of this system clock, this data select signal and the output of these lock units; And
Multiplex's controller receives the data-signal that these lock units are exported, and the data-signal of exporting according to these lock units that this control signal control output has received.
28. signal synchronizing system according to claim 20, wherein this data select signal can be alternatively between pulse signal and Bitstream signal.
29. a signal synchronizing system, comprising:
A plurality of lock units receive the output of a plurality of output devices respectively, and these lock units are exported respectively synchronization operation back is carried out in the output of these output devices according to system clock and data select signal; And
Control unit, this system clock, this data select signal are provided, this control unit receives the output of these lock units, this control unit utilizes this system clock and output to select signal, be transferred into pairing receiving system with the output of controlling these lock units that received, wherein receiving system equates with the quantity of output device, the respectively corresponding output device of each receiving system.
30. signal synchronizing system according to claim 29, wherein the output of this output device includes first clock, first synchronizing signal and first data-signal, and the output of this lock unit comprises second synchronizing signal and second data-signal.
31. signal synchronizing system according to claim 30, wherein this lock unit comprises:
Detecting and measuring appliance, is according to this system clock and this first clock, this first synchronizing signal and this second synchronizing signal, to export synchronization discrepancy apart from signal; And
Signal generator, be according to this synchronization discrepancy apart from signal, to export behind the siding-to-siding block length of adjusting this second synchronizing signal, wherein this signal generator produces this second synchronizing signal according to this system clock.
32. signal synchronizing system according to claim 31, wherein this first synchronizing signal comprises first horizontal-drive signal and first vertical synchronizing signal, and this second synchronizing signal comprises second horizontal-drive signal and second vertical synchronizing signal.
33. the signal Synchronization device of system according to claim 32, wherein this detection and measuring appliance detect this first clock, this system clock, this first vertical synchronizing signal, this second vertical synchronizing signal, this signal generation device is in this second vertical synchronizing signal interval, adjust in the length of the quantity of this second horizontal-drive signal and this second horizontal-drive signal, the alternatively is to adjust the siding-to-siding block length of this second vertical synchronizing signal.
34. the signal Synchronization device of system according to claim 32, wherein this detection and measuring appliance detect this first clock, this system clock, this first horizontal-drive signal, this second horizontal-drive signal, this signal generation device is in this second horizontal-drive signal interval, adjust the data length of this first data-signal, or adjust this second horizontal-drive signal length, to adjust the length of this second horizontal-drive signal.
35. signal synchronizing system according to claim 29, wherein this control unit also comprises:
Generator is selected in output, according to the synchronizing signal of this system clock and the output of these lock units, selects signal to produce this output;
Output select circuit is according to the synchronizing signal of this system clock, this output selection signal and the output of these lock units, with the decision control signal; And
Multiplex's controller receives the data-signal that these lock units are exported, and the data-signal of exporting according to these lock units that this control signal control output has received.
36. signal synchronizing system according to claim 29, wherein this data select signal and this output select signal to can be alternatively between pulse signal and Bitstream signal.
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| CNA200610106393XA CN101106448A (en) | 2006-07-14 | 2006-07-14 | Signal synchronization system |
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| CNA200610106393XA CN101106448A (en) | 2006-07-14 | 2006-07-14 | Signal synchronization system |
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2006
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Open date: 20080116 |