CN101101445A - Two-dimensional nanostructure deep etching method - Google Patents
Two-dimensional nanostructure deep etching method Download PDFInfo
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- CN101101445A CN101101445A CNA200610091006XA CN200610091006A CN101101445A CN 101101445 A CN101101445 A CN 101101445A CN A200610091006X A CNA200610091006X A CN A200610091006XA CN 200610091006 A CN200610091006 A CN 200610091006A CN 101101445 A CN101101445 A CN 101101445A
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Abstract
The invention is a 2D nano structure deeply etching method, characterized in that it comprises the steps of: S01. coating photoresist on a substrate, adopting electron beam exposure or other exposure technique to make photon crystal nano pattern on the photoresist; S02. transferring the photon crystal nano pattern onto the substrate; S03. after nano pattern transfer, removing the photoresist from the substrate surface and adopting thermal oxidization process to oxidize part of the nano structure to generate SiO2; S04. taking a to-be-etched III-V family semiconductor substrate and making the substrate surface with nano structure opposite to the to-be-etched surface of the III-V family semiconductor substrate, utilizing nonplanar bonding technique to bond the two materials; and S05. adopting thinning process to thin the substrate to the nano structure oxidized into SiO2.
Description
Technical field
The present invention relates to III-V family semiconductor nano level processing technique field, particularly relate to two-dimensional nanostructure, as the implementation method of the deep erosion of photon crystal structure.
Background technology
In recent years, with the photonic crystal be the nano-device research acquisition develop rapidly of representative.The polarization separation of waveguide, the light beam of submicron order, devices such as path filter, bandpass filter, microdefect cavity laser and edge-emitting laser up and down on the 2 D photon crystal basis of based semiconductor material, have successfully been realized, the development of photon crystal device and improving to realizing that the photon integrated circuit created necessary condition.Because silicon materials are indirect bandgap material, be unfavorable in the photon integrated circuit, realizing that light source is integrated, it greatly may be to realize on III-V family semiconductor material that the therefore following optical chip has.At present, various light functional units based on III-V family semiconductor material are realized on a kind of photonic crystal thin plate usually, promptly the thickness of being made by high-index material is the thin plate of hundreds of nanometers, top and bottom are covered by the very big low-index material of contrast, and the 2 D photon crystal figure vertically passes through thin plate.Thin plate has the suspension structure that is coated by air up and down, and perhaps top is air, and SiO is arranged below
2Or Al
2O
3The unsymmetric structure that supports.But this thin-slab construction is difficult to popularize in actual applications, the mechanical property of suspension structure and heat conductivility extreme difference, and even mould exists coupling [Yoshinori Tanaka, Takashi Asano, Ranko Hatsuta with strange intermode in the unsymmetric structure, and Susumu Noda, the applied physics wall bulletin, 88 volumes, 011112 (2006)], make the pattern loss aggravation on the direction that is parallel to the thin plate plane that is positioned at even mould forbidden band, these two kinds of structures are difficult to all realize that electricity injects pumping simultaneously.The method of problem epitaxial growth conventional semiconductor laser on III-V family Semiconductor substrate is led limiting structure a little less than using always above solving, and by anisotropic dry etch process photonic crystal pattern is transferred in the substrate again.This structure realizes that easily electricity injects pumping, and mechanical property also is enhanced, report [the Thomas D.Happ of existing waveguide and edge-emitting laser, Martin Kamp, Alfred Forchel, Jean-LouisGentner and L.Goldstein, the applied physics wall bulletin, 82 volumes, 4 (2003); M.Mulot, S.Anand, M.Swillo, M.Qiu, B.Jaskorzynska, A.Talneau, vacuum technology periodical B, 21 volumes, 900 (2003)].Light needs to be led restriction by weak guided wave simultaneously and modulated by photon crystal structure in this structure, thereby the deep erosion of photon crystal structure is necessary.In present etching technics, be to adopt photoresist directly to make the mask layer etching, or on III-V family Semiconductor substrate deposit one deck SiO
2Or SiNx, with the figure transfer on the photoresist behind illuvium, carry out etching with illuvium as mask layer again, but the nanostructured exposure does not allow blocked up photoresist, thereby the thickness of the mask layer that uses of these two kinds of methods can not surpass the 500-600 nanometer, and Bao mask layer has restricted the transfer degree of depth of nanostructured excessively.The maximum transfer degree of depth of photon crystal structure only reaches about 4.5 microns [M.Mulot under optimized conditions at present, S.Anand, R.Ferrini, B.Wild, R.Houdre, J.Moosburger andA.Forchel, vacuum technology periodical B, 22 volumes, 707 (2004)], this makes that the loss of vertical direction is bigger, is necessary to improve lithographic technique, makes photon crystal structure realize the transfer of the bigger degree of depth.
Summary of the invention
The objective of the invention is to overcome so that the shortcoming of technology to be arranged, a kind of two-dimensional nanostructure deep etching method is provided, it is the method that realizes nanostructure deep etchings such as photonic crystal on III-V family semiconductor material, by new mask fabrication technique, improves the anisotropic dry etch degree of depth.
The performing step of the inventive method is as follows:
A kind of two-dimensional nanostructure deep etching method of the present invention is characterized in that, comprises the steps:
S01, on substrate, apply photoresist, adopt electron beam exposure or other exposure technique on photoresist, to produce the photonic crystal nano graph;
S02, the photonic crystal nano graph is transferred on the substrate;
S03, after nano graph shifts, the photoresist of substrate surface is removed, adopt thermal oxidation technology will have the partial oxidation of nanostructured to generate SiO
2
S04, get an III-V family Semiconductor substrate to be etched, the surface that described substrate is had a nanostructured and III-V family Semiconductor substrate to be etched is relative, utilizes the on-plane surface bonding techniques, and two kinds of materials are bonding;
S05, employing reduction process extremely only stay the already oxidised SiO that is with substrate thinning
2Nanostructured.
Wherein substrate is silicon substrate or n type silicon substrate.
Among the wherein said step S02, the employing fluorine base gas is that the dry etching technology of source of the gas is transferred to silicon substrate with nano graph.
Among the wherein said step S02, adopt the galvanic corrosion technology that nano graph is transferred to n type silicon substrate.
The invention has the beneficial effects as follows:
Two-dimensional nanostructure deep etching method of the present invention can obtain the SiO that thickness surpasses 2 microns
2Mask layer.With respect to existing lithographic method because mask layer thickness has had the raising of an order of magnitude, in etching selection ratio identical or near the time, can realize the darker etching of nanostructureds such as photonic crystal.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is a process chart of the present invention.
Embodiment
See also shown in Figure 1ly, a kind of two-dimensional nanostructure deep etching method of the present invention comprises the steps:
S01, apply photoresist on substrate, adopt electron beam exposure or other exposure technique to produce the photonic crystal nano graph on photoresist, described substrate is silicon substrate or n type silicon substrate;
S02, the photonic crystal nano graph is transferred on the substrate; Among the described step S02, the employing fluorine base gas is that the dry etching technology of source of the gas is transferred to silicon substrate with nano graph or transferred to n type silicon substrate;
S03, after nano graph shifts, the photoresist of substrate surface is removed, adopt thermal oxidation technology will have the partial oxidation of nanostructured to generate SiO
2
S04, get an III-V family Semiconductor substrate to be etched, the surface that described substrate is had a nanostructured and III-V family Semiconductor substrate to be etched is relative, utilizes the on-plane surface bonding techniques, and two kinds of materials are bonding;
S05, employing reduction process extremely only stay the already oxidised SiO that is with substrate thinning
2Nanostructured.
Below in conjunction with specific embodiment the present invention is described in further detail.
Embodiment 1:
Please shown in Figure 1 in conjunction with consulting again, two-dimensional nanostructure deep etching method of the present invention comprises the steps:
Step S01: on silicon substrate, apply the thick electron beam resist of 300nm,, obtain the figure of nanostructured with developing through electron beam exposure as PMMA;
Step S02: adopt reactive ion beam or inductively coupled plasma lithographic technique with figure transfer to silicon substrate, the control underlayer temperature is below 10 ℃ in using C4F8 source of the gas and etching, can obtain＞20: 1 selection ratio, the etching of nanostructured shifts the degree of depth and can reach more than 5 microns;
Step S03: have the surface of nanostructured to make thermal oxidation silicon substrate, make nanostructured be oxidized to SiO
2Epitaxial growth InP cushion, InGaAsP multi layer quantum well and InP overlayer successively on the InP substrate comprise that the gross thickness of quantum well reaches 10 microns;
Step S04: with the SiO of silicon substrate
2Face and InP substrate bond together by the on-plane surface bonding techniques;
Step S05: utilize reduction process to remove silicon unnecessary on the silicon substrate and SiO
2, only stay the nanostructured of about 2 micron thickness.
With SiO
2Nanostructured is that mask carries out dry etching to the InP substrate, can adopt technology such as chemically assisted ion beam etching or inductively coupled plasma etching, as with the inductively coupled plasma etching, select when using the chloro source of the gas specific energy reach＞5: 1, can make nanostructured reach 10 microns with the mask of 2 micron thickness in the transfer degree of depth of InP substrate.
Embodiment 2:
Please shown in Figure 1 in conjunction with consulting again, two-dimensional nanostructure deep etching method of the present invention comprises the steps:
Step S01: on n type silicon substrate, apply electron beam resist, obtain the figure of nanostructured with developing through electron beam exposure;
Step S02: adopt the electrochemical etching technology that figure transfer is arrived silicon substrate, the transfer degree of depth of nanostructured can reach more than 50 microns;
Step S03: have the surface of nanostructured to make thermal oxidation silicon substrate, make nanostructured be oxidized to SiO
2Epitaxial growth GaAs cushion, AlGaAs limiting layer, InGaAs quantum dot layer, AlGaAs limiting layer and GaAs overlayer successively on the GaAs substrate, the gross thickness of epitaxial structure reaches 15 microns;
Step S04: with the SiO of silicon substrate
2Face and InP substrate bond together by the on-plane surface bonding techniques;
Step S05: utilize reduction process to remove silicon unnecessary on the silicon substrate and SiO
2, only stay the nanostructured of about 2 micron thickness;
With SiO
2Nanostructured is that mask carries out dry etching to the GaAs substrate, with the inductively coupled plasma etching, select when using Cl2/BCl3 as source of the gas specific energy reach＞10: 1, can make nanostructured reach nearly 20 microns with the mask of 2 micron thickness in the transfer degree of depth of InP substrate.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiments, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (4)
1, a kind of two-dimensional nanostructure deep etching method is characterized in that, comprises the steps:
S01, on substrate, apply photoresist, adopt electron beam exposure or other exposure technique on photoresist, to produce the photonic crystal nano graph;
S02, the photonic crystal nano graph is transferred on the substrate;
S03, after nano graph shifts, the photoresist of substrate surface is removed, adopt thermal oxidation technology will have the partial oxidation of nanostructured to generate SiO
2
S04, get an III-V family Semiconductor substrate to be etched, the surface that described substrate is had a nanostructured and III-V family Semiconductor substrate to be etched is relative, utilizes the on-plane surface bonding techniques, and two kinds of materials are bonding;
S05, employing reduction process extremely only stay the already oxidised SiO that is with substrate thinning
2Nanostructured.
2, two-dimensional nanostructure deep etching method as claimed in claim 1 is characterized in that, wherein substrate is silicon substrate or n type silicon substrate.
3, two-dimensional nanostructure deep etching method as claimed in claim 1 or 2 is characterized in that, among the wherein said step S02, the employing fluorine base gas is that the dry etching technology of source of the gas is transferred to silicon substrate with nano graph.
4, two-dimensional nanostructure deep etching method as claimed in claim 1 or 2 is characterized in that, among the wherein said step S02, adopts the galvanic corrosion technology that nano graph is transferred to n type silicon substrate.
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|---|---|---|---|
| CNB200610091006XA CN100570485C (en) | 2006-07-07 | 2006-07-07 | Two-dimensional nanostructure deep etching method |
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|---|---|---|---|
| CNB200610091006XA CN100570485C (en) | 2006-07-07 | 2006-07-07 | Two-dimensional nanostructure deep etching method |
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| CN101101445A true CN101101445A (en) | 2008-01-09 |
| CN100570485C CN100570485C (en) | 2009-12-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068541A (en) * | 2016-12-22 | 2017-08-18 | 天津三安光电有限公司 | A kind of processing method of epitaxy defect |
| CN114137660A (en) * | 2021-11-29 | 2022-03-04 | 中国科学院上海微系统与信息技术研究所 | Preparation method and structure of hybrid integrated light quantum chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0170253B1 (en) * | 1992-11-18 | 1999-03-20 | 김광호 | Method for etching using sylilation |
| US5374583A (en) * | 1994-05-24 | 1994-12-20 | United Microelectronic Corporation | Technology for local oxidation of silicon |
| US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
| US6309929B1 (en) * | 2000-09-22 | 2001-10-30 | Industrial Technology Research Institute And Genetal Semiconductor Of Taiwan, Ltd. | Method of forming trench MOS device and termination structure |
| US6559002B1 (en) * | 2001-12-31 | 2003-05-06 | Infineon Technologies North America Corp. | Rough oxide hard mask for DT surface area enhancement for DT DRAM |
| CN1252817C (en) * | 2002-06-05 | 2006-04-19 | 中国科学院物理研究所 | Single electron memory having carbon nano tube structure and process for making it |
| KR20050051652A (en) * | 2002-08-28 | 2005-06-01 | 유니버시티 오브 피츠버그 | Self-organized nanopore arrays with controlled symmetry and order |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068541A (en) * | 2016-12-22 | 2017-08-18 | 天津三安光电有限公司 | A kind of processing method of epitaxy defect |
| CN114137660A (en) * | 2021-11-29 | 2022-03-04 | 中国科学院上海微系统与信息技术研究所 | Preparation method and structure of hybrid integrated light quantum chip |
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