CN101097891A - Method of manufacturing a flash memory device - Google Patents
Method of manufacturing a flash memory device Download PDFInfo
- Publication number
- CN101097891A CN101097891A CNA200610156444XA CN200610156444A CN101097891A CN 101097891 A CN101097891 A CN 101097891A CN A200610156444X A CNA200610156444X A CN A200610156444XA CN 200610156444 A CN200610156444 A CN 200610156444A CN 101097891 A CN101097891 A CN 101097891A
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- China
- Prior art keywords
- dielectric layer
- under
- low dielectric
- seconds
- gate pattern
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a method of manufacturing a flash memory device. The method includes the steps of forming cell gate patterns and select transistor gate patterns on a semiconductor substrate; forming a low dielectric layer on the resultant structure; etching the low dielectric layer, leavinin gaps adjacent the cell gate patterns; and, forming a nitride layer spacer on one side wall of each of the select transistor gate patterns. The resulting flash memory device has an improved rate of change in the threshold voltage and reduces the contact resistance when a self-aligned contact method is subsequently performed.
Description
Technical field
The present invention relates to make the method for flash memory.
Background technology
Because flash memory becomes more highly integrated, thereby the distance between the gate pattern in the device cell zone becomes narrower.In live width 100nm or littler flash memory, between adjacent floating grid interference phenomenon takes place usually.Because this interference phenomenon, cause the threshold voltage of device to change and correspondingly reduce the reliability of device.The variations in threshold voltage rate is subjected to the influence of the distance between the gate pattern, the existence of the insulating material between gate pattern etc. to a great extent.
Summary of the invention
The invention solves foregoing problems.The purpose of this invention is to provide a kind of method of making flash memory, wherein the space between the gate pattern is filled with dielectric materials, so that the interference phenomenon that occurs between the gate pattern minimizes, improves the unit reliability thus.
The present invention relates to make the method for flash memory, and may further comprise the steps: on Semiconductor substrate, form cell gate pattern and select the transistor gate pattern, form the gate pattern structure thus; On resulting structures, form low dielectric layer; With the etching low dielectric layer, low dielectric layer only is retained in the gap adjacent with cell gate pattern.
Method of the present invention also is included in and forms the buffer oxide layer on the gate pattern structure.
Method of the present invention is implemented heat treatment process after also being included in and forming dielectric layer.
Method of the present invention is implemented ultraviolet processing procedure or solidification process after also being included in and forming low dielectric layer.
Method of the present invention is implemented ultraviolet processing procedure or solidification process after also being included in the etching low dielectric layer.
Method of the present invention is implemented heat treatment process and is implemented ultraviolet processing procedure or solidification process after also being included in and forming dielectric layer.
Method of the present invention also is included on the resulting structures that comprises residual low dielectric layer and forms nitride layer; With the nitride etching layer to form the nitride layer separator on the sidewall of selecting the transistor gate pattern at each.
Description of drawings
By the explanation of the following preferred embodiment that provides, above and other objects of the present invention, feature and advantage will become apparent in conjunction with the accompanying drawings.
Fig. 1-Fig. 4 is the sectional view that the method for making flash memory according to an embodiment of the invention is shown.
Embodiment
Below, preferred embodiments of the invention will be described with reference to the drawings.Yet, the invention is not restricted to following embodiment, and can come particular instantiation by various forms.To those skilled in the art, described embodiment is used for four corner of the present invention is provided support.
With reference to figure 1, order forms oxide skin(coating) 102, first polysilicon layer 103, dielectric layer 104, second polysilicon layer 105, conductive layer 106 and hard mask layer 107 on Semiconductor substrate 101.Form the gate pattern structure that comprises cell gate pattern 350A, 350B and selection transistor gate pattern 300A, 300B subsequently.Comprising formation buffer oxide layer 108 on the gained gate pattern structure of gate pattern 300A, 300B, 35 0A, 350B.Buffer oxide layer 108 strengthens the thickness that tetraethyl orthosilicate (PE-TEOS) formed and had 50 -150 by low pressure tetraethyl orthosilicate (LP-TEOS) or plasma.
With reference to figure 2, on the structure that obtains by Fig. 1, form low dielectric layer 109, described structure comprises buffer oxide layer 108 and gate pattern 300A, 300B, 350A, 350B.As shown in Figure 2, low dielectric layer 109 is filled the gap (for example gap gap gate pattern 350A, 350B between and gate pattern 350B, 300A between) adjacent with cell gate pattern 350A, 350B, but does not fill the gap of selecting between transistor gate pattern 300A, the 300B.In order to remove the moisture that comprises in the low dielectric layer 109, can implement heat treatment process.Also can implement ultraviolet (UV) processing procedure or solidification process to improve the quality of low dielectric layer 109.
In the present invention, utilize dielectric constant values for the fluorinated silicate glass of 3.2-3.6, dielectric constant values for organic aromatic polymer that about 3.5 hydrogen polysilazane (hydrogen polysilozane), hydrogen silsesquioxane (hydrogen silsesquioxane), dielectric constant values that dielectric constant values is 2.8-3.0 are about 2.7 methyl silsesquioxane, dielectric constant values is 2.8-3.0 organic silicate glass or dielectric constant values are 2.6-2.9, form low dielectric layer 109 by spin coating on the dielectric (SOD) deposition or by chemical vapor deposition (CVD).Low dielectric layer has the thickness of 500 -5000 .
In the present invention, implementing heat treatment process 30 seconds-300 seconds under the atmosphere of one arbitrarily under 100 ℃ of-150 ℃ of temperature, in air, argon gas (Ar) and helium (He).
In the present invention, under 300 ℃ of-400 ℃ of temperature, utilize 10mW/cm
2-20mW/cm
2The ultraviolet power supply, utilize the wafer of 50mm-200mm-lamp distance, under the pressure of 0.1Torr-0.5Torr, adopt 100 seconds-500 seconds processing time and adopt the inflow gas of 10cc/ minute-100cc/ minute flow to implement ultraviolet (UV) processing procedure.Inflow gas comprises nitrogen (N
2), oxygen (O
2) or its mixture.
In the present invention, under 300 ℃ of-500 ℃ of temperature, comprising water (H
2O) and oxygen (O
2) steam atmosphere under, processing time of adopting 30 minutes-120 minutes implements solidification process.
With reference to figure 3, utilize wet etching process etching low dielectric layer 109.Wet etching process removes to be present in selects all low dielectric layers 109 in the gap between transistor gate pattern 300A and the 300B.Wet etching process also removes the low dielectric layer 109 at gate pattern 300A, 300B, 350A, 350B top.Wet etching process forms residual low dielectric layer 109A, and it is retained in (for example gap between the gap between gate pattern 350A, the 350B and gate pattern 350B, the 300A) in the gap adjacent with cell gate pattern 350A, 350B.Because the wet etch rate in the close clearance adjacent with cell gate pattern 350A, 350B is lower than the wet etch rate in the big gap of selecting between transistor gate pattern 300A, the 300B, therefore residual low dielectric layer 109A only is retained in the above-mentioned specific region.Buffer oxide etch agent (BOE) can be used for wet etching process.On the resulting structures that comprises residual low dielectric layer 109A and buffering oxide skin(coating) 108, form nitride layer 110.Nitride layer 110 is formed and is had the thickness of 100 -500 by low-pressure chemical vapor deposition (LP-CVD).
In addition, can after etching low dielectric layer 109, implement ultraviolet processing procedure or solidification process for the second time to improve the quality of residual low dielectric layer 109A.The condition of ultraviolet processing procedure and solidification process is identical with aforementioned condition.
With reference to figure 4, nitride etching layer 110 to form nitride spacer 110S on the sidewall selecting transistor gate pattern 300A and 300B at each.When forming nitride spacer 110S, part nitride layer 110 is retained in the upside of cell gate pattern 350A and 350B.Nitride spacer 110S can be used in self-aligned contacts (SAC) method in the follow-up source/drain contact forming process.Usually, the separator that is used for the SAC method is by piling up two separators that oxide skin(coating) and nitride layer obtain.Yet in the present invention, because only adopt nitride spacer 110S, it is long-pending therefore to increase relative contact.Thereby, can reduce the rate of change of threshold voltage and contact resistance in the device.
As mentioned above, the present invention can improve because the variations in threshold voltage rate that the electrical effect between the cell gate pattern causes by with the adjacent gap of gate pattern in dielectric materials filling and the flash memory cells.
And, in the present invention, be used to use the formed separator of SAC method and be formed in single separator (that is not being two separators) on the sidewall that is used to select transistorized gate pattern.Therefore, contact area increases, thereby can reduce contact resistance.
Though specifically described technical spirit of the present invention in conjunction with preferred embodiment, scope of the present invention is not subjected to the restriction of particular, but should be made of claims.In addition, those skilled in the art should understand that and to carry out variations and modifications and not deviate from scope of the present invention the present invention.
Claims (21)
1. method of making flash memory may further comprise the steps:
(a) on Semiconductor substrate, form cell gate pattern and selection transistor gate pattern, form the gate pattern structure thus;
(b) on structure, form low dielectric layer by step (a) gained; With
(c) etching low dielectric layer only is retained in the gap adjacent with cell gate pattern low dielectric layer, forms residual low dielectric layer thus.
2. the process of claim 1 wherein that step (a) also is included in formation buffer oxide layer on the gate pattern structure.
3. the method for claim 2, wherein the buffer oxide layer strengthens the thickness that tetraethyl orthosilicate (PE-TEOS) formed and had 50 -150 by low pressure tetraethyl orthosilicate (LP-TEOS) or plasma.
4. the process of claim 1 wherein that low dielectric layer forms and have the thickness of 500 -5000 by spin-on deposition on the dielectric (SOD) or chemical vapor deposition (CVD).
5. the process of claim 1 wherein that low dielectric layer is formed by fluorinated silicate glass, hydrogen polysilazane, hydrogen silsesquioxane, methyl silsesquioxane, organic silicate glass or organic aromatic polymer.
6. the process of claim 1 wherein that step (b) also is included in the formation low dielectric layer and implements heat treatment process afterwards.
7. the method for claim 6, wherein heat treatment process under 100 ℃ of-150 ℃ of temperature, be selected under the atmosphere of air, argon gas (Ar) and helium (He) and implementing 30 seconds-150 seconds.
8. the process of claim 1 wherein that step (b) also is included in the formation low dielectric layer and implements ultraviolet processing procedure or solidification process afterwards.
9. the method for claim 8 comprises and implements the ultraviolet processing procedure, and its medium ultraviolet processing procedure is utilized 10mW/cm under 300 ℃ of-400 ℃ of temperature
2-20mW/cm
2The ultraviolet power supply, utilize the wafer of 50mm-200mm-lamp distance, under the pressure of 0.1Torr-0.5Torr, adopt 100 seconds-500 seconds processing time and adopt the inflow gas of 10cc/ minute-100cc/ minute flow to implement, inflow gas comprises nitrogen (N
2) and oxygen (O
2) at least a.
10. the method for claim 8 comprises the enforcement solidification process, wherein solidification process under 300 ℃ of-500 ℃ of temperature, comprising water (H
2O) and oxygen (O
2) steam atmosphere under, processing time of adopting 30 minutes-120 minutes implements.
Form after the residual low dielectric layer 11. the step of the process of claim 1 wherein (c) also is included in, implement ultraviolet processing procedure or solidification process.
12. the method for claim 11 comprises and implements the ultraviolet processing procedure that its medium ultraviolet processing procedure is utilized 10mW/cm under 300 ℃ of-400 ℃ of temperature
2-20mW/cm
2The ultraviolet power supply, utilize the wafer of 50mm-200mm-lamp distance, under the pressure of 0.1Torr-0.5Torr, adopt 100 seconds-500 seconds processing time and adopt the inflow gas of 10cc/ minute-100cc/ minute flow to implement, inflow gas comprises nitrogen (N
2) and oxygen (O
2) at least a.
13. the method for claim 11 comprises the enforcement solidification process, wherein solidification process under 300 ℃ of-500 ℃ of temperature, comprising water (H
2O) and oxygen (O
2) steam atmosphere under, processing time of adopting 30 minutes-120 minutes implements.
14. the process of claim 1 wherein that step (b) also comprises after forming dielectric layer:
Implement heat treatment process; With
Implement ultraviolet processing procedure or solidification process.
15. the method for claim 14, wherein heat treatment process under 100 ℃ of-150 ℃ of temperature, be selected under the atmosphere of air, argon gas (Ar) and helium (He) and implementing 30 seconds-150 seconds.
16. the method for claim 14 comprises and implements the ultraviolet processing procedure that its medium ultraviolet processing procedure is utilized 10mW/cm under 300 ℃ of-400 ℃ of temperature
2-20mW/cm
2The ultraviolet power supply, utilize the wafer of 50mm-200mm-lamp distance, under the pressure of 0.1Torr-0.5Torr, adopt 100 seconds-500 seconds processing time and adopt the inflow gas of 10cc/ minute-100cc/ minute flow to implement, inflow gas comprises nitrogen (N
2) and oxygen (O
2) at least a.
17. the method for claim 14 comprises the enforcement solidification process, wherein solidification process under 300 ℃ of-500 ℃ of temperature, comprising water (H
2O) and oxygen (O
2) steam atmosphere under, processing time of adopting 30 minutes-120 minutes implements.
18. the process of claim 1 wherein and utilize wet etching process to come the etching low dielectric layer.
19. the method for claim 18, wherein wet etching process uses buffer oxide etch agent (BOE) solution.
20. the method for claim 1 is further comprising the steps of:
(d) on the structure that comprises residual low dielectric layer that obtains by step (c), form nitride layer; With
(e) nitride etching layer to form the nitride layer separator on the sidewall selecting the transistor gate pattern at each.
21. the method for claim 20, wherein nitride layer is formed and is had the thickness of 100 -500 by low-pressure chemical vapor deposition (LP-CVD).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060060500 | 2006-06-30 | ||
| KR20060060500 | 2006-06-30 | ||
| KR1020060113185 | 2006-11-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101097891A true CN101097891A (en) | 2008-01-02 |
| CN100527388C CN100527388C (en) | 2009-08-12 |
Family
ID=39011568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610156444XA Expired - Fee Related CN100527388C (en) | 2006-06-30 | 2006-12-31 | Method of manufacturing a flash memory device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20080003171A (en) |
| CN (1) | CN100527388C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100079960A (en) | 2008-12-31 | 2010-07-08 | 삼성전자주식회사 | Method for formation of flash memory |
| KR101019711B1 (en) * | 2009-04-14 | 2011-03-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR20110061329A (en) | 2009-12-01 | 2011-06-09 | 삼성전자주식회사 | Semiconductor device |
-
2006
- 2006-11-16 KR KR1020060113185A patent/KR20080003171A/en not_active Application Discontinuation
- 2006-12-31 CN CNB200610156444XA patent/CN100527388C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN100527388C (en) | 2009-08-12 |
| KR20080003171A (en) | 2008-01-07 |
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Granted publication date: 20090812 Termination date: 20131231 |