CN101097562A - Device for breaking through nonvolatile semiconductor memory member speed bottle-neck - Google Patents
Device for breaking through nonvolatile semiconductor memory member speed bottle-neck Download PDFInfo
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- CN101097562A CN101097562A CNA2006100360924A CN200610036092A CN101097562A CN 101097562 A CN101097562 A CN 101097562A CN A2006100360924 A CNA2006100360924 A CN A2006100360924A CN 200610036092 A CN200610036092 A CN 200610036092A CN 101097562 A CN101097562 A CN 101097562A
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Abstract
A kind of device to breach the speed bottleneck of non-volatile memory is disclosed, which includes buffering device, instruction bus and the access bus of non-volatile memory; the buffering device is mounted between the CPU the non-volatile memory, the buffering device and microprocessor CPU are connected by instruction bus, the buffering device and the non-volatile memory are connected by the access bus of non-volatile memory to expand the bit width of access bus of non-volatile memory connected with buffering device; the instruction bus includes state bus, information bus of instruction address and instruction code bus; the access bus of non-volatile memory includes address bus of non-volatile memory and data bus of non-volatile memory; the buffering device includes buffering controller and buffering unit, and the buffering unit can be controlled by buffering controller via control bus.
Description
Technical field
The present invention relates to integrated circuit (IC, Integrated Chip) design field, be specifically related to a kind of device of breaking through nonvolatile semiconductor memory member speed bottle-neck.
Background technology
Along with the development of semiconductor technology, the time-delay of logical device is more and more littler, thereby the travelling speed of the functional unit that microprocessor CPU etc. are made up of logical circuit can be more and more faster; Some nonvolatile semiconductor memory members are not made up of logical device as unit such as Flash or EEPROM, and its access speed but can not promote synchronously.Existing technology status is that most of SOC (system on a chip) SOC (System On Chip) chip all needs to use nonvolatile memory and stores run time version or data, like this problem that the nonvolatile semiconductor memory member access speed can't be mated the travelling speed of microprocessor will appear, owing to the access speed of the permission of nonvolatile semiconductor memory member causes the processing power of microprocessor core and entire chip to improve synchronously along with the development of technology too slowly.
Existing solution at this problem is to adopt the CACHE caching technology, promptly some data in advance that will use expection in the nonvolatile semiconductor memory member earlier by the mode of looking ahead take out and leave in some high speed random access memory parts (RAM), are come to eliminate the bottleneck that the nonvolatile semiconductor memory member visit brings by visiting this high speed random access memory part by microprocessor unit then.The shortcoming of prior art is that the later working mechanism of introducing CACHE is very complicated, the realization circuit scale is huge, generally be used among the labyrinth SOC (system on a chip) SOC (System On Chip) of (as based on 32 bit CPUs nuclear), not too be fit to the simple structure SOC (system on a chip) of (as based on 8 bit CPUs nuclear).All have CACHE as the present Pentium CPU of many 32 chip systems such as Intel, and all do not possess the CACHE buffer based on 8 or the intelligent card chip system of 16 bit CPUs nuclear such as the SLE66 series of Infineon, AT90 series of ATMEL or the like.These intelligent card chips generally all can only operate in the 20MHz; Perhaps adopt the MCU in multiple instruction cycle to examine and realize higher dominant frequency, but the true processing power of its microprocessor unit can not be complementary with dominant frequency.
Summary of the invention
At above problem, the invention provides a kind of device of breaking through nonvolatile semiconductor memory member speed bottle-neck, introduce the speed bottle-neck that embedded non-volatile memory spare (as embedded Flash) brings to overcome, avoid adopting this class complex technology of traditional C ACHE buffer simultaneously.
Problem to be solved by this invention can solve by the following technical programs:
The present invention solves owing to introduce the speed bottle-neck that nonvolatile semiconductor memory member causes by a kind of device of breaking through nonvolatile semiconductor memory member speed bottle-neck.
Nonvolatile semiconductor memory member access bus bandwidth depends on: access bus frequency * access bus bit wide, and the reading command bandwidth of microprocessor CPU depends on: instruction frequency * instruction bit wide; When if microprocessor CPU instructs frequency much larger than nonvolatile semiconductor memory member access bus frequency, can be under the situation that does not change access bus frequency, instruction frequency and instruction bit wide, only improve nonvolatile semiconductor memory member access bus bandwidth, thereby can reach the purpose of the instruction bandwidth of coupling microprocessor CPU by improving nonvolatile semiconductor memory member access bus bit wide.
Expand nonvolatile semiconductor memory member access bus bit wide earlier, making this bit wide is the several times (for example 4 times) of the access bus bit wide of actual use, design the device of a corresponding breaking through nonvolatile semiconductor memory member speed bottle-neck again, feasible once visiting of nonvolatile semiconductor memory member to this high-bit width can access and store the instruction and data information that is several times as much as current microprocessor CPU actual needs; The instruction and data information of these storages can satisfy the needs of instruction and data of the CPU that runs up in current and subsequent instructions cycle, and data information stored can be used as instruction code and the data message in follow-up a plurality of microprocessor CPU instruction cycle; Promptly the data that microprocessor CPU instruction cycle visit nonvolatile semiconductor memory member obtains can be moved a plurality of instruction cycles for CPU.So just directly broken through nonvolatile semiconductor memory member access bus bandwidth constraints, thereby the performance of entire chip is increased dramatically.
A kind of device of breaking through nonvolatile semiconductor memory member speed bottle-neck comprises snubber assembly, instruction bus and nonvolatile semiconductor memory member access bus; Wherein snubber assembly is between microprocessor CPU and the nonvolatile semiconductor memory member, instruction bus connects snubber assembly and microprocessor CPU, the nonvolatile semiconductor memory member access bus connects snubber assembly and nonvolatile semiconductor memory member, the bit wide of the nonvolatile semiconductor memory member access bus that expansion is connected with snubber assembly.
For microprocessor CPU, its operational efficiency depends on frequency of operation, when the frequency of operation of microprocessor CPU improves, and the also corresponding raising of the frequency of operation of its instruction bus; And for nonvolatile semiconductor memory member, owing to be subject to physical characteristics, there is the upper limit in the frequency of operation of its nonvolatile semiconductor memory member access bus, and for example the frequency of operation of Flash is generally about 10MHz, far below the needed access frequency of microprocessor CPU instruction bus under the current technology.And after the bit wide by expansion nonvolatile semiconductor memory member access bus, the bandwidth of nonvolatile semiconductor memory member access bus also improves thereupon, thereby it is suitable to reach the and instruction bus width.
Snubber assembly between instruction bus and nonvolatile semiconductor memory member access bus, its major function is with the obtained metadata cache of the each visit of nonvolatile semiconductor memory member access bus, use for instruction bus, thereby realize the data access and the exchange of two suitable buses of bandwidth.
Instruction bus comprises status bus, instruction address bus and instruction code bus; The nonvolatile semiconductor memory member access bus comprises nonvolatile semiconductor memory member address bus and nonvolatile semiconductor memory member data bus; Snubber assembly comprises buffer control unit and buffering unit, and wherein buffer control unit is controlled buffer cell by control bus.
The core of snubber assembly is a buffer control unit, and its groundwork process comprises course of normal operation, the course of work of processing microprocessor CPU jump instruction, the processing microprocessor CPU visits the too fast course of work and the processing microprocessor CPU was visited the slow course of work.
The course of normal operation of buffer control unit is: buffer control unit will export nonvolatile semiconductor memory member to by the nonvolatile semiconductor memory member address bus according to the instruction access address of the prediction of the address information on microprocessor CPU instruction address bus microprocessor CPU; Nonvolatile semiconductor memory member will return corresponding data according to the nonvolatile semiconductor memory member address bus, deliver to buffer unit by the nonvolatile semiconductor memory member data bus; Buffer unit will be selected the data sent here on the buffer memory nonvolatile semiconductor memory member data bus according to the control bus of buffer control unit; Cache controller is selected corresponding data simultaneously according to the address information on the instruction address bus from buffer unit, and returns to microprocessor CPU by the instruction code bus.
The course of work that buffer control unit is handled the microprocessor CPU jump instruction is: when buffer control unit detected the jump instruction of microprocessor CPU by the command information on the cpu instruction address information bus, it carried out the invalid operation of data in the buffer unit.
Buffer control unit is handled the too fast course of work of microprocessor CPU visit: when buffer control unit detects buffer unit for empty, mean that the microprocessor CPU visit is too fast, then buffer control unit is returned to microprocessor CPU with current state by status bus, makes microprocessor CPU stop visit to wait for that data are effective in the buffer unit.
Buffer control unit processing microprocessor CPU was visited the slow course of work and is: when buffer control unit detects buffer unit for full, mean microprocessor CPU visited slow, then buffer control unit will stop to visit nonvolatile semiconductor memory member in buffer unit, have clearance spaces continue again the visit.
Simultaneously,, can also set up the buffer unit of two nonvolatile semiconductor memory members, realize that table tennis switches in order to improve the speed bottle-neck of nonvolatile semiconductor memory member better.
Compared with prior art, solved the speed bottle-neck that embedded non-volatile memory spares such as introducing Flash brings; Compare the complexity that greatly reduces circuit with traditional C ACHE solution, avoided realizing the complex mechanism of CACHE.The present invention is particularly suitable for the simple chip system, especially is fit to the chip system based on 8 or 16 single command cycle CPU nuclears, can operate in 60MHz even higher based on its frequency of operation of chip system of the present invention.
Description of drawings
Fig. 1 is the overall plan synoptic diagram that installs among the present invention;
Fig. 2 is the detailed protocol synoptic diagram that installs among the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Nonvolatile semiconductor memory member access bus bandwidth depends on: access bus frequency * access bus bit wide, and the reading command bandwidth of microprocessor CPU depends on: instruction frequency * instruction bit wide; When if microprocessor CPU instructs frequency much larger than nonvolatile semiconductor memory member access bus frequency, can be under the situation that does not change access bus frequency, instruction frequency and instruction bit wide, only improve nonvolatile semiconductor memory member access bus bandwidth, thereby can reach the purpose of the instruction bandwidth of coupling microprocessor CPU by improving nonvolatile semiconductor memory member access bus bit wide.
Expand nonvolatile semiconductor memory member access bus bit wide earlier, making this bit wide is the several times (for example 4 times) of the access bus bit wide of actual use, design the device of a corresponding breaking through nonvolatile semiconductor memory member speed bottle-neck again, feasible once visiting of nonvolatile semiconductor memory member to this high-bit width can access and store the instruction and data information that is several times as much as current microprocessor CPU actual needs; The instruction and data information of these storages can satisfy the needs of instruction and data of the CPU that runs up in current and subsequent instructions cycle, and data information stored can be used as instruction code and the data message in follow-up a plurality of microprocessor CPU instruction cycle; Promptly the data that microprocessor CPU instruction cycle visit nonvolatile semiconductor memory member obtains can be moved a plurality of instruction cycles for CPU.So just directly broken through nonvolatile semiconductor memory member access bus bandwidth constraints, thereby the performance of entire chip is increased dramatically.
As shown in Figure 1, the device of a kind of breaking through nonvolatile semiconductor memory member speed bottle-neck provided by the present invention comprises snubber assembly 103, instruction bus 102 and nonvolatile semiconductor memory member access bus 104; Wherein snubber assembly 103 is between high speed device microprocessor CPU 101 and the nonvolatile semiconductor memory member 105, instruction bus 102 connects snubber assembly 103 and microprocessor CPU 101, and nonvolatile semiconductor memory member access bus 104 connects snubber assembly 103 and nonvolatile semiconductor memory member 105.The bit wide of the nonvolatile semiconductor memory member access bus 104 that expansion is connected with buffer storage.
For microprocessor CPU 101, its operational efficiency depends on frequency of operation, when the frequency of operation of microprocessor CPU 101 improves, and the also corresponding raising of the frequency of operation of its instruction bus 102; And for nonvolatile semiconductor memory member 105, owing to be subject to physical characteristics, there is the upper limit in the frequency of operation of its nonvolatile semiconductor memory member access bus 104, for example the frequency of operation of Flash is generally about 10MHz, far below the 102 needed access frequencys of the microprocessor CPU instruction bus under the current technology.And after the bit wide of access bus by expansion nonvolatile semiconductor memory member 105, the bandwidth of nonvolatile semiconductor memory member access bus 104 also improves thereupon, thereby the bandwidth that can reach and instruction bus 102 is suitable.
Snubber assembly 103 between instruction bus 102 and nonvolatile semiconductor memory member access bus 104, its major function is with the obtained metadata cache of nonvolatile semiconductor memory member access bus 104 each visits, use for instruction bus 102, thereby realize the data access and the exchange of two suitable buses of bandwidth.
The composition of instruction bus 102, nonvolatile semiconductor memory member access bus 104 and snubber assembly 103 as shown in Figure 2.Wherein instruction bus 102 comprises status bus 201, instruction address bus 202 and instruction code bus 203; Nonvolatile semiconductor memory member access bus 104 comprises nonvolatile semiconductor memory member address bus 207 and nonvolatile semiconductor memory member data bus 208; Snubber assembly 103 comprises buffer control unit 204 and buffering unit 206, and wherein buffer control unit 204 is controlled buffer cell 206 by control bus 205.
The core of snubber assembly 103 is buffer control units 204, and its groundwork process comprises course of normal operation, the course of work of processing microprocessor CPU 101 jump instructions, processing microprocessor CPU 101 visits the too fast course of work and processing microprocessor CPU 101 was visited the slow course of work.
The course of normal operation of buffer control unit 204 is: buffer control unit 204 will export nonvolatile semiconductor memory member 105 to by nonvolatile semiconductor memory member address bus 207 according to the instruction access address of the prediction of the address information on the microprocessor CPU instruction address bus 202 microprocessor CPU 101; Nonvolatile semiconductor memory member 105 will return corresponding data according to nonvolatile semiconductor memory member address bus 207, deliver to buffer unit 206 by nonvolatile semiconductor memory member data bus 208; Buffer unit 206 will be selected the data sent here on the buffer memory nonvolatile semiconductor memory member data bus 208 according to the control bus 205 of buffer control unit 204; Cache controller 204 is selected corresponding data simultaneously according to the address information on the instruction address bus 202 from buffer unit 206, and returns to microprocessor CPU 101 by instruction code bus 203.
The course of work that buffer control unit 204 is handled microprocessor CPU 101 jump instructions is: when buffer control unit 204 detected the jump instruction of microprocessor CPU 101 by the command information on the cpu instruction address information bus 202, it carried out the invalid operation of data in the buffer unit 206.
Buffer control unit 204 is handled the too fast course of work of microprocessor CPU 101 visits: when buffer control unit 204 detects buffer unit 206 for empty, mean that microprocessor CPU 101 visits are too fast, then buffer control unit 204 is returned to microprocessor CPU 101 with current state by status bus 201, makes microprocessor CPU 101 stop visit to wait for that data are effective in the buffer unit 206.
Buffer control unit 204 processing microprocessor CPUs 101 were visited the slow course of work and are: when buffer control unit 204 detects buffer unit 206 for full, mean microprocessor CPU 101 visited slow, then buffer control unit 204 will stop to visit nonvolatile semiconductor memory member 105 in buffer unit 206, have clearance spaces continue again the visit.
In addition,, can also set up the buffer unit of two nonvolatile semiconductor memory members, realize that table tennis switches in order to improve the speed bottle-neck of nonvolatile semiconductor memory member better.
Claims (8)
1. the device of a breaking through nonvolatile semiconductor memory member speed bottle-neck, it is characterized in that: described device comprises snubber assembly, instruction bus and nonvolatile semiconductor memory member access bus; Wherein snubber assembly is between microprocessor CPU and the nonvolatile semiconductor memory member, and instruction bus connects snubber assembly and microprocessor CPU, and the nonvolatile semiconductor memory member access bus connects snubber assembly and nonvolatile semiconductor memory member.
2. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 1 is characterized in that: the bit wide of the nonvolatile semiconductor memory member access bus that expansion is connected with buffer storage.
3. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 1, it is characterized in that: described instruction bus comprises status bus, instruction address bus and instruction code bus; Described nonvolatile semiconductor memory member access bus comprises nonvolatile semiconductor memory member address bus and nonvolatile semiconductor memory member data bus; Described snubber assembly comprises buffer control unit and buffering unit, and wherein buffer control unit is controlled buffer cell by control bus.
4. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 3, it is characterized in that: described snubber assembly is all realized once once visit to non-volatile device according to the request of access each time of microprocessor CPU, and can both obtain and store the data message that is several times as much as current actual needs at the visit of non-volatile device each time, these information can be moved a plurality of instruction cycles for microprocessor CPU.
5. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 3, it is characterized in that: described buffer control unit, in course of normal operation, will export nonvolatile semiconductor memory member to by the nonvolatile semiconductor memory member address bus according to the instruction access address of microprocessor CPU instruction address bus prediction microprocessor CPU; Nonvolatile semiconductor memory member will return corresponding data according to the nonvolatile semiconductor memory member address bus, deliver to buffer unit by the nonvolatile semiconductor memory member data bus; Buffer unit will be selected the data sent here on the buffer memory nonvolatile semiconductor memory member data bus according to the control bus of buffer control unit; Cache controller is simultaneously according to the information of instruction address bus, from buffer unit) the corresponding data of selection, and return to microprocessor CPU by the instruction code bus.
6. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 3, it is characterized in that: when described buffer control unit detects the jump instruction of the microprocessor CPU that the instruction address bus transmits when it, carry out the data invalidation in the buffer unit.
7. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 3, it is characterized in that: described buffer control unit is carried out buffer unit for empty when it detects, mean that promptly the microprocessor CPU visit is too fast, return to microprocessor CPU with its current state by status bus by cache controller this moment, and microprocessor CPU will stop visit to wait for that data are effective in the buffer unit this moment.
8. the device of breaking through nonvolatile semiconductor memory member speed bottle-neck as claimed in claim 3, it is characterized in that: described buffer control unit is carried out buffer unit for full when it detects, promptly mean microprocessor CPU visited slow, this moment cache controller will stop to visit nonvolatile semiconductor memory member in buffer unit, have clearance spaces continue again the visit.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006100360924A CN101097562A (en) | 2006-06-27 | 2006-06-27 | Device for breaking through nonvolatile semiconductor memory member speed bottle-neck |
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| CNA2006100360924A CN101097562A (en) | 2006-06-27 | 2006-06-27 | Device for breaking through nonvolatile semiconductor memory member speed bottle-neck |
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| CN101097562A true CN101097562A (en) | 2008-01-02 |
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| CNA2006100360924A Pending CN101097562A (en) | 2006-06-27 | 2006-06-27 | Device for breaking through nonvolatile semiconductor memory member speed bottle-neck |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834483A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Implementing method for improving property of embedded MCU (microprogrammed control unit) |
| CN105138481A (en) * | 2014-05-30 | 2015-12-09 | 华为技术有限公司 | Stored data processing method and apparatus and system |
| CN106155926A (en) * | 2015-04-09 | 2016-11-23 | 澜起科技（上海）有限公司 | Memorizer and the data interactive method of memorizer |
| CN108399146A (en) * | 2018-02-26 | 2018-08-14 | 上海东软载波微电子有限公司 | Flash controllers, instruction fetch method and computer readable storage medium |
| CN114281570A (en) * | 2021-12-23 | 2022-04-05 | 合肥市芯海电子科技有限公司 | Embedded control circuit, control method, device and chip |
-
2006
- 2006-06-27 CN CNA2006100360924A patent/CN101097562A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105138481A (en) * | 2014-05-30 | 2015-12-09 | 华为技术有限公司 | Stored data processing method and apparatus and system |
| CN105138481B (en) * | 2014-05-30 | 2018-03-27 | 华为技术有限公司 | Processing method, the device and system of data storage |
| CN106155926A (en) * | 2015-04-09 | 2016-11-23 | 澜起科技（上海）有限公司 | Memorizer and the data interactive method of memorizer |
| CN106155926B (en) * | 2015-04-09 | 2019-11-26 | 澜起科技股份有限公司 | The data interactive method of memory and memory |
| CN104834483A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Implementing method for improving property of embedded MCU (microprogrammed control unit) |
| CN104834483B (en) * | 2015-05-11 | 2018-02-27 | 江苏宏云技术有限公司 | A kind of implementation method for lifting embedded MCU performance |
| CN108399146A (en) * | 2018-02-26 | 2018-08-14 | 上海东软载波微电子有限公司 | Flash controllers, instruction fetch method and computer readable storage medium |
| CN108399146B (en) * | 2018-02-26 | 2021-11-23 | 上海东软载波微电子有限公司 | Flash controller, instruction fetching method and computer readable storage medium |
| CN114281570A (en) * | 2021-12-23 | 2022-04-05 | 合肥市芯海电子科技有限公司 | Embedded control circuit, control method, device and chip |
| WO2023116093A1 (en) * | 2021-12-23 | 2023-06-29 | 合肥市芯海电子科技有限公司 | Embedded control circuit, control method and apparatus, and chip |
| CN114281570B (en) * | 2021-12-23 | 2024-05-03 | 合肥市芯海电子科技有限公司 | Embedded control circuit, control method, device and chip |
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