CN101087177B - Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals - Google Patents
Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals Download PDFInfo
- Publication number
- CN101087177B CN101087177B CN2007100353111A CN200710035311A CN101087177B CN 101087177 B CN101087177 B CN 101087177B CN 2007100353111 A CN2007100353111 A CN 2007100353111A CN 200710035311 A CN200710035311 A CN 200710035311A CN 101087177 B CN101087177 B CN 101087177B
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- frequency deviation
- transmission
- situation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a concourse transmission method for multi-path E1 data with offset frequency in SDH signal, and the steps are: (1) builds first-in first-out buffer corresponding with every E1 signal, and judges the offset frequency of E1 signal according to the number and changing situation of stored data in every buffer; (2) builds the concourse processing module; processes the data transmission in concourse module according to the offset frequency situation in step (1) between the E1 signal and the transmission clock; (3) processes the data transmission in concourse module accordingto the offset frequency situation in step (1) between the E1 signals. The invention provides that it can solve the concourse problems of multi-path E1 signals with offset frequency and the concourse transmission method in multi-path E1 data with offset frequency according to the offset frequency of E1 signal to self-adaptive SDH signal STM 1.
Description
Technical field
The present invention is mainly concerned with optical fiber communication signal processing field, refers in particular to the convergence transmission method that has the multi-channel E 1 data of frequency deviation in a kind of SDH signal.
Background technology
Can carry 63 road E1 signals in the SDH signal of TUG structure STM-1, these E1 signals are by advancing in the SDH frame of STM-1 from the signal map of different PDH equipment, and these PDH equipment may adopt the different clocks system.From the SDH signal of TUG structure STM-1, tell the E1 signal and must pass through a two-level pointer adjustment and a bit adjustment, may there be frequency departure between these E1 signals and between E1 signal and transmission or the receive clock, to converge this each E1 signal of frequency deviation that exists, at first need to set up a kind of transformat that can receive this frequency deviation, solve the convergence method that adapts to this transformat then.
In some application at SDH signal processing, need to understand the type and the feature of each road E1 time slot data, as speech channel data, IP bag data and ATM cell data with TUG structure STM-1.When sending to follow-up respective handling module, just need carry out convergence processing to treated these E1 time slot data to these E1 time slot data through the discriminator processing from different E1 equipment if adopt same data channel to send data.In the convergence processing process, should guarantee that original E1 signal can normally transmit, guarantee some time slot characteristic signal energy synchronous transmission that processing obtains through discriminator again, make the subsequent treatment module from unified interface signal, to receive own required signal like this according to own needs.
Summary of the invention
The problem to be solved in the present invention just is: at the technical problem of prior art existence, the invention provides a kind of problem that converges that can solve the multi-channel E 1 signal that has frequency deviation, can make the convergence transmission method that has the multi-channel E 1 data of frequency deviation among the SDH signal STM-1 of self adaptation adjustment according to the E1 signal frequency deviation.
In order to solve the problems of the technologies described above, the solution that the present invention proposes is: have the convergence transmission method of the multi-channel E 1 data of frequency deviation in a kind of SDH signal, it is characterized in that step is:
(1), sets up a first in first out buffer corresponding for each E1 signal, for the number of storage data in each buffer and the offset frequency situation of variation speed situation judgement E1 signal with it.
(2), set up the convergence processing module; According to offset frequency situation between determined each E1 signal and the transfer clock in the step (1), in the convergence processing module, the transmission data procedures is handled accordingly:
1. when not having frequency deviation between each E1 signal and the transfer clock, only adopt main span line transmission data, the clock number is fixed as 2430 in the transmission cycle;
2. when having positive frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that reduces in the transmission cycle and the quantity that increases fast transmission cycle to adapt to this offset frequency situation;
3. when having negative frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that increases in the transmission cycle and the quantity that increases slow transmission cycle to adapt to the situation of this frequency deviation;
(3), according to offset frequency situation between determined each E1 signal in the step (1), in the convergence processing module, the transmission data procedures is handled accordingly:
1. when not having frequency deviation between each E1 signal, only adopt main span line transmission data;
2. when having less frequency deviation between each E1 signal, can adopt main span line and adapt in conjunction with the method for additional transmitted section for the part that has positive frequency deviation E1 signal; Can adopt the method for main span line and binding data useful signal to adapt to for the part that has negative frequency deviation E1 signal; For the situation that positive frequency deviation and negative frequency deviation all exist, then use multiple means such as main span line, additional transmitted section and data useful signal to adapt to respectively;
3. the frequency deviation of working as between most of E1 signal is very little, have only when having bigger positive frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less positive frequency deviation, just for there being the bigger that part of E1 signal of positive frequency deviation, it is frequent that utilization additional transmitted section is transmitted the meeting of the data that accumulate in its buffer;
4. between the E1 signal of minority E1 signal and remainder, there is bigger negative frequency deviation, have only when having bigger negative frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less negative frequency deviation, just for there being the bigger that part of E1 signal of negative frequency deviation, the maintenance data useful signal indicates its meeting of invalid time frequent.
(4), according to the number of storage data in each E1 signal corresponding cache device be provided with several judging points (A B C D): A point is arranged on the buffer degree of depth 1/16 place for stopping data transmissions judging point; The B point is arranged on the buffer degree of depth 1/4 place for the beginning or the data transmission judging point that slows down; The C point is arranged on the buffer degree of depth 1/2 place for normal data sends judging point; The D point sends judging point for accelerating data, is arranged on the buffer degree of depth 3/4 place.
(5), be:, as follows to the judgement of the number of storage data in each E1 signal corresponding cache device and situation of change thereof according to the judging point in the step (4) to the discriminating step of E1 signal frequency deviation situation described in the step (1):
1. difference keeps being not more than 10 between the number of storage data in each E1 signal corresponding cache device, just can judge that the frequency deviation difference between these E1 signals is less; Otherwise just judge that the frequency deviation difference between these E1 signals is bigger;
2. the number of storage data just can judge that less than B judging point number there is negative frequency deviation in its corresponding E1 signal in certain E1 signal corresponding cache device, and the transmission data speed need slow down; Otherwise that just judges this E1 signal does not exist negative frequency deviation;
3. the number of storage data just can judge that greater than D judging point number there is positive frequency deviation in its corresponding E1 signal in certain E1 signal corresponding cache device, needs to accelerate to send data speed; Otherwise that just judges this E1 signal does not exist positive frequency deviation;
4. be in when slowing down state when sending data speed,, judge then that its corresponding E1 signal has returned to not need to slow down to send the state of data speed again if the number of storage data has reached greater than C judging point number in certain E1 signal corresponding cache device;
5. when the transmission data speed is in the quickening state,, judge that then its corresponding E1 signal has returned to the state that does not need to accelerate again to send data speed if the number of storage data has been less than C judging point number in certain E1 signal corresponding cache device;
6. in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is big by 64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is positive frequency deviation;
7. in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is little by-64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is negative frequency deviation;
8. the number of storage data is smaller or equal to 32 (stop data and send judging point A) in the first in first out buffer of certain E1 correspondence, and can judge that the SDH signal of STM-1 does not carry this E1 signal this moment, and this E1 signal is invalid E1 signal, does not participate in above-mentioned judgement; Otherwise this E1 signal is effective E1 signal, participates in above-mentioned judgement.
All E1 time slot data in the SDH signal of described STM-1 and corresponding characteristic thereof adopt the validity of same data useful signal designation data, the indication of same header signal they are in position, a same clock in the transmission frame and take/beat in, and the syllogic transmission means that adopts main span line, additional transmitted section and wait for span line adapts between the SDH signal frame of STM-1 and each E1 signal and the transfer clock or the offset frequency situation between each E1 signal
Compared with prior art, advantage of the present invention just is:
(1) this transmission method frame by frame mode transmit corresponding with the frame transmission means of the SDH signal of STM-1, easy to understand, processing and Project Realization.
(2) have the adjustment mode of multiple adaptation frequency deviation, can adjust in the SDH signal of STM-1 between each E1 signal and the multiple offset frequency situation that exists between E1 signal and the transfer clock.
(3) can adjust the clock number in each transmission frame and the quantity of speed transmission frame according to the frequency deviation of E1 signal.
(4) in each transmission frame, adopt transmission segment processing mode.Can utilize the cooperation of main span line, additional transmitted section and data useful signal can adapt to the multiple offset frequency situation that exists between each E1 signal in the SDH signal of STM-1.
(5) in main span line and additional transmitted section, utilize the position (or sequential) of transmission corresponding one by one with the numbering of time slot data in the SDH of STM-1 signal.
(6) for the relation of position number and STM-1 time slot data number, similar in main span line and in the additional transmitted section sending or receiving terminal can adopt the same treatment module of giving different initial values to handle, and can simplify it and realize difficulty.
(7) data-signal and characteristic signal transmitting terminal in transmission course adopts Synchronous Transfer Mode, but receiving terminal can separately receive and handle; Has bigger flexibility.
Adopt pointer adjustment and justification to adapt to the various offset frequency situation of E1 signal in the SDH system, it has carried corresponding Overhead in transmission course simultaneously.Method such as the clock number by transmitting every frame, speed transmission frame number, segment transmissions mode adapts to the various offset frequency situation of E1 signal in the present invention, but it is synchronous transmission and E1 signal characteristic of correspondence data simultaneously, and have abandoned some Overhead in the SDH system.
Description of drawings
Fig. 1 is the sequential schematic diagram of data transmission interface signal;
Fig. 2 is a transmitting terminal data transmission and processing schematic flow sheet;
First in first out buffer judging point was provided with schematic diagram when Fig. 3 was the E1 signal gathering;
When being the E1 signal gathering, Fig. 4 judges buffer store status schematic diagram;
Fig. 5 receives data module example block diagram.
Embodiment
Below with reference to the drawings and specific embodiments the present invention is described in further details.
There is the convergence transmission method of the multi-channel E 1 data of frequency deviation in a kind of SDH signal of the present invention, the steps include:
(1), sets up a first in first out buffer corresponding for each E1 signal, for the number of storage data in each buffer and the offset frequency situation of variation speed situation judgement E1 signal with it;
(2), set up the convergence processing module; According to offset frequency situation classification between determined each E1 signal and the transfer clock in the step (1), in the convergence processing module, buffer is handled accordingly:
1. when not having frequency deviation between each E1 signal and the transfer clock, only adopt main span line transmission data, the clock number is fixed as 2430 in the transmission cycle;
2. when having positive frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that reduces in the transmission cycle and the quantity that increases fast transmission cycle to adapt to this offset frequency situation;
3. when having negative frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that increases in the transmission cycle and the quantity that increases slow transmission cycle to adapt to the situation of this frequency deviation;
(3), according to offset frequency situation between determined each E1 signal in the step (1), in the convergence processing module, the transmission data procedures is handled accordingly:
1. when not having frequency deviation between each E1 signal, only adopt main span line transmission data;
2. when having less frequency deviation between each E1 signal, can adopt main span line and adapt in conjunction with the method for additional transmitted section for the part that has positive frequency deviation E1 signal; Can adopt the method for main span line and binding data useful signal to adapt to for the part that has negative frequency deviation E1 signal; For the situation that positive frequency deviation and negative frequency deviation all exist, then use multiple means such as main span line, additional transmitted section and data useful signal to adapt to respectively;
3. the frequency deviation of working as between most of E1 signal is very little, have only when having bigger positive frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less positive frequency deviation, just for there being the bigger that part of E1 signal of positive frequency deviation, it is frequent that utilization additional transmitted section is transmitted the meeting of the data that accumulate in its buffer;
4. between the E1 signal of minority E1 signal and remainder, there is bigger negative frequency deviation, have only when having bigger negative frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less negative frequency deviation, just for there being the bigger that part of E1 signal of negative frequency deviation, the maintenance data useful signal indicates its meeting of invalid time frequent.
(4), according to the number of storage data in each E1 signal corresponding cache device be provided with several judging points (A B C D): A point is arranged on the buffer degree of depth 1/16 place for stopping data transmissions judging point; The B point is arranged on the buffer degree of depth 1/4 place for the beginning or the data transmission judging point that slows down; The C point is arranged on the buffer degree of depth 1/2 place for normal data sends judging point; The D point sends judging point for accelerating data, is arranged on the buffer degree of depth 3/4 place.
(5), be:, as follows to the judgement of the number of storage data in each E1 signal corresponding cache device and situation of change thereof according to the judging point in the step (4) to the discriminating step of E1 signal frequency deviation situation described in the step (1):
1. difference keeps being not more than 10 between the number of storage data in each E1 signal corresponding cache device, just can judge that the frequency deviation difference between these E1 signals is less; Otherwise just judge that the frequency deviation difference between these E1 signals is bigger;
2. the number of storage data just can judge that less than B judging point number there is negative frequency deviation in its corresponding E1 signal in certain E1 signal corresponding cache device, and the transmission data speed need slow down; Otherwise that just judges this E1 signal does not exist negative frequency deviation;
3. the number of storage data just can judge that greater than D judging point number there is positive frequency deviation in its corresponding E1 signal in certain E1 signal corresponding cache device, needs to accelerate to send data speed; Otherwise that just judges this E1 signal does not exist positive frequency deviation;
4. be in when slowing down state when sending data speed,, judge then that its corresponding E1 signal has returned to not need to slow down to send the state of data speed again if the number of storage data has reached greater than C judging point number in certain E1 signal corresponding cache device;
5. when the transmission data speed is in the quickening state,, judge that then its corresponding E1 signal has returned to the state that does not need to accelerate again to send data speed if the number of storage data has been less than C judging point number in certain E1 signal corresponding cache device;
6. in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is big by 64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is positive frequency deviation;
7. in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is little by-64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is negative frequency deviation;
8. the number of storage data is smaller or equal to 32 (stop data and send judging point A) in the first in first out buffer of certain E1 correspondence, and can judge that the SDH signal of STM-1 does not carry this E1 signal this moment, and this E1 signal is invalid E1 signal, does not participate in above-mentioned judgement; Otherwise this E1 signal is effective E1 signal, participates in above-mentioned judgement.
Among the present invention, data are in transmission course, and the signal of transfer of data is made up of clock signal (CLK), header signal (HEAD), data-signal (DAT[7:0]), characteristic signal (FLAG[1:0]), data useful signal (VALID) etc.Header signal, data-signal, characteristic signal and data useful signal are taken by the clock signal trailing edge at transmitting terminal, receive by rising edge clock signal at receiving terminal, and with the clock signal strict synchronism.As shown in Figure 1.
Clock signal (CLK) is the clock (abbreviation transfer clock) of transmission data, and it follows the tracks of the clock signal of the SDH signal of STM-1, and its clock frequency adopts 19.44MHz.Header signal (HEAD) is represented the original position of a transmission frame during for high level, and each header signal only is high in a clock cycle, it between the correspondence position of two adjacent header signals a transmission cycle (or claiming transmission frame), the position number of header signal correspondence is 0, position number subsequently adds 1 successively until next header signal, and its position number then returns 0 once more.Data-signal (DAT[7:0]) bit wide is 8 bits, and it is the original time slot data transmission channel of each road E1 in the SDH signal of STM-1.Characteristic signal (FLAG[1:0]) bit wide is 2 bits, and it is the transmission channel of the time slot characteristic that obtains after the SDH signal of STM-1 is handled, and its bit wide can be expanded according to application need.Whether corresponding data-signal and the characteristic signal of data useful signal (VALID) expression be effective, when VALID represents that data-signal and characteristic signal are effective during for high level, otherwise invalid.
The data of data are the E1 time slot data of telling from the net load of SDH carrying, and the data of characteristic signal transmission are the characteristics that obtains after by the user E1 time slot data of telling from the net load of SDH carrying being handled.These two kinds of data are to be mutually related, has identical data useful signal, and adopt same clock to take simultaneously/beat in, in a clock cycle, can finish and can only finish the transmission of E1 time slot data and corresponding characteristic thereof, and adopt the validity of same data useful signal designation data and adopt same header signal to indicate them to be in a position in the transmission frame.Therefore, data-signal and characteristic signal not only synchronous transmission but also can independently receive and handle in transmission course.
Be a transmission cycle between the correspondence position of two adjacent header signals, the clock number is 2430 ± 1 in the transmission cycle, and the clock number is identical in continuous at least three transmission cycles.A transmission cycle is divided into three sections: main span line, additional transmitted section and wait span line.Main span line adopts 2106 2016 E1 time slot data of clock cycle transmission and corresponding characteristic thereof, 63 road E1 in the SDH signal of corresponding STM-1 (every road E1 has 32 time slots), i.e. 63 * 32=2016 time slot.The additional transmitted section adopts 253 252 E1 time slot data of clock cycle transmission and corresponding characteristic and frame number data.Be exactly to wait for span line except that main span line and additional transmitted section in the transmission cycle, in waiting for span line, transmitting terminal does not transmit any data, and the duration of wait is determined by SDH signal frame and the E1 signal frequency deviation situation of STM-1.
Can carry 63 road E1 in the SDH signal of STM-1, it is numbered 1 to 63, meets the G.707 coding rule among the FIGURE7-10 in the standard of ITU-T.Every road E1 has 32 time slots, and it is numbered 0 to 31, respectively corresponding TS0 to TS31.Therefore, time-gap number adopts 5bit, and its numbering decimal integer scope is 0≤N
TS≤ 31; The numbering of E1 signal adopts 6bit, and its numbering decimal integer scope is 1≤N
E1≤ 63; The STM-1 numbering adopts 4bit, and its numbering decimal integer scope is 0≤N
STM≤ 15; The spare bits that adds 1bit adopts 16bit to number each time slot among the STM-1 altogether, and is as shown in table 1.
Table 1:STM-1 time slot data coding rule
| The position | 15 | 14∽11 | 10∽5 | 4∽0 |
| Meaning | Idle | The STM-1 numbering | The E1 numbering | Time-gap number |
| Figure place | 1bit | 4bit | 6bit | 5bit |
In main span line, adopt 2106 2016 E1 time slot data of clock cycle transmission and corresponding characteristic thereof, corresponding one group of data of each clock cycle, every group of corresponding position of data, the position number scope is 0 to 2015 integer, the position number of header signal correspondence is 0, and position number subsequently is 1, and the rest may be inferred until position number is 2015.This moment, the pass of position number and STM-1 time slot data number was:
W＝N
TS×63+N
E1-1 (1)
Or:
Wherein, W is a position number, and its decimal integer scope is 0≤W≤2015; N
E1Be the numbering of E1 signal, its decimal integer scope is 1≤N
E1≤ 63; N
TSBe time-gap number, its decimal integer scope is 0≤N
TS≤ 31.Therefore in main span line, can obtain the position number of data in transmission frame by the numbering and the time-gap number of E1 signal, promptly can determine the position of time slot data in transmission frame at transmitting terminal according to arithmetic expression (1); And can promptly can determine the numbering and the time-gap number of its E1 signal according to the position of time slot data in transmission frame by the numbering and the time-gap number of the position number acquisition E1 signal of data in transmission frame at receiving terminal according to arithmetic expression (2).
In the additional transmitted section, adopt 253 252 E1 time slot data of clock cycle transmission and corresponding characteristic and frame number data.Wherein the position number of frame number data corresponds to 2016, and frame number data S is the integer for 0≤S≤7.Its coding rule is:
Table 2: the relation of frame number data S and time-gap number
| S | The time slot scope | S | The |
| 0 | 0≤N TS≤3 | 4 | 16≤N TS≤19 |
| 1 | 4≤N TS≤7 | 5 | 20≤N TS≤23 |
| 2 | 8≤N TS≤11 | 6 | 24≤N TS≤27 |
| 3 | 12≤N TS≤15 | 7 | 28≤N TS≤31 |
W position number 2017 to 2268 corresponding 252 E1 time slot data and corresponding characteristic thereof, the pass of position number and STM-1 time slot data number is:
W＝2016+N
TS×63+N
E1-S×252 (3)
Or:
Wherein, W is a position number, and its decimal integer scope is 2017≤W≤2268; N
E1Be the numbering of E1 signal, its decimal integer scope is 1≤N
E1≤ 63; N
TSBe time-gap number, its decimal integer scope is 0≤N
TS≤ 31; S is a frame number, and its decimal integer scope is 0≤S≤7.Equally in the additional transmitted section, can be according to arithmetic expression (3) by numbering and the time-gap number and the position number of frame number (it is determined by time-gap number) acquisition data in transmission frame of E1 signal, promptly can determine the position of time slot data in transmission frame at transmitting terminal, and can be according to arithmetic expression (4) by the position number and the frame number numbering and the time-gap number that can obtain the E1 signal of data in transmission frame, promptly at receiving terminal according to the position of time slot data in transmission frame and the numbering and the time-gap number of the frame number E1 signal that can determine it.
Additional transmitted Duan Jike adopts it to transmit data also can not adopt its transmission data, and when not adopting additional transmitted section transmission data, its function is consistent with the wait span line.Can be that 2016 frame number S is arranged to 0xffh this moment with position number, promptly when S=0xffh, has only main span line to transmit data in a transmission frame, and all the other are all the wait span line.
Therefore, the present invention may have 63 E1 signals of different frequency deviations in need the SDH signal for STM-1 and carry out convergence processing, so that transmit according to transformat recited above in the aggregate transmission processing procedure.In specific embodiment, be that example is elaborated to it with the SDH signal of STM-1.According to processing mode be divided into the offset frequency situation of E1 signal following several to the checking of actual signal:
There is not frequency deviation between each E1 signal and the transfer clock in the SDH signal of (1) first kind of situation: STM-1.
There is less frequency deviation between each E1 signal and the transfer clock in the SDH signal of (2) second kinds of situation: STM-1.
(3) there is bigger positive frequency deviation in the SDH signal of the third situation: STM-1 between each E1 signal and the transfer clock.
There is bigger negative frequency deviation in the SDH signal of (4) the 4th kinds of situation: STM-1 between each E1 signal and the transfer clock.
There is not frequency deviation between each E1 signal in the SDH signal of (5) the 5th kinds of situation: STM-1.
There is less frequency deviation between each E1 signal in the SDH signal of (6) the 6th kinds of situation: STM-1.
Frequency deviation in the SDH signal of (7) the 7th kinds of situation: STM-1 between most of E1 signal is very little, has only to have bigger positive frequency deviation between the E1 signal of minority E1 signal and remainder.
Frequency deviation in the SDH signal of (8) the 8th kinds of situation: STM-1 between most of E1 signal is very little, has only to have bigger negative frequency deviation between the E1 signal of minority E1 signal and remainder.
Between preceding four kinds of situations or be mutual exclusion between back four kinds of situations, can not comprise each other in these eight kinds of offset frequency situation, but may intersect between preceding four kinds of situations and the back four kinds of situations, bigger but the processing mode of preceding four kinds of situations and back four kinds of situations is distinguished.Their processing mode is as follows:
For above-mentioned one to four kind of situation: they all are the situations of frequency deviation between each E1 signal and the transfer clock in the SDH signal of STM-1.When not having frequency deviation (i.e. first kind of situation) in the SDH of the STM-1 signal between each E1 signal and the transfer clock, each E1 signal and transmit clock signal are homologies in the SDH signal of STM-1 in other words, only adopt main span line transmission data this moment, needn't adopt additional transmitted section transmission data; The clock number is normal 2430 in a transmission cycle, does not need to adjust.When having frequency deviation between each E1 signal and the transfer clock in the SDH of the STM-1 signal, each E1 signal and its transfer clock are not homologies in the SDH signal of STM-1, then need to adjust the frequency deviation between each E1 signal and transfer clock in the SDH signal that clock number in the transmission cycle adapts to STM-1.When having positive frequency deviation between each E1 signal and the transmit clock signal in the SDH of the STM-1 signal, then need to reduce clock number in the transmission cycle to accelerate the transmission of data, the clock number is 2429 in this moment each transmission cycle, and to keep the clock number of three transmission cycles at least continuously be 2429; If the positive frequency deviation that exists between each E1 signal and the transmit clock signal in the SDH signal of STM-1 is big more, then be that the transmission cycle of 2429 clock numbers is just many continuously, on the contrary just few.Simultaneously, when having negative frequency deviation between each E1 signal and the transmit clock signal in the SDH of the STM-1 signal, then need to increase in the transmission cycle clock number with the transmission of the data that slow down, the clock number is 2431 in this moment each transmission cycle, and to keep the clock number of three transmission cycles at least continuously be 2431; If the negative frequency deviation that exists between each E1 signal and the transmit clock signal in the SDH signal of STM-1 is big more, then be that the transmission cycle of 2431 clock numbers is just many continuously, on the contrary just few.Therefore can adapt to the situation that has frequency deviation in the SDH signal of STM-1 between each E1 signal and transmit clock signal by the quantity of adjusting clock number in the transmission cycle and speed transmission cycle.Though for having less frequency deviation between each E1 signal and the transfer clock in the SDH signal of second kind of situation STM-1, may comprise the situation of positive frequency deviation and negative frequency deviation, using above-mentioned method of adjustment is that the quantity of speed transmission cycle is less.For there being bigger positive frequency deviation in the SDH signal of the third situation STM-1 between each E1 signal and the transfer clock, then can use clock number that reduces in the transmission cycle and the quantity that increases the speed transmission cycle to adapt to the situation of this frequency deviation.For there being bigger negative frequency deviation in the SDH signal of the 4th kind of situation STM-1 between each E1 signal and the transfer clock, then can use clock number that increases in the transmission cycle and the quantity that increases the speed transmission cycle to adapt to the situation of this frequency deviation.
For above-mentioned five to eight kinds of situations: they all are the situations of frequency deviation between each E1 signal in the SDH signal of STM-1.When not having frequency deviation between each E1 signal in the SDH of the STM-1 signal, only need to adopt main span line transmission data, needn't adopt additional transmitted section transmission data.When having frequency deviation between each E1 signal in the SDH of the STM-1 signal, no matter how it has two types of positive frequency deviation and negative frequency deviations etc. to the frequency deviation size.For there being the situation of positive frequency deviation in the SDH signal of STM-1 between each E1 signal,, exist the E1 signal of positive frequency deviation the metadata cache overflow may occur and the phenomenon of loss of data more so if only adopt main span line transmission data; Adopt the additional transmitted section to transmit the data that in buffer, accumulate that there is the E1 signal of positive frequency deviation in these, avoid its metadata cache overflow to cause loss of data.Obviously, the positive frequency deviation that exists between each E1 signal in the SDH signal of STM-1 is big more, and then the utilization of additional transmitted section is just frequent more.Equally, the E1 signal number of the positive frequency deviation that exists in the SDH signal of STM-1 is many more, and then the utilization of additional transmitted section is also frequent more.For the situation that has negative frequency deviation in the SDH signal of STM-1 between each E1 signal, if only adopt main span line transmission data and binding data useful signal to adapt to this offset frequency situation, can reach the not purpose of obliterated data, export discontinuous phenomenon but may occur existing the E1 signal of negative frequency deviation the E1 signal to occur.Reaching neither obliterated data if desired, can not occur the output of E1 signal again discontinuous, then need to utilize the clock number in the transmission cycle to adapt to that part of E1 signal that has negative frequency deviation, use the additional transmitted section to adapt to not exist that part of E1 signal of negative frequency deviation then.This obliterated data that reaches neither can not occur the E1 signal again to export discontinuous transmission method comparatively complicated, and also can select the suitable buffer degree of depth to solve by receiving terminal.Example of the present invention adopts the above-mentioned not transmission method of obliterated data of only considering.From the above mentioned,,, only need to adopt main span line transmission data, needn't adopt the additional transmitted section owing to do not have frequency deviation between each E1 signal in the SDH signal of STM-1 for the 5th kind of situation.For the 6th kind of situation, though have less frequency deviation between each E1 signal in the SDH signal of STM-1, may comprise to exist between the E1 signal and exist negative frequency deviation and a part of E1 signal to show as the situation that positive frequency deviation another part E1 signal shows as negative frequency deviation between positive frequency deviation, the E1 signal; No matter which kind of situation can adopt main span line and adapt to it in conjunction with the method for additional transmitted section for the part that has positive frequency deviation E1 signal; Can adopt the method for main span line and binding data useful signal to adapt to its (not requiring the continuous output of E1 signal) for the part that has negative frequency deviation E1 signal; For the situation that positive frequency deviation and negative frequency deviation all exist, then use multiple means such as main span line, additional transmitted section and data useful signal to adapt to it respectively.Similar for the 7th kind of situation and the processing method of less positive frequency deviation that exists noted earlier, just for there being the bigger that part of E1 signal of positive frequency deviation, it is frequent that utilization additional transmitted section is transmitted the meeting of the data that accumulate in its buffer.Equally, similar for the 8th kind of situation and the processing method of less negative frequency deviation that exists noted earlier, just for there being the bigger that part of E1 signal of negative frequency deviation, the maintenance data useful signal indicates its meeting of invalid time frequent.
Can use VHDL (advanced hardware descriptive language) programming FPGA (field programmable device) to realize that a device is realized the SDH Signal Processing of one road STM-1 in the specific embodiment of the invention, its transmitting terminal is realized block diagram as shown in Figure 2.
Send in the processing at SDH signal one road STM-1, at first set up respectively corresponding each the road E1 signal of 63 FIFO (first in first out) buffer, the degree of depth of buffer is chosen as 512, and width is 8 digit time slot data+2 characteristic (can widen according to actual needs)+6 effective designation datas of E1 numbering+5 digit time slots numbering+1 bit data.Set up the convergence processing module then, in the convergence processing module, number and situation of change according to storage data in the buffer are determined eight kinds of offset frequency situation of above-mentioned E1 signal, determine buffer is handled (as: whether certain FIFO buffer being read) accordingly thus, adopt sequential loop to read mode the mode that reads of buffer.The E1 numbering and the time-gap number that read determine that by arithmetic expression (1) or (3) time slot data and characteristic deposit the address (position) in the output storage in, and the effective designation data of the data that read determines that current time slot data and characteristic and data effectively indicate whether to deposit in output storage.Output storage is made up of A and two identical memories of B, and the address realm of each memory is 0 to 4095, and the data-interface width is 8 digit time slot data+2 characteristic (can widen according to actual needs)+effective designation datas of 1 bit data; Two memories of A and B take ping-pong to carry out read-write operation, promptly when a memory is in the convergence processing module and carries out write operation, another memory must be in after the read operation of data outputting module and the read operation clear operation immediately following a memory cell.The address realm of output storage read-write operation is 0 to 2268.Data outputting module address realm from output storage is that 0 to 2268 position is read the effective designation data of time slot data and characteristic and data and is sent to DAT[7:0 in the interface respectively], FLAG[1:0] and VALID, send a high level signal for header signal (HEAD) when simultaneously the address is 0 data in sending output storage, to remain low level be 0 data up to send address in the output storage next time to header signal (HEAD) always subsequently.After having sent 2268 data, transmission frame enters waits for section, DAT[7:0 in waiting for section], FLAG[1:0], signals such as VALID and HEAD all send low level signal, begin up to next transmission frame, another enters new transmission processing procedure, when noting simultaneously not adopting the additional transmitted section, be 2016 places, data-signal DAT[7:0 at position number] data that send are 0xffh.
For the number of storage data in 63 first in first out buffers with change the offset frequency situation that the speed situation is judged the E1 signal, concrete mode as shown in Figure 3, at first to the number of storage data in the buffer be provided with several judging points (A B C D).Wherein the A point sends judging point for stopping data, is arranged on the buffer degree of depth 1/16 place; The B point is arranged on the buffer degree of depth 1/4 place for the beginning or the data transmission judging point that slows down; The C point is arranged on the buffer degree of depth 1/2 place for normal data sends judging point; The D point sends judging point for accelerating data, is arranged on the buffer degree of depth 3/4 place.Judgement to storage number of data and situation of change thereof in the first in first out buffer is as follows:
(1) difference keeps being not more than 10 between the number of storage data in all first in first out buffers, just can judge that the frequency deviation difference of these E1 signals is less; Otherwise the frequency deviation difference of just judging these E1 signals is bigger.
(2) number of storage data just can judge that less than B judging point number there is negative frequency deviation in its corresponding E1 signal in certain first in first out buffer, and the transmission data speed need slow down; Otherwise that just judges this E1 signal does not exist negative frequency deviation.
(3) number of storage data just can judge that greater than D judging point number there is positive frequency deviation in its corresponding E1 signal in certain first in first out buffer, needs to accelerate to send data speed; Otherwise that just judges this E1 signal does not exist positive frequency deviation.
(4) be in when slowing down state when sending data speed,, then judge extensive multiple the state of its corresponding E1 signal to the transmission data speed that do not need to slow down again if the number of storage data has reached greater than C judging point number in certain first in first out buffer.
(5) when the transmission data speed is in the quickening state,, judge that then its corresponding E1 signal has returned to the state that does not need to accelerate again to send data speed if the number of storage data has been less than C judging point number in certain first in first out buffer.
(6) in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is big by 64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is positive frequency deviation.
(7) in certain certain time window (for example time span is set to 10 seconds), the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is little by-64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is negative frequency deviation.
(8) in the first in first out buffer of certain E1 correspondence, store the number of data smaller or equal to 32 (stop data and send judging point A), can judge that the SDH signal of STM-1 does not carry this E1 signal this moment, this E1 signal is invalid E1 signal, does not participate in above-mentioned judgement; Otherwise this E1 signal is effective E1 signal, participates in above-mentioned judgement.
According to the judgement of above-mentioned eight kinds of situations, the convergence processing module uses method of the present invention to carry out various operations and processing to each E1 signal in the SDH signal of STM-1, just can reach the situation of the various frequency deviations of E1 signal in the SDH signal that adapts to STM-1.
As shown in Figure 4, it is (as each E1 signal corresponding cache device among Fig. 2) at the buffer of some E1 signals, wherein in " beginning " square frame, finish the accumulation of primary data in the buffer and make the number of storage data in the buffer reach the C judging point, make it be in normal transmission speed state simultaneously.Among the figure each A B C corresponding judgment point in the D judgment value corresponding diagram 3.Wherein " stop to send data ", " accelerate send data speed ", " slow down and send data speed " and square frames such as " recovering normal transmission data speed " finish respectively to the convergence processing module and send corresponding request command.The request command that each road E1 signal of convergence processing module synthesis is sent is handled accordingly.
Transmission method proposed by the invention has varied in the receiving terminal processing mode, this specification is an example with some time slots of selective reception and corresponding characteristic thereof, as shown in Figure 5, this receiver module is made of count pick up device, main span line processing module, additional transmitted section processing module and reception buffer, wherein main span line processing module is that operational formula is different with additional transmitted section processing module, but implementation structure is identical.
The count pick up device receives the HEAD signal, and by the zero clearing of HEAD signal controlling count pick up device, promptly the count pick up device and is counted the clock signal of transmitting terminal output with regard to zero clearing when receiving the HEAD signal.
When count pick up device value less than 2016 the time, main span line processing module work, its utilization arithmetic expression (2) obtains the numbering and the time-gap number of the E1 signal of current reception data, thereby whether the data of determining current reception meet selected time slot, if satisfy then receive these data and corresponding characteristic, and data are sent to reception buffer, otherwise do not receive these data.
Equal at 2016 o'clock in count pick up device value, receive the frame number data of additional transmitted section and pay S, if S 〉=8 then this additional transmitted section is not transmitted data, additional transmitted section processing module does not receive work of treatment; Otherwise additional transmitted section processing module receives work of treatment.When count pick up device value greater than 2016 less than 2268 the time, the utilization arithmetic expression
(4) obtain the numbering and the time-gap number of the E1 signal of current reception data, if satisfy then receive these data and corresponding characteristic, and data are sent to reception buffer, otherwise do not receive these data.
Reception buffer adopts the push-up storage mode, and its bit wide is 8 digit time slot data+2 characteristic (can widen according to actual needs), and its degree of depth can be set to 64 as its degree of depth according to the requirement setting of subsequent treatment.
Claims (3)
1. there is the convergence transmission method of the multi-channel E 1 data of frequency deviation in the SDH signal, it is characterized in that step is:
(1), sets up a first in first out buffer corresponding for each E1 signal, for the number of storage data in each buffer and the offset frequency situation of variation speed situation judgement E1 signal with it;
(2), set up the convergence processing module; According to offset frequency situation between determined each E1 signal and the transfer clock in the step (1), in the convergence processing module, the transmission data procedures is handled accordingly:
1. when not having frequency deviation between each E1 signal and the transfer clock, only adopt main span line transmission data, the clock number is fixed as 2430 in the transmission cycle;
2. when having positive frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that reduces in the transmission cycle and the quantity that increases fast transmission cycle to adapt to this offset frequency situation;
3. when having negative frequency deviation between each E1 signal and the transfer clock, when adopting main span line to transmit data, utilize clock number that increases in the transmission cycle and the quantity that increases slow transmission cycle to adapt to the situation of this frequency deviation;
(3), according to offset frequency situation between determined each E1 signal in the step (1), in the convergence processing module, the transmission data procedures is handled accordingly:
1. when not having frequency deviation between each E1 signal, only adopt main span line transmission data;
2. when having less frequency deviation between each E1 signal, can adopt main span line and adapt in conjunction with the method for additional transmitted section for the part that has positive frequency deviation E1 signal; Can adopt the method for main span line and binding data useful signal to adapt to for the part that has negative frequency deviation E1 signal; For the situation that positive frequency deviation and negative frequency deviation all exist, then use multiple means such as main span line, additional transmitted section and data useful signal to adapt to respectively;
3. the frequency deviation of working as between most of E1 signal is very little, have only when having bigger positive frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less positive frequency deviation, just for there being the bigger that part of E1 signal of positive frequency deviation, it is frequent that utilization additional transmitted section is transmitted the meeting of the data that accumulate in its buffer;
4. between the E1 signal of minority E1 signal and remainder, there is bigger negative frequency deviation, have only when having bigger negative frequency deviation between the E1 signal of minority E1 signal and remainder, similar with the processing method that has less negative frequency deviation, just for there being the bigger that part of E1 signal of negative frequency deviation, the maintenance data useful signal indicates its meeting of invalid time frequent.
2. the convergence transmission method that has the multi-channel E 1 data of frequency deviation in the SDH signal according to claim 1, the determining step that it is characterized in that described E1 signal frequency deviation situation is: at first the number to storage data in the buffer is provided with several judging point A, B, C, D, wherein the A point sends judging point for stopping data, is arranged on the buffer degree of depth 1/16 place; The B point is arranged on the buffer degree of depth 1/4 place for the beginning or the data transmission judging point that slows down; The C point is arranged on the buffer degree of depth 1/2 place for normal data sends judging point; The D point sends judging point for accelerating data, is arranged on the buffer degree of depth 3/4 place, and is as follows to the judgement of the number of storage data in the first in first out buffer and situation of change thereof:
1. difference keeps being not more than 10 between the number of storage data in all first in first out buffers, just can judge that the frequency deviation difference of these E1 signals is less; Otherwise the frequency deviation difference of just judging these E1 signals is bigger;
2. the number of storage data just can judge that less than B judging point number there is negative frequency deviation in its corresponding E1 signal in certain first in first out buffer, and the transmission data speed need slow down; Otherwise that just judges this E1 signal does not exist negative frequency deviation;
3. the number of storage data just can judge that greater than D judging point number there is positive frequency deviation in its corresponding E1 signal in certain first in first out buffer, needs to accelerate to send data speed; Otherwise that just judges this E1 signal does not exist positive frequency deviation;
4. be in when slowing down state when sending data speed,, judge then that its corresponding E1 signal has returned to not need to slow down to send the state of data speed again if the number of storage data has reached greater than C judging point number in certain first in first out buffer;
5. when the transmission data speed is in the quickening state,, judge that then its corresponding E1 signal has returned to the state that does not need to accelerate again to send data speed if the number of storage data has been less than C judging point number in certain first in first out buffer;
6. in certain certain time window, the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is big by 64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is positive frequency deviation;
7. in certain certain time window, the average of storing the data accumulation number when the number of storage data accumulation in the first in first out buffer of certain E1 correspondence in than the first in first out buffer of all E1 correspondences is little by 64, the frequency deviation difference that then can be judged as its corresponding E1 signal is bigger, and is negative frequency deviation;
8. the number of storage data stops data and sends judging point A smaller or equal to 32 in the first in first out buffer of certain E1 correspondence, and can judge that the SDH signal of STM-1 does not carry this E1 signal this moment, and this E1 signal is invalid E1 signal, does not participate in above-mentioned judgement; Otherwise this E1 signal is effective E1 signal, participates in above-mentioned judgement.
3. the convergence transmission method that has the multi-channel E 1 data of frequency deviation in the SDH signal according to claim 1, it is characterized in that: all E1 time slot data in the SDH signal of described STM-1 and corresponding characteristic thereof adopt the validity of same data useful signal designation data, they are in a position in the transmission frame same header signal indication, same clock is taken/is beated in, and adopts main span line, additional transmitted section and the syllogic transmission means of waiting for span line adapt between the SDH signal frame of STM-1 and each E1 signal and the transfer clock or the offset frequency situation between each E1 signal; When being in the wait span line, transmitting terminal does not transmit any data, and the duration of wait is determined by SDH signal frame and the E1 signal frequency deviation situation of STM-1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100353111A CN101087177B (en) | 2007-07-09 | 2007-07-09 | Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100353111A CN101087177B (en) | 2007-07-09 | 2007-07-09 | Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101087177A CN101087177A (en) | 2007-12-12 |
| CN101087177B true CN101087177B (en) | 2010-12-29 |
Family
ID=38937970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100353111A Expired - Fee Related CN101087177B (en) | 2007-07-09 | 2007-07-09 | Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101087177B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108798922B (en) * | 2017-04-27 | 2021-03-26 | 比亚迪股份有限公司 | Engine air flow sampling method and system and automobile |
| CN108988849B (en) * | 2018-06-22 | 2019-05-28 | 西安邮电大学 | E1 tributary signal output smoothing phaselocked loop and dividing method in SDH system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001047158A1 (en) * | 1999-12-20 | 2001-06-28 | Kabushiki Kaisha Toshiba | Transmitter and tributary interface board |
| CN1581758A (en) * | 2003-08-14 | 2005-02-16 | 华为技术有限公司 | Transmission method for realizing multi-port arbitrary rate integration |
| CN1988526A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Synchronizing method for multiple input multiple output orthogonal frequency division multiplex radio system |
-
2007
- 2007-07-09 CN CN2007100353111A patent/CN101087177B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001047158A1 (en) * | 1999-12-20 | 2001-06-28 | Kabushiki Kaisha Toshiba | Transmitter and tributary interface board |
| CN1581758A (en) * | 2003-08-14 | 2005-02-16 | 华为技术有限公司 | Transmission method for realizing multi-port arbitrary rate integration |
| CN1988526A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Synchronizing method for multiple input multiple output orthogonal frequency division multiplex radio system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101087177A (en) | 2007-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0241113B1 (en) | Traffic scheduler for multiple access communication channels | |
| US20070214291A1 (en) | Elasticity buffer for streaming data | |
| US3519750A (en) | Synchronous digital multiplex communication system including switchover | |
| EP1958404B1 (en) | Alignment and deskew for multiple lanes of serial interconnect | |
| KR910001743B1 (en) | Data multiplex transmission system | |
| US6631138B1 (en) | Reduced pin-count 10Base-T MAC to transceiver interface | |
| US7756028B2 (en) | Pulsed backpressure mechanism for reduced FIFO utilization | |
| JP2003037572A (en) | Scheduling system | |
| CN101087177B (en) | Convergence transmission method of multi-channel E1 data with frequency deviation in SDH signals | |
| CN108304335A (en) | A method of the indefinite long message of serial ports is received by DMA | |
| CN103425614B (en) | Synchronous serial data dispensing device and method thereof for Single Chip Microcomputer (SCM) system | |
| CN101529806A (en) | Methods and apparatus for deskewing VCAT/LCAS members | |
| US8848526B1 (en) | Network processor with traffic shaping response bus interface | |
| US4270203A (en) | Timing adjustment circuit for digital switching | |
| US6882661B1 (en) | System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate | |
| CN105933244B (en) | A kind of device and method that deflection is gone in channel alignment | |
| US20080209064A1 (en) | System and Method For Transmitting Data | |
| EP1091289B1 (en) | Device for processing sonet or SDH frames-DS0 to channel mapping | |
| CN102238436A (en) | Method and device for processing data in optical transmission | |
| EP1221647A1 (en) | Virtual insertion of cells from a secondary source into a fifo | |
| JPH05260120A (en) | Method and system for transmitting communication information by variable length data block on transmission link of asynchronous time division multiplex system | |
| JP2002101133A (en) | Handling of long packet | |
| JP2959448B2 (en) | Time-division multiplex highway ATM interface device | |
| CN108964931A (en) | A kind of downstream packet scheduling Ethernet energy-saving scheme based on mixing sleep pattern | |
| JP4387530B2 (en) | Wireless base station equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101229 Termination date: 20120709 |